write cr0 when op.write_cr.ok is set

diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py
index dfc2cd632cba57d15d3dc1d6b9a1a795e82a2bf1..1faa1ee6015babb747829584fc00e7cbb63790e7 100644 (file)
--- a/src/soc/fu/common_output_stage.py
+++ b/src/soc/fu/common_output_stage.py
@@ -63,7 +63,7 @@ class CommonOutputStage(PipeModBase):
         comb += self.o.o.data.eq(o)
         comb += self.o.o.ok.eq(self.i.o.ok)
         comb += self.o.cr0.data.eq(cr0)
-        comb += self.o.cr0.ok.eq((op.rc.rc & op.rc.rc_ok) | is_cmp | is_cmpeqb)
+        comb += self.o.cr0.ok.eq(op.write_cr.ok)
         # CR0 to be set
         comb += self.o.ctx.eq(self.i.ctx)
 

diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py
index 093c5fc70d71590e7b5aa91e70abc774c53621ca..049a276ed4819fac7a15864b74e8200ee07dc0c4 100644 (file)
--- a/src/soc/fu/compunits/test/test_alu_compunit.py
+++ b/src/soc/fu/compunits/test/test_alu_compunit.py
@@ -230,6 +230,7 @@ class TestRunner(FHDLTestCase):
         cridx = yield dec2.e.write_cr.data
 
         if rc:
+            self.assertEqual(cridx_ok, 1, code)
             self.assertEqual(cridx, 0, code)
 
         if cridx_ok: