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author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Thu, 11 Nov 2021 16:14:58 +0000
(16:14 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Thu, 11 Nov 2021 16:14:58 +0000
(16:14 +0000)
src/soc/simple/core.py
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diff --git
a/src/soc/simple/core.py
b/src/soc/simple/core.py
index d01490648a0ff8d603168551627a300f24a3026b..8082976116f7796346d78236d834ccab8ced5afb 100644
(file)
--- a/
src/soc/simple/core.py
+++ b/
src/soc/simple/core.py
@@
-647,7
+647,7
@@
class NonProductionCore(ControlBase):
print(" %s" % regname, wid, read, write, rdflag)
for (funame, fu, idx) in fuspec:
fusig = fu.src_i[idx] if readmode else fu.dest[idx]
- print(" ", funame, fu, idx, fusig)
+ print(" ", funame, fu
.__class__.__name__
, idx, fusig)
print()
return byregfiles, byregfiles_spec