test case for MMU SPRs: PID and PRTBL

diff --git a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
index 9d1836e51ae3bf5cc399e5237fb599d4dc296559..5037ceba4cdd464e204d137297588dba81cb3705 100644 (file)
--- a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
+++ b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
@@ -21,10 +21,14 @@ class MMUTestCase(TestAccumulatorBase):
                 "mtspr 19, 2",     # reg 2 to DAR
                 "mfspr 1, 18",     # DSISR to reg 1
                 "mfspr 2, 19",     # DAR to reg 2
+                "mtspr 48, 3",    # set MMU PID
+                "mtspr 720, 4",    # set MMU PRTBL
                 "lhz 3, 0(1)"      # load some data
               ]
 
         initial_regs = [0] * 32
+        initial_regs[3] = 1
+        initial_regs[4] = 0xDEADBEEF
         #initial_regs[1] = 0xDEADBEEF
 
         #FIXME initial_sprs = {'DSISR': 0x12345678, 'DAR': 0x87654321}

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index add184fb66b27a71c5b6b1630ce6f411864f5ceb..f3b439506a1fc47e1976b3c076e375795c1db34b 100644 (file)
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -332,7 +332,10 @@ class TestRunner(FHDLTestCase):
             traces += [
                 {'comment': 'microwatt_mmu'},
                 'core.fus.mmu0.alu_mmu0.illegal',
-                'core.fus.mmu0.alu_mmu0.debug0[3:0]'
+                'core.fus.mmu0.alu_mmu0.debug0[3:0]',
+                'core.fus.mmu0.alu_mmu0.mmu.state',
+                'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
+                'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]'
             ]
 
         write_gtkw("issuer_simulator.gtkw",