first attempt running cxxsim

diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index 6e48cb2c22312691a0e11f7b26ef75e858e6cea0..bbd496ba3204e2afcef2283bff963706b5db3bd9 100644 (file)
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -1,5 +1,10 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.back.pysim import Delay, Settle
+cxxsim = True
+if cxxsim:
+    from nmigen.sim.cxxsim import Simulator
+else:
+    from nmigen.back.pysim import Simulator
 from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 import unittest
@@ -256,9 +261,13 @@ class TestRunner(FHDLTestCase):
                     break
 
         sim.add_sync_process(process)
-        with sim.write_vcd("simulator.vcd", "simulator.gtkw",
-                            traces=[]):
+        print (dir(sim))
+        if cxxsim:
             sim.run()
+        else:
+            with sim.write_vcd("simulator.vcd", "simulator.gtkw",
+                                traces=[]):
+                sim.run()
 
     def check_alu_outputs(self, alu, dec2, sim, code):