OP_CMP is requesting a change of the output register (should not do that)

diff --git a/src/soc/fu/alu/formal/proof_main_stage.py b/src/soc/fu/alu/formal/proof_main_stage.py
index 0257d6f001225e11eb8234eedcb45c33929df1eb..08e742597d965234eb0bf523a8c14d8aff6f40cd 100644 (file)
--- a/src/soc/fu/alu/formal/proof_main_stage.py
+++ b/src/soc/fu/alu/formal/proof_main_stage.py
@@ -116,6 +116,7 @@ class Driver(Elaboratable):
                 # CMP is defined as not taking in carry
                 comb += Assume(ca_in == 0)
                 comb += Assert(o == (a+b)[0:64])
+                comb += o_ok.eq(0) # must not change output reg
 
             with m.Case(InternalOp.OP_CMPEQB):
                 src1 = a[0:8]

diff --git a/src/soc/fu/alu/main_stage.py b/src/soc/fu/alu/main_stage.py
index 8b05976f0d31b674f37596c972e6ef87d6186d9e..1d0f34326f04cbc47a21de9eb32722ec42733695 100644 (file)
--- a/src/soc/fu/alu/main_stage.py
+++ b/src/soc/fu/alu/main_stage.py
@@ -61,6 +61,7 @@ class ALUMainStage(PipeModBase):
                 # MUXes to invert a and b, or messing with a 64-bit output,
                 # swap +ve and -ve test in the *output* stage using an XOR gate
                 comb += o.data.eq(add_o[1:-1])
+                comb += o.ok.eq(0) # use o.data but do *not* actually output
 
             #### add ####
             with m.Case(InternalOp.OP_ADD):

diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py
index ac635363444e6bf8018f1ae2d6fa09e806f4ddd5..e38a7058fb6f163ad94112665acb425e2d52eb4a 100644 (file)
--- a/src/soc/fu/compunits/test/test_alu_compunit.py
+++ b/src/soc/fu/compunits/test/test_alu_compunit.py
@@ -178,6 +178,13 @@ class TestRunner(FHDLTestCase):
                     # reset read-operand mask
                     rdmask = yield from get_cu_rd_mask(pdecode2)
                     yield cu.rdmaskn.eq(~rdmask)
+                    # reset write-operand mask
+                    for idx in range(cu.n_dst):
+                        wrok = cu.get_out(idx)
+                        fname = find_ok(wrok.fields)
+                        yield getattr(wrok, fname).eq(0)
+
+                    # set operand and inputs
                     yield from set_operand(cu, pdecode2, sim)
                     rd_rel_o = yield cu.rd.rel
                     wr_rel_o = yield cu.wr.rel
@@ -191,11 +198,17 @@ class TestRunner(FHDLTestCase):
                     wrmask = yield cu.wrmask
                     print ("after inputs, rd_rel, wr_rel, wrmask: ",
                             bin(rd_rel_o), bin(wr_rel_o), bin(wrmask))
+
+                    # call simulated operation
                     opname = code.split(' ')[0]
                     yield from sim.call(opname)
                     index = sim.pc.CIA.value//4
 
                     out_reg_valid = yield pdecode2.e.write_reg.ok
+                    wrmask = yield cu.wrmask
+                    assert bool(wrmask&0b1) == out_reg_valid, \
+                       "write-mask mismatch %s %d" % \
+                        (bin(wrmask), out_reg_valid)
                     yield
                     yield
                     yield
@@ -217,8 +230,8 @@ class TestRunner(FHDLTestCase):
                         for i in range(cu.n_dst):
                             wr_rel_o = yield cu.wr.rel[i]
                             if wr_rel_o:
-                                print ("discard output", i)
                                 discard = yield from get_cu_output(cu, i, code)
+                                print ("discard output", i, hex(discard))
                         yield
 
         sim.add_sync_process(process)
@@ -255,8 +268,10 @@ class TestRunner(FHDLTestCase):
             self.assertEqual(expected_carry32, real_carry32, code)
 
         # TODO
-        #xer_ov = yield from get_cu_output(cu, 3, code)
-        #xer_so = yield from get_cu_output(cu, 4, code)
+        oe = yield dec2.e.oe.data
+        if oe:
+            xer_ov = yield from get_cu_output(cu, 3, code)
+            xer_so = yield from get_cu_output(cu, 4, code)
 
 
 if __name__ == "__main__":