convert power_decoder2 Data to Record-based

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 5524ce1e9e431ebff0e96519e97788a6b7b6def2..63da54972df3b7442e1fda2826195b8a45740294 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -3,7 +3,7 @@
 based on Anton Blanchard microwatt decode2.vhdl
 
 """
-from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl
+from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
 from nmigen.cli import rtlil
 
 from soc.decoder.power_decoder import create_pdecode
@@ -61,16 +61,17 @@ class DecodeA(Elaboratable):
 
         return m
 
-class Data:
 
-    def __init__(self, width, name):
-
-        self.data = Signal(width, name=name, reset_less=True)
-        self.ok = Signal(name="%s_ok" % name, reset_less=True)
+class Data(Record):
 
-    def eq(self, rhs):
-        return [self.data.eq(rhs.data),
-                self.ok.eq(rhs.ok)]
+    def __init__(self, width, name):
+        name_ok = "%s_ok" % name
+        layout = ((name, width), (name_ok, 1))
+        Record.__init__(self, layout)
+        self.data = getattr(self, name) # convenience
+        self.ok = getattr(self, name_ok) # convenience
+        self.data.reset_less = True # grrr
+        self.reset_less = True # grrr
 
     def ports(self):
         return [self.data, self.ok]
@@ -343,6 +344,7 @@ class Decode2ToExecute1Type:
                 self.imm_data.ports()
                 # + self.xerc.ports()
 
+
 class PowerDecode2(Elaboratable):
 
     def __init__(self, dec):