class PartitionTestCase(FHDLTestCase):
def test_formal(self):
+ style = {
+ 'dec': {'base': 'dec'},
+ 'bin': {'base': 'bin'}
+ }
traces = [
- ('p_offset[2:0]', {'base': 'dec'}),
- ('p_width[3:0]', {'base': 'dec'}),
- ('p_finish[3:0]', {'base': 'dec'}),
- ('p_gates[8:0]', {'base': 'bin'}),
+ ('p_offset[2:0]', 'dec'),
+ ('p_width[3:0]', 'dec'),
+ ('p_finish[3:0]', 'dec'),
+ ('p_gates[8:0]', 'bin'),
('dut', {'submodule': 'dut'}, [
- ('gates[6:0]', {'base': 'bin'}),
+ ('gates[6:0]', 'bin'),
'output[63:0]']),
'p_output[63:0]', 'expected_3[21:0]']
write_gtkw(
'proof_partition_cover.gtkw',
os.path.dirname(__file__) +
'/proof_partition_formal/engine_0/trace0.vcd',
- traces,
+ traces, style,
module='top',
zoom=-3
)
'proof_partition_bmc.gtkw',
os.path.dirname(__file__) +
'/proof_partition_formal/engine_0/trace.vcd',
- traces,
+ traces, style,
module='top',
zoom=-3
)
self.assertFormal(module, mode="cover", depth=1)
def test_generator(self):
+ style = {
+ 'dec': {'base': 'dec'},
+ 'bin': {'base': 'bin'}
+ }
traces = [
- ('p_offset[2:0]', {'base': 'dec'}),
- ('p_width[3:0]', {'base': 'dec'}),
- ('p_finish[3:0]', {'base': 'dec'}),
- ('p_gates[8:0]', {'base': 'bin'}),
+ ('p_offset[2:0]', 'dec'),
+ ('p_width[3:0]', 'dec'),
+ ('p_finish[3:0]', 'dec'),
+ ('p_gates[8:0]', 'bin'),
('dut', {'submodule': 'dut'}, [
- ('gates[6:0]', {'base': 'bin'}),
+ ('gates[6:0]', 'bin'),
'output[63:0]']),
'p_output[63:0]', 'expected_3[21:0]']
write_gtkw(
'proof_partition_generator_cover.gtkw',
os.path.dirname(__file__) +
'/proof_partition_generator/engine_0/trace0.vcd',
- traces,
+ traces, style,
module='top',
zoom=-3
)
'proof_partition_generator_bmc.gtkw',
os.path.dirname(__file__) +
'/proof_partition_generator/engine_0/trace.vcd',
- traces,
+ traces, style,
module='top',
zoom=-3
)
self.assertFormal(module, mode="cover", depth=1)
def test_partsig_eq(self):
+ style = {
+ 'dec': {'base': 'dec'},
+ 'bin': {'base': 'bin'}
+ }
traces = [
- ('p_offset[2:0]', {'base': 'dec'}),
- ('p_width[3:0]', {'base': 'dec'}),
- ('p_gates[8:0]', {'base': 'bin'}),
+ ('p_offset[2:0]', 'dec'),
+ ('p_width[3:0]', 'dec'),
+ ('p_gates[8:0]', 'bin'),
('eq_1', {'submodule': 'eq_1'}, [
- ('gates[6:0]', {'base': 'bin'}),
+ ('gates[6:0]', 'bin'),
'a[63:0]', 'b[63:0]',
- ('output[7:0]', {'base': 'bin'})])]
+ ('output[7:0]', 'bin')])]
write_gtkw(
'proof_partsig_eq_cover.gtkw',
os.path.dirname(__file__) +
'/proof_partition_partsig_eq/engine_0/trace0.vcd',
- traces,
+ traces, style,
module='top',
zoom=-3
)
'proof_partsig_eq_bmc.gtkw',
os.path.dirname(__file__) +
'/proof_partition_partsig_eq/engine_0/trace.vcd',
- traces,
+ traces, style,
module='top',
zoom=-3
)
class PartitionedEqTestCase(FHDLTestCase):
def test_formal(self):
+ style = {
+ 'dec': {'base': 'dec'},
+ 'bin': {'base': 'bin'}
+ }
traces = [
- ('p_offset[2:0]', {'base': 'dec'}),
- ('p_width[3:0]', {'base': 'dec'}),
- ('p_gates[8:0]', {'base': 'bin'}),
+ ('p_offset[2:0]', 'dec'),
+ ('p_width[3:0]', 'dec'),
+ ('p_gates[8:0]', 'bin'),
('dut', {'submodule': 'dut'}, [
- ('gates[6:0]', {'base': 'bin'}),
+ ('gates[6:0]', 'bin'),
'a[63:0]', 'b[63:0]',
- ('output[7:0]', {'base': 'bin'})]),
+ ('output[7:0]', 'bin')]),
('ripple', {'submodule': 'ripple'}, [
- ('output[7:0]', {'base': 'bin'})]),
- ('p_output[7:0]', {'base': 'bin'}),
- ('expected_3[2:0]', {'base': 'bin'})]
+ ('output[7:0]', 'bin')]),
+ ('p_output[7:0]', 'bin'),
+ ('expected_3[2:0]', 'bin')]
write_gtkw(
'proof_partitioned_eq_cover.gtkw',
os.path.dirname(__file__) +
'/proof_partitioned_eq_formal/engine_0/trace0.vcd',
- traces,
+ traces, style,
module='top',
zoom=-3
)
'proof_partitioned_eq_bmc.gtkw',
os.path.dirname(__file__) +
'/proof_partitioned_eq_formal/engine_0/trace.vcd',
- traces,
+ traces, style,
module='top',
zoom=-3
)
class PartitionedEqTestCase(FHDLTestCase):
def test_formal(self):
+ style = {
+ 'dec': {'base': 'dec'},
+ 'bin': {'base': 'bin'}
+ }
traces = [
- ('p_offset[2:0]', {'base': 'dec'}),
- ('p_width[3:0]', {'base': 'dec'}),
- ('p_gates[8:0]', {'base': 'bin'}),
+ ('p_offset[2:0]', 'dec'),
+ ('p_width[3:0]', 'dec'),
+ ('p_gates[8:0]', 'bin'),
('dut', {'submodule': 'dut'}, [
- ('gates[6:0]', {'base': 'bin'}),
+ ('gates[6:0]', 'bin'),
'a[63:0]', 'b[63:0]',
- ('output[7:0]', {'base': 'bin'})]),
+ ('output[7:0]', 'bin')]),
('ripple', {'submodule': 'ripple'}, [
- ('output[7:0]', {'base': 'bin'})]),
- ('p_output[7:0]', {'base': 'bin'}),
- ('expected_3[2:0]', {'base': 'bin'})]
+ ('output[7:0]', 'bin')]),
+ ('p_output[7:0]', 'bin'),
+ ('expected_3[2:0]', 'bin')]
write_gtkw(
'proof_partitioned_eq_gt_ge_cover.gtkw',
os.path.dirname(__file__) +
'/proof_partitioned_eq_gt_ge_formal/engine_0/trace0.vcd',
- traces,
+ traces, style,
module='top',
zoom=-3
)
'proof_partitioned_eq_gt_ge_bmc.gtkw',
os.path.dirname(__file__) +
'/proof_partitioned_eq_gt_ge_formal/engine_0/trace.vcd',
- traces,
+ traces, style,
module='top',
zoom=-3
)