sigh sorting out litex pin-connections to sdram

diff --git a/libreriscv b/libreriscv
index 91e6ce1716c6bf1fd30c66f012db81b661b5dfc4..a4c2bff3d2f51f4feab0a1fb7624c5f94e80b60a 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 91e6ce1716c6bf1fd30c66f012db81b661b5dfc4
+Subproject commit a4c2bff3d2f51f4feab0a1fb7624c5f94e80b60a

diff --git a/pinmux b/pinmux
index 24c4414dee7455efbdbafb555517020fa405a4f4..18409e43e4385b4c78eeceb5c875153a85a958cb 160000 (submodule)
--- a/pinmux
+++ b/pinmux
@@ -1 +1 @@
-Subproject commit 24c4414dee7455efbdbafb555517020fa405a4f4
+Subproject commit 18409e43e4385b4c78eeceb5c875153a85a958cb

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index d56a524994019f15666762073cae70c60b2a556f..728034de78096f3bd1f4d10f8b7b66463fc7f200 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -38,6 +38,7 @@ def make_wb_slave(prefix, obj):
     return res
 
 def make_pad(res, dirn, name, suffix, cpup, iop):
+    print ("make pad", dirn, name, suffix, cpup, iop)
     cpud, iod = ('i', 'o') if dirn else ('o', 'i')
     res['%s_%s__core__%s' % (cpud, name, suffix)] = cpup
     res['%s_%s__pad__%s' % (iod, name, suffix)] = iop
@@ -99,13 +100,19 @@ def make_jtag_ioconn(res, pin, cpupads, iopads):
     elif iotype == IOType.InTriOut:
         if fn == 'gpio': # sigh decode GPIO special-case
             idx = int(pin[1:])
+            oe_idx = idx
+        elif fn == 'sdr': # sigh
+            idx = int(pin.split('_')[-1])
+            oe_idx = 0
         else:
             idx = 0
+            oe_idx = 0
+        print ("gpio tri", fn, pin, iotype, pin_name, scan_idx, idx)
         cpup, iop = get_field(cpu, "i")[idx], get_field(io, "i")[idx]
         make_pad(res, False, name, "i", cpup, iop)
         cpup, iop = get_field(cpu, "o")[idx], get_field(io, "o")[idx]
         make_pad(res, True, name, "o", cpup, iop)
-        cpup, iop = get_field(cpu, "oe")[idx], get_field(io, "oe")[idx]
+        cpup, iop = get_field(cpu, "oe")[oe_idx], get_field(io, "oe")[oe_idx]
         make_pad(res, True, name, "oe", cpup, iop)
 
     if iotype in (IOType.In, IOType.InTriOut):
@@ -150,6 +157,11 @@ class LibreSoC(CPU):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
+        # used by coriolis2 to connect up IO VSS/VDD to niolib GPIO cell lib
+        if False:
+            self.io_in        = Signal()
+            self.io_out        = Signal()
+
         irq_en = "noirq" not in variant
 
         if irq_en:
@@ -205,6 +217,8 @@ class LibreSoC(CPU):
             o_memerr_o         = Signal(),   # not connected
             o_pc_o             = Signal(64), # not connected
 
+            #o_io_in            = 0, # set io_in signal to False (for niolib)
+            #o_io_out           = 1, # set io_in signal to True (for niolib)
         )
 
         if irq_en:

diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index 4279effcffe2fbf15f877e9b2a1b76beab248dac..93ed3890eb03c8fd7d326cb4d1400d67f090fc40 100755 (executable)
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -372,6 +372,14 @@ class LibreSoCSim(SoCCore):
 
         #ram_init = []
 
+        if False:
+            # for niolib temporary hack
+            io_in = Signal()
+            io_out = Signal()
+
+            self.comb += io_in.eq(self.cpu.io_in)
+            self.comb += io_out.eq(self.cpu.io_out)
+
         # SDRAM ----------------------------------------------------
         if with_sdram:
             sdram_clk_freq   = int(100e6) # FIXME: use 100MHz timings