use register latching in Computation Unit

diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py
index f1322a065e1538c882db9c120bd7c9920271a7da..8039db679b6c02e93ba19a53b8e694f9f54e0c4d 100644 (file)
--- a/src/experiment/compalu.py
+++ b/src/experiment/compalu.py
@@ -2,7 +2,7 @@ from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Elaboratable
 
-from nmutil.latch import SRLatch
+from nmutil.latch import SRLatch, latchregister
 
 
 class ComputationUnitNoDelay(Elaboratable):
@@ -53,22 +53,31 @@ class ComputationUnitNoDelay(Elaboratable):
         m.d.comb += self.busy_o.eq(opc_l.qn) # busy out
         m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.qn) # request release out
 
-        with m.If(src_l.q):
-            m.d.comb += self.alu.a.eq(self.src1_i)
-            m.d.comb += self.alu.b.eq(self.src2_i)
-        with m.Else():
-            m.d.comb += self.alu.a.eq(self.alu.a)
-            m.d.comb += self.alu.b.eq(self.alu.b)
-        #with m.If(opc_l.q): # XXX operand type in at same time as src1/src2
+        # create a latch/register for src1/src2
+        latchregister(m, self.src1_i, self.alu.a, src_l.q)
+        latchregister(m, self.src2_i, self.alu.b, src_l.q)
+        with m.If(src_l.qn):
             m.d.comb += self.alu.op.eq(self.oper_i)
 
+        if False:
+            data_o = Signal(self.rwid, reset_less=True) # Dest register
+            data_r = Signal(self.rwid, reset_less=True) # Dest register
+            with m.If(req_l.q):
+                m.d.comb += data_o.eq(self.alu.o)
+                m.d.sync += data_r.eq(self.alu.o)
+            with m.Else():
+                m.d.comb += data_o.eq(data_r)
+            #with m.If(self.go_wr_i):
+                #m.d.comb += self.data_o.eq(data_o)
+
+
+        # create a latch/register for the operand
+        #latchregister(m, self.oper_i, self.alu.op, opc_l.q)
+
+        # and one for the output from the ALU
         data_o = Signal(self.rwid, reset_less=True) # Dest register
-        data_r = Signal(self.rwid, reset_less=True) # Dest register
-        with m.If(req_l.q):
-            m.d.comb += data_o.eq(self.alu.o)
-            m.d.sync += data_r.eq(self.alu.o)
-        with m.Else():
-            m.d.comb += data_o.eq(data_r)
+        latchregister(m, self.alu.o, data_o, req_l.q)
+
         with m.If(self.go_wr_i):
             m.d.comb += self.data_o.eq(data_o)
 

diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py
index be085c51ad814c02c5446616168659767b6bdfd8..018c8a17a7893a42f5e1faf2d63eaa9ed6af912a 100644 (file)
--- a/src/experiment/cscore.py
+++ b/src/experiment/cscore.py
@@ -305,7 +305,7 @@ def scoreboard_sim(dut, alusim):
 
         yield from alusim.check(dut)
 
-    for i in range(100):
+    for i in range(3):
         src1 = randint(1, dut.n_regs-1)
         src2 = randint(1, dut.n_regs-1)
         while True:

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index c2ec3d89732be9f906daf8cebe1b1d130d8ee24b..12d9e0799337b6b331813be65c5b169ff479e396 100644 (file)
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -306,11 +306,12 @@ def scoreboard_sim(dut, alusim):
             break
             if dest not in [src1, src2]:
                 break
-        #src1 = 7
-        #src2 = 7
+        src1 = 1
+        src2 = 7
         dest = src2
 
         op = randint(0, 1)
+        op = 0
         print ("random %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
         yield from int_instr(dut, alusim, op, src1, src2, dest)
         yield from print_reg(dut, [3,4,5])