%type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srcimm
%type <reg> indirectgenreg indirectregion
%type <reg> immreg src reg32 payload directgenreg_list addrparam region
-%type <reg> region_wh swizzle directgenreg directmsgreg indirectmsgreg
+%type <reg> region_wh directgenreg directmsgreg indirectmsgreg
+%type <integer> swizzle
/* registers */
%type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
$4.vstride,
$4.width,
$4.hstride,
- $5.swizzle,
+ $5,
WRITEMASK_X);
$$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
$4.vstride,
$4.width,
$4.hstride,
- $5.swizzle,
+ $5,
WRITEMASK_X);
}
| srcarcoperandex
swizzle:
%empty
{
- $$.swizzle = BRW_SWIZZLE_NOOP;
+ $$ = BRW_SWIZZLE_NOOP;
}
| DOT chansel
{
- $$.swizzle = BRW_SWIZZLE4($2, $2, $2, $2);
+ $$ = BRW_SWIZZLE4($2, $2, $2, $2);
}
| DOT chansel chansel chansel chansel
{
- $$.swizzle = BRW_SWIZZLE4($2, $3, $4, $5);
+ $$ = BRW_SWIZZLE4($2, $3, $4, $5);
}
;