create lists of latches in each FU, to record the read/write register

numbers required by the FU to read/write to regfiles.

previously, in the FSM-only version, these read/write regnums were
held (globally) by TestIssuer, and because only one instruction was
active, it did not matter.

now with the possibility of multiple instructions being run, it matters
(a lot)

diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index ea99c7b318306ab6c76aa2a6d6c9c1ab4ddfd0f8..be3d4e69c5806dcce1cf68642e0a514ac37249e2 100644 (file)
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -108,6 +108,11 @@ class FunctionUnitBaseSingle(MultiCompUnit):
     note that the rdflags function obtains (dynamically, from instruction
     decoding) which read-register ports are to be requested.  this is not
     ideal (it could be a lot neater) but works for now.
+
+    also note: additional members, fu.rd_latches and fu.wr_latches
+    are replaced, here, by core.py.  those contain the latched
+    read/write register information which the FU needs in order
+    to actually read (and write) the correct register number
     """
 
     def __init__(self, speckls, pipekls, idx):
@@ -118,6 +123,10 @@ class FunctionUnitBaseSingle(MultiCompUnit):
         alu = pipekls(pspec)                     # create actual NNNBasePipe
         self.pspec = pspec
         super().__init__(regspec, alu, opsubset, name=alu_name)  # MultiCompUnit
+        # these are set to None for now: core get_byregfiles fills them in
+        # (for now)
+        self.fu_rdlatches = None
+        self.fu_wrlatches = None
 
 
 ##############################################################

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index a97acde1121e03a0195746c7339b09ca88bd00ac..5ed83a830f7be78ef5c2ce2d227344b1407d3b95 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -831,6 +831,15 @@ class NonProductionCore(ControlBase):
         byregfiles = {}
         byregfiles_spec = {}
         for (funame, fu) in fus.items():
+            # create in each FU a receptacle for the read/write register
+            # hazard numbers.  to be latched in connect_rd/write_ports
+            # XXX better that this is moved into the actual FUs, but
+            # the issue there is that this function is actually better
+            # suited at the moment
+            if readmode:
+                fu.rd_latches = []
+            else:
+                fu.wr_latches = []
             print("%s ports for %s" % (mode, funame))
             for idx in range(fu.n_src if readmode else fu.n_dst):
                 if readmode:
@@ -838,6 +847,7 @@ class NonProductionCore(ControlBase):
                 else:
                     (regfile, regname, wid) = fu.get_out_spec(idx)
                 print("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
+                name = "%s_%s_%s" % (regfile, idx, funame)
                 if readmode:
                     rdflag, read = regspec_decode_read(e, regfile, regname)
                     wrport, write = None, None
@@ -857,6 +867,16 @@ class NonProductionCore(ControlBase):
                 byregfiles[regfile][idx].append(fuspec)
                 byregfiles_spec[regfile][regname][5].append(fuspec)
 
+                # append a latch Signal to the FU's list of latches
+                regidx = len(byregfiles_spec[regfile][regname][5])-1
+                name = "%s_%s_%s_%i" % (regfile, idx, funame, regidx)
+                if readmode:
+                    rdl = Signal.like(read, name="rdlatch_"+name)
+                    fu.rd_latches.append(rdl)
+                else:
+                    wrl = Signal.like(write, name="wrlatch_"+name)
+                    fu.wr_latches.append(wrl)
+
         # ok just print that out, for convenience
         for regfile, spec in byregfiles.items():
             print("regfile %s ports:" % mode, regfile)