""" Base Mix-in for DivPipe*Stage. """
def _elaborate(self, m, platform):
+ m.d.comb += self.o.ctx.eq(self.i.ctx)
m.d.comb += self.o.z.eq(self.i.z)
m.d.comb += self.o.oz.eq(self.i.oz)
m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
- m.d.comb += self.o.ctx.eq(self.i.ctx)
class DivPipeSetupStage(DivPipeBaseStage, DivPipeCoreSetupStage):
ControlBase.__init__(self)
pipechain = []
- max_n_comb_stages = 2 # TODO (depends on how many RS's we want)
+ max_n_comb_stages = 3 # TODO (depends on how many RS's we want)
# to which the answer: "as few as possible"
# is required. too many ReservationStations
# means "big problems".
def roundup(x, mod):
return x if x % mod == 0 else x + mod - x % mod
+
class FPDIVMuxInOut(ReservationStations):
""" Reservation-Station version of FPDIV pipeline.
then be used to change the behaviour of the pipeline.
"""
- def __init__(self, width, num_rows, op_wid=0):
+ def __init__(self, width, num_rows, op_wid=1):
self.id_wid = num_bits(width)
self.pspec = PipelineSpec(width, self.id_wid, op_wid)
# get the standard mantissa width, store in the pspec HOWEVER...