-""" Pipeline and BufferedPipeline examples
+""" Pipeline and BufferedHandshake examples
"""
from singlepipe import (PrevControl, NextControl, ControlBase,
StageCls, Stage, StageChain,
- BufferedPipeline, UnbufferedPipeline, eq)
+ BufferedHandshake, UnbufferedPipeline, eq)
from nmigen import Signal, Module
from nmigen.cli import verilog, rtlil
return i[0] + i[1]
-class ExampleBufPipeAdd(BufferedPipeline):
+class ExampleBufPipeAdd(BufferedHandshake):
""" an example of how to use the buffered pipeline, using a class instance
"""
def __init__(self):
addstage = ExampleAddStage()
- BufferedPipeline.__init__(self, addstage)
+ BufferedHandshake.__init__(self, addstage)
class ExampleStage(Stage):
return i + 1
-class ExampleBufPipe(BufferedPipeline):
+class ExampleBufPipe(BufferedHandshake):
""" an example of how to use the buffered pipeline.
"""
def __init__(self):
- BufferedPipeline.__init__(self, ExampleStage)
+ BufferedHandshake.__init__(self, ExampleStage)
class ExamplePipeline(UnbufferedPipeline):
from nmigen.compat.fhdl.bitcontainer import value_bits_sign
from contextlib import contextmanager
-from singlepipe import eq, StageCls, ControlBase, BufferedPipeline
+from singlepipe import eq, StageCls, ControlBase, BufferedHandshake
from singlepipe import UnbufferedPipeline
for s in self.stages:
print ("stage specs", s, s.inspecs, s.outspecs)
if self.pipetype == 'buffered':
- p = BufferedPipeline(s)
+ p = BufferedHandshake(s)
else:
p = AutoPipe(s, s.assigns)
pipes.append(p)
-""" Pipeline and BufferedPipeline implementation, conforming to the same API.
+""" Pipeline and BufferedHandshake implementation, conforming to the same API.
For multi-input and multi-output variants, see multipipe.
eq:
------------------
A simple stalling clock-synchronised pipeline that has no buffering
- (unlike BufferedPipeline). Data flows on *every* clock cycle when
+ (unlike BufferedHandshake). Data flows on *every* clock cycle when
the conditions are right (this is nominally when the input is valid
and the output is ready).
A stall anywhere along the line will result in a stall back-propagating
- down the entire chain. The BufferedPipeline by contrast will buffer
+ down the entire chain. The BufferedHandshake by contrast will buffer
incoming data, allowing previous stages one clock cycle's grace before
also having to stall.
clock delay, when its stage is a PassThroughStage, it results in a Pipeline
stage that, duh, delays its (unmodified) input by one clock cycle.
- BufferedPipeline:
+ BufferedHandshake:
----------------
nmigen implementation of buffered pipeline stage, based on zipcpu:
return m
-class BufferedPipeline(ControlBase):
+class BufferedHandshake(ControlBase):
""" buffered pipeline stage. data and strobe signals travel in sync.
if ever the input is ready and the output is not, processed data
is shunted in a temporary register.
Note that a stall in one stage will result in the entire pipeline
chain stalling.
- Also that unlike BufferedPipeline, the valid/ready signalling does NOT
+ Also that unlike BufferedHandshake, the valid/ready signalling does NOT
travel synchronously with the data: the valid/ready signalling
combines in a *combinatorial* fashion. Therefore, a long pipeline
chain will lengthen propagation delays.
Note that a stall in one stage will result in the entire pipeline
chain stalling.
- Also that unlike BufferedPipeline, the valid/ready signalling does NOT
+ Also that unlike BufferedHandshake, the valid/ready signalling does NOT
travel synchronously with the data: the valid/ready signalling
combines in a *combinatorial* fashion. Therefore, a long pipeline
chain will lengthen propagation delays.
from example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
from example_buf_pipe import ExamplePipeline, UnbufferedPipeline
from example_buf_pipe import ExampleStageCls
-from example_buf_pipe import PrevControl, NextControl, BufferedPipeline
+from example_buf_pipe import PrevControl, NextControl, BufferedHandshake
from example_buf_pipe import StageChain, ControlBase, StageCls
from singlepipe import UnbufferedPipeline2
from singlepipe import SimpleHandshake
# Test 9
######################################################################
-class ExampleBufPipeChain2(BufferedPipeline):
+class ExampleBufPipeChain2(BufferedHandshake):
""" connects two stages together as a *single* combinatorial stage.
"""
def __init__(self):
stage1 = ExampleStageCls()
stage2 = ExampleStageCls()
combined = StageChain([stage1, stage2])
- BufferedPipeline.__init__(self, combined)
+ BufferedHandshake.__init__(self, combined)
def data_chain2():
UnbufferedPipeline.__init__(self, stage)
-class ExampleLTBufferedPipeDerived(BufferedPipeline):
+class ExampleLTBufferedPipeDerived(BufferedHandshake):
""" an example of how to use the buffered pipeline.
"""
def __init__(self):
stage = LTStageDerived()
- BufferedPipeline.__init__(self, stage)
+ BufferedHandshake.__init__(self, stage)
def test6_resultfn(o_data, expected, i, o):
return i.op1 + i.op2
-class ExampleBufPipeAddClass(BufferedPipeline):
+class ExampleBufPipeAddClass(BufferedHandshake):
""" an example of how to use the buffered pipeline, using a class instance
"""
def __init__(self):
addstage = ExampleAddClassStage()
- BufferedPipeline.__init__(self, addstage)
+ BufferedHandshake.__init__(self, addstage)
class TestInputAdd:
return m
-class ExampleBufDelayedPipe(BufferedPipeline):
+class ExampleBufDelayedPipe(BufferedHandshake):
def __init__(self):
stage = ExampleStageDelayCls(valid_trigger=2)
- BufferedPipeline.__init__(self, stage, stage_ctl=True)
+ BufferedHandshake.__init__(self, stage, stage_ctl=True)
def elaborate(self, platform):
- m = BufferedPipeline.elaborate(self, platform)
+ m = BufferedHandshake.elaborate(self, platform)
m.submodules.stage = self.stage
return m
# Test 13
######################################################################
-class ExampleUnBufDelayedPipe(BufferedPipeline):
+class ExampleUnBufDelayedPipe(BufferedHandshake):
def __init__(self):
stage = ExampleStageDelayCls(valid_trigger=3)
- BufferedPipeline.__init__(self, stage, stage_ctl=True)
+ BufferedHandshake.__init__(self, stage, stage_ctl=True)
def elaborate(self, platform):
- m = BufferedPipeline.elaborate(self, platform)
+ m = BufferedHandshake.elaborate(self, platform)
m.submodules.stage = self.stage
return m
# http://bugs.libre-riscv.org/show_bug.cgi?id=57
######################################################################
-class ExampleBufAdd1Pipe(BufferedPipeline):
+class ExampleBufAdd1Pipe(BufferedHandshake):
def __init__(self):
stage = ExampleStageCls()
- BufferedPipeline.__init__(self, stage)
+ BufferedHandshake.__init__(self, stage)
class ExampleUnBufAdd1Pipe(UnbufferedPipeline):
projects / ieee754fpu.git / commitdiff