correct pin names for HyperRAMResource, indent spi0 core

diff --git a/src/ls2.py b/src/ls2.py
index c664ccc25afc7d64f3a1e75c96b6b1f5fbfdd34d..291b061b8169742bd76f8dd267a472c653fb0279 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -10,6 +10,7 @@
 
 from nmigen import (Module, Elaboratable, DomainRenamer, Record,
                     Signal, Cat, Const, ClockSignal, ResetSignal)
+from nmigen.build.dsl import Attrs
 from nmigen.cli import verilog
 from nmigen.lib.cdc import ResetSynchronizer
 from nmigen_soc import wishbone, memory
@@ -497,15 +498,16 @@ class DDR3SoC(SoC, Elaboratable):
         print (fname)
         self.uart.add_verilog_source(fname, platform)
 
-        # add Tercel verilog source. assumes a directory
-        # structure where ls2 has been checked out in a common
-        # subdirectory as https://git.libre-soc.org/git/microwatt.git
-        raptor_tercel = "../../microwatt/tercel"
-        pth = os.path.split(__file__)[0]
-        pth = os.path.join(pth, raptor_tercel)
-        fname = os.path.abspath(pth)
-        print (fname)
-        self.spi0.add_verilog_source(fname, platform)
+        if hasattr(self, "spi0"):
+            # add Tercel verilog source. assumes a directory
+            # structure where ls2 has been checked out in a common
+            # subdirectory as https://git.libre-soc.org/git/microwatt.git
+            raptor_tercel = "../../microwatt/tercel"
+            pth = os.path.split(__file__)[0]
+            pth = os.path.join(pth, raptor_tercel)
+            fname = os.path.abspath(pth)
+            print (fname)
+            self.spi0.add_verilog_source(fname, platform)
 
         # add the main core
         pth = os.path.split(__file__)[0]
@@ -617,12 +619,12 @@ if __name__ == "__main__":
     # Get HyperRAM pins
     hyperram_pins = None
     if platform is not None and fpga in ['versa_ecp5']:
-        hyperram_ios = HyperRAMResources(cs_n="B1",
-                                         dq="D0 D1 D2 D3 D4 D7 D6 D7",
-                                         rwds="B2", rst_n="B3", ck_p="B4",
-                                         attrs=IOStandard("LVCMOS33"))
-        self.platform.add_extension(hyperram_ios)
-        hyperram_pins = self.platform.request("hyperram")
+        hyperram_ios = HyperRAMResource(0, cs_n="B13",
+                                        dq="E14 C10 B10 E12 D12 A9 D11 D14",
+                                        rwds="C14", rst_n="E13", ck_p="D13",
+                                        attrs=Attrs(IOSTANDARD="LVCMOS33"))
+        platform.add_resources(hyperram_ios)
+        hyperram_pins = platform.request("hyperram")
     else:
         hyperram_pins = HyperRAMPads()