begin dram support for ls2

diff --git a/src/ls2.py b/src/ls2.py
index 41ab7179f0f600d58f13efc619cd5fbebba2ca1b..53c379252f4f6d64db3d329704652b4b0c7cc3e6 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -837,6 +837,7 @@ def build_platform(fpga, firmware):
     dram_cls = {'arty_a7': None,
                  'versa_ecp5': MT41K64M16,
                  'versa_ecp5_85': MT41K64M16,
+                 'orangecrab': MT41K64M16,
                  #'versa_ecp5': MT41K256M16,
                  'ulx3s': None,
                  'sim': MT41K256M16,
@@ -874,7 +875,8 @@ def build_platform(fpga, firmware):
     if fpga == 'ulx3s':
         clk_freq = 40.0e6
     if fpga == 'orangecrab':
-        clk_freq = 40.0e6
+        clk_freq = 40.0e6 # 50 MHz does not work
+        ##dram_clk_freq = 80.0e6 # does not work yet (0 warnings, 2 errors)
 
     # merge dram_clk_freq with clk_freq if the same
     if clk_freq == dram_clk_freq:
@@ -908,7 +910,8 @@ def build_platform(fpga, firmware):
     # get DDR resource pins, disable if clock frequency is below 50 mhz for now
     ddr_pins = None
     if (enable_dram and platform is not None and
-        fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim']): # not yet 'arty_a7',
+        fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim',
+                 'orangecrab']): # not yet 'arty_a7',
         ddr_pins = platform.request("ddr3", 0,
                                     dir={"dq":"-", "dqs":"-"},
                                     xdr={"rst": 4, "clk":4, "a":4,