code-comments

diff --git a/experiments10_verilog/add.py b/experiments10_verilog/add.py
index fa7c2f0d8409c44728c6d439f121f9909b812d22..3e66b26fcd4f19a2c503a6f1ec7ecf8edecad595 100644 (file)
--- a/experiments10_verilog/add.py
+++ b/experiments10_verilog/add.py
@@ -21,7 +21,8 @@ class ADD(Elaboratable):
         self.b      = Signal(width)
         self.f      = Signal(width)
 
-        # set up JTAG
+        # set up JTAG - use an irwidth of 4, up to 16 ircodes (1<<4).
+        # change this to add more Wishbone interfaces: see below
         self.jtag = TAP(ir_width=4)
         self.jtag.bus.tck.name = 'jtag_tck'
         self.jtag.bus.tms.name = 'jtag_tms'