wildcards never ok. update comments

diff --git a/src/crg.py b/src/crg.py
index 195e8fdad79364a690dd71d3e2b9d2c3e59707d3..3cf483f5893bebfe7723da13c3b0553753b8b7a7 100644 (file)
--- a/src/crg.py
+++ b/src/crg.py
@@ -10,7 +10,8 @@
 # under EU Grants 871528 and 957073, under the LGPLv3+ License
 
 
-from nmigen import *
+from nmigen import (Elaboratable, Module, Signal, ClockDomain, Instance,
+                    ClockSignal, ResetSignal)
 
 __ALL__ = ["ECPIX5CRG"]
 
@@ -110,6 +111,7 @@ class PLL(Elaboratable):
             i_CLKI          = self.clkin,
             o_LOCK          = self.locked,
         )
+        # for each clock-out, set additional parameters
         for n, (clk, f, p, m) in sorted(self.clkouts.items()):
             n_to_l = {0: "P", 1: "S", 2: "S2"}
             div    = config["clko{}_div".format(n)]