load bios not 1.bin unit test

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index 4699ac6d78e6f612c55abf1433f2f0e82d2af456..68be7702ebd72ef6d17e7796e8682848bc658578 100755 (executable)
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -50,6 +50,7 @@ class LibreSoCSim(SoCSDRAM):
         #            "hello_world/hello_world.bin"
         ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
                     "tests/1.bin"
+        ram_fname = None
 
         ram_init = []
         if ram_fname: