increase power-on-delay for icarus sim to allow reset to occur

diff --git a/src/ls2.py b/src/ls2.py
index 04a10bff3ea53660305a7ca9863ee506fd6982d7..91d37797a6dc0c6fc69ecbfac7abf49717b33334 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -281,7 +281,7 @@ class DDR3SoC(SoC, Elaboratable):
         pod_bits = 25
         if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim', 'ulx3s']:
             if fpga in ['isim']:
-                pod_bits = 2
+                pod_bits = 6
             self.crg = ECP5CRG(clk_freq, pod_bits)
         if fpga in ['arty_a7']:
             self.crg = ArtyA7CRG(clk_freq)