fix wishbone jtag test to run: results not correct yet

diff --git a/ls180/pre_pnr/run_iverilog_ls180.sh b/ls180/pre_pnr/run_iverilog_ls180.sh
index eae098658c633a07ef7fc4a433c17267c49953df..68bb2663e5b63daf74027b1dcbc55f27dcb8792a 100755 (executable)
--- a/ls180/pre_pnr/run_iverilog_ls180.sh
+++ b/ls180/pre_pnr/run_iverilog_ls180.sh
@@ -7,7 +7,7 @@ make \
   TOPLEVEL=ls180 \
   COCOTB_RESULTS_FILE=results_iverilog_ls180.xml \
   COCOTB_HDL_TIMEUNIT=100ps \
-  TESTCASE="idcode_reset,idcodesvf_reset,boundary_scan_reset" \
+  TESTCASE="idcode_reset,idcodesvf_reset,boundary_scan_reset,wishbone_basic" \
   SIM_BUILD=sim_build_iverilog_ls180
 
 

diff --git a/ls180/pre_pnr/test.py b/ls180/pre_pnr/test.py
index 4c4d722893c44634e10ca0d6be7f975c3270fbcf..b6dd38b6faf9f2f968e7ab969094c3506d57f712 100644 (file)
--- a/ls180/pre_pnr/test.py
+++ b/ls180/pre_pnr/test.py
@@ -301,24 +301,23 @@ def boundary_scan_run(dut):
 
 
 @cocotb.test()
-def test05_wishbone(dut):
+def wishbone_basic(dut):
     """
     Test of an added Wishbone interface
     """
+    clk_period = 100 # 10MHz
+    tck_period = 300 # 3MHz
+
     data_in = BinaryValue()
     # these have to match with soc.debug.jtag.JTAG ircodes
     cmd_MEMADDRESS = BinaryValue("0101")    # 5
     cmd_MEMREAD = BinaryValue("0110")       # 6
     cmd_MEMREADWRITE = BinaryValue("0111")  # 7
 
-    # Run JTAG @ 1MHz
-    jtagclk_period = get_sim_steps(1, "us")
-    master = JTAG_Master(
-        dut.tap_bus__tck, dut.tap_bus__tms, dut.tap_bus__tdi, dut.tap_bus__tdo,
-        clk_period=jtagclk_period, ir_width=3,
-    )
-    # Run main chip @ 10MHz; need to be clocked for WB interface to function
-    cocotb.fork(Clock(dut.clk, 100, "ns").start())
+    info = "Running Wishbone basic test"
+    wrap = yield from setup_sim(dut, info=info, clk_period=clk_period,
+                                run=False)
+    master = yield from setup_jtag(wrap, tck_period = tck_period)
 
     # Load the memory address
     yield master.load_ir(cmd_MEMADDRESS)
@@ -333,12 +332,12 @@ def test05_wishbone(dut):
     yield master.load_ir(cmd_MEMREADWRITE)
     dut._log.info("Writing memory")
 
-    data_in.binstr = "01010101"
+    data_in.binstr = "01010101" * 8
     dut._log.info("  input: {}".format(data_in.binstr))
     yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
 
-    data_in.binstr = "10101010"
+    data_in.binstr = "10101010" * 8
     dut._log.info("  input: {}".format(data_in.binstr))
     yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
@@ -351,7 +350,7 @@ def test05_wishbone(dut):
     dut._log.info("  input: {}".format(data_in.binstr))
     yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
-    assert master.result.binstr == "1100000000000010"
+    assert master.result.binstr == "00000000000000000000000000000"
 
     # Do read and write
     yield master.load_ir(cmd_MEMREADWRITE)
@@ -377,7 +376,7 @@ def test05_wishbone(dut):
     dut._log.info("  input: {}".format(data_in.binstr))
     yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
-    assert master.result.binstr == "1100000000000010"
+    assert master.result.binstr == "00000000000000000000000000010"
 
     # Do read
     yield master.load_ir(cmd_MEMREAD)
@@ -402,7 +401,7 @@ def test05_wishbone(dut):
     dut._log.info("  input: {}".format(data_in.binstr))
     yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
-    assert master.result.binstr == "1100000000000010"
+    assert master.result.binstr == "00000000000000000000000000010"
 
     # Do read
     yield master.load_ir(cmd_MEMREAD) # MEMREAD
@@ -420,6 +419,8 @@ def test05_wishbone(dut):
     assert master.result.binstr == "01010101" * 8
 
     dut._log.info("{!r}".format(wbmem))
+
+
 # demo / debug how to get boundary scan names. run "python3 test.py"
 if __name__ == '__main__':
     pinouts = get_jtag_boundary()