add missing ispec/ospecs

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
index 6cb8711557ef248e74ebde6e3a4d5f9916afe369..9e1541fd0a4dac5965be8d7ba15d745145a77777 100644 (file)
--- a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
@@ -135,6 +135,14 @@ class DivPipeSetupStage(DivPipeBaseStage, DivPipeCoreSetupStage):
         self.pspec = pspec
         DivPipeCoreSetupStage.__init__(self, pspec.core_config)
 
+    def ispec(self):
+        """ Get the input spec for this pipeline stage."""
+        return DivPipeInputData(self.pspec)
+
+    def ospec(self):
+        """ Get the output spec for this pipeline stage."""
+        return DivPipeInterstageData(self.pspec)
+
     def elaborate(self, platform):
         m = DivPipeCoreSetupStage(platform) # XXX TODO: out_do_z logic!
         self._elaborate(m, platform)
@@ -147,6 +155,14 @@ class DivPipeCalculateStage(DivPipeBaseStage, DivPipeCoreCalculateStage):
         self.pspec = pspec
         DivPipeCoreCalculateStage.__init__(self, pspec.core_config, stage_index)
 
+    def ispec(self):
+        """ Get the input spec for this pipeline stage."""
+        return DivPipeInterstageData(self.pspec)
+
+    def ospec(self):
+        """ Get the output spec for this pipeline stage."""
+        return DivPipeInterstageData(self.pspec)
+
     def elaborate(self, platform):
         m = DivPipeCoreCalculateStage(platform) # XXX TODO: out_do_z logic!
         self._elaborate(m, platform)
@@ -159,6 +175,14 @@ class DivPipeFinalStage(DivPipeBaseStage, DivPipeCoreFinalStage):
         self.pspec = pspec
         DivPipeCoreFinalStage.__init__(self, pspec.core_config, stage_index)
 
+    def ispec(self):
+        """ Get the input spec for this pipeline stage."""
+        return DivPipeInterstageData(self.pspec)
+
+    def ospec(self):
+        """ Get the output spec for this pipeline stage."""
+        return DivPipeOutputData(self.pspec)
+
     def elaborate(self, platform):
         m = DivPipeCoreCalculateStage(platform) # XXX TODO: out_do_z logic!
         self._elaborate(m, platform)

diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 68546007dd36ec6678032309d0cf03c9298b418d..eb786ad3a3b91b9a247f96f0ba789a3fcd4d41ca 100644 (file)
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -3,7 +3,7 @@
 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
 """
 
-from nmigen import Module, Signal, Cat, Elaboratable
+from nmigen import Module, Signal, Cat, Elaboratable, Const
 from nmigen.cli import main, verilog
 
 from ieee754.fpcommon.fpbase import (FPNumBaseRecord, Overflow)

diff --git a/src/ieee754/fpdiv/div2.py b/src/ieee754/fpdiv/div2.py
index 295d2d100aded3153eed968c1819776683eb6326..a92043c3117126dc8b5c91969dff9622005dbf58 100644 (file)
--- a/src/ieee754/fpdiv/div2.py
+++ b/src/ieee754/fpdiv/div2.py
@@ -8,7 +8,6 @@ from nmigen.cli import main, verilog
 
 from ieee754.fpcommon.fpbase import FPState
 from ieee754.fpcommon.postcalc import FPAddStage1Data
-from .div0 import FPDivStage0Data # XXX TODO: replace
 
 
 class FPDivStage2Mod(FPState, Elaboratable):

diff --git a/src/ieee754/fpdiv/divstages.py b/src/ieee754/fpdiv/divstages.py
index 914e77232a4d5dee11f62cec4530c867b96c95f1..385743f846fe37cd6d74167d8876ad2fd6d98e84 100644 (file)
--- a/src/ieee754/fpdiv/divstages.py
+++ b/src/ieee754/fpdiv/divstages.py
@@ -21,7 +21,6 @@ from ieee754.div_rem_sqrt_rsqrt.div_pipe import (DivPipeInterstageData,
 # TODO: write these
 from .div0 import FPDivStage0Mod
 from .div2 import FPDivStage2Mod
-from .div0 import FPDivStage0Data
 
 
 class FPDivStagesSetup(FPState, SimpleHandshake):