yield from ALUHelpers.get_xer_so(res, alu, dec2)
yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
- yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2)
+ yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
yield from ALUHelpers.get_sim_xer_ca(sim_o, sim, dec2)
yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
sim_o = {}
yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
- yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2)
+ yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
yield from ALUHelpers.get_sim_xer_ca(sim_o, sim, dec2)
yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
sim_o = {}
yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
- yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2)
+ yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
ALUHelpers.check_int_o(self, res, sim_o, code)
yield from ALUHelpers.get_xer_so(res, alu, dec2)
yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
- yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2)
+ yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
yield from ALUHelpers.get_sim_xer_ca(sim_o, sim, dec2)
yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
yield from ALUHelpers.get_int_o(res, alu, dec2)
yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
- yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2)
+ yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
ALUHelpers.check_int_o(self, res, sim_o, code)
class ALUHelpers:
+ def get_sim_cr_a(res, sim, dec2):
+ cridx_ok = yield dec2.e.read_cr1.ok
+ if cridx_ok:
+ cridx = yield dec2.e.read_cr1.data
+ res['cr_a'] = sim.crl[cridx].get_range().value
+
def get_sim_int_ra(res, sim, dec2):
# TODO: immediate RA zero
reg1_ok = yield dec2.e.read_reg1.ok
write_reg_idx = yield dec2.e.write_reg.data
res['o'] = sim.gpr(write_reg_idx).value
- def get_sim_cr_a(res, sim, dec2):
+ def get_wr_sim_cr_a(res, sim, dec2):
cridx_ok = yield dec2.e.write_cr.ok
if cridx_ok:
cridx = yield dec2.e.write_cr.data