rename get_sim_cr_a to get_wr_sim_cr_a for now

add read-version of get_sim_cr_a

diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index c8ed6e444a130a0fac4cf058c37399e67896111d..62a1d0b692a4977096dd2f1f9c9dc9b305a3f8b0 100644 (file)
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -274,7 +274,7 @@ class TestRunner(FHDLTestCase):
         yield from ALUHelpers.get_xer_so(res, alu, dec2)
 
         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
-        yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
         yield from ALUHelpers.get_sim_xer_ca(sim_o, sim, dec2)
         yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)

diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py
index 5cc1c2a620caf552514bf898bf4ca04e7148392c..514bb0bb28d3eac8c3e689992a80a4ffa87ecaf0 100644 (file)
--- a/src/soc/fu/compunits/test/test_alu_compunit.py
+++ b/src/soc/fu/compunits/test/test_alu_compunit.py
@@ -38,7 +38,7 @@ class ALUTestRunner(TestRunner):
         sim_o = {}
 
         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
-        yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
         yield from ALUHelpers.get_sim_xer_ca(sim_o, sim, dec2)
         yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)

diff --git a/src/soc/fu/compunits/test/test_logical_compunit.py b/src/soc/fu/compunits/test/test_logical_compunit.py
index b3d8a1f798a30b857f7ce6e768b0ecb8b54a374b..e9a201e34047287c577069f43939b60927196c7e 100644 (file)
--- a/src/soc/fu/compunits/test/test_logical_compunit.py
+++ b/src/soc/fu/compunits/test/test_logical_compunit.py
@@ -37,7 +37,7 @@ class LogicalTestRunner(TestRunner):
         sim_o = {}
 
         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
-        yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 
         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
         ALUHelpers.check_int_o(self, res, sim_o, code)

diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index 720b05f2e212231ba30c9e699b5c7ce5bd7f6fb6..5571571b0d920b69e438b4c127334519d7af437b 100644 (file)
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -274,7 +274,7 @@ class TestRunner(FHDLTestCase):
         yield from ALUHelpers.get_xer_so(res, alu, dec2)
 
         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
-        yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
         yield from ALUHelpers.get_sim_xer_ca(sim_o, sim, dec2)
         yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)

diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py
index 6c26cad8a2d8aadd018af7240a4f4a70aa15778a..1d9dfb5067f5dbd9be923c724c8c298d9f6ad1e9 100644 (file)
--- a/src/soc/fu/logical/test/test_pipe_caller.py
+++ b/src/soc/fu/logical/test/test_pipe_caller.py
@@ -234,7 +234,7 @@ class TestRunner(FHDLTestCase):
         yield from ALUHelpers.get_int_o(res, alu, dec2)
 
         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
-        yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 
         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
         ALUHelpers.check_int_o(self, res, sim_o, code)

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index d2505290a4a86caa6853eb2c28c31cff6df694f0..2ca7df638be0a2b204577cc249731202f8917150 100644 (file)
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -27,6 +27,12 @@ class TestCase:
 
 class ALUHelpers:
 
+    def get_sim_cr_a(res, sim, dec2):
+        cridx_ok = yield dec2.e.read_cr1.ok
+        if cridx_ok:
+            cridx = yield dec2.e.read_cr1.data
+            res['cr_a'] = sim.crl[cridx].get_range().value
+
     def get_sim_int_ra(res, sim, dec2):
         # TODO: immediate RA zero
         reg1_ok = yield dec2.e.read_reg1.ok
@@ -137,7 +143,7 @@ class ALUHelpers:
             write_reg_idx = yield dec2.e.write_reg.data
             res['o'] = sim.gpr(write_reg_idx).value
 
-    def get_sim_cr_a(res, sim, dec2):
+    def get_wr_sim_cr_a(res, sim, dec2):
         cridx_ok = yield dec2.e.write_cr.ok
         if cridx_ok:
             cridx = yield dec2.e.write_cr.data