putting in a lot more debug print statements in DCache, investigation

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 208fa14496c699ef50c4c91af98cc19174f021ed..5cf5895cd0e408f2cc447c27b4c497a6db011686 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -621,7 +621,7 @@ class DCache(Elaboratable):
 
         with m.If(m_in.valid):
             comb += r.req.valid.eq(1)
-            comb += r.req.load.eq(~(m_in.tlbie | m_in.tlbld))
+            comb += r.req.load.eq(~(m_in.tlbie | m_in.tlbld))# no invalidate
             comb += r.req.dcbz.eq(0)
             comb += r.req.nc.eq(0)
             comb += r.req.reserve.eq(0)
@@ -634,6 +634,9 @@ class DCache(Elaboratable):
             comb += r.doall.eq(m_in.doall)
             comb += r.tlbld.eq(m_in.tlbld)
             comb += r.mmu_req.eq(1)
+            m.d.sync += Display("    DCACHE req mmu addr %x pte %x ld %d",
+                                 m_in.addr, m_in.pte, r.req.load)
+
         with m.Else():
             comb += r.req.eq(d_in)
             comb += r.req.data.eq(0)
@@ -651,6 +654,9 @@ class DCache(Elaboratable):
                      ~r0.mmu_req):
                 sync += r0.req.data.eq(d_in.data)
                 sync += r0.d_valid.eq(1)
+        with m.If(d_in.valid):
+            m.d.sync += Display("    DCACHE req cache addr %x data %x ld %d",
+                                 r.req.addr, r.req.data, r.req.load)
 
     def tlb_read(self, m, r0_stall, tlb_valid_way,
                  tlb_tag_way, tlb_pte_way, dtlb_valid_bits,
@@ -749,6 +755,15 @@ class DCache(Elaboratable):
             comb += perm_attr.priv.eq(1)
             comb += perm_attr.rd_perm.eq(1)
             comb += perm_attr.wr_perm.eq(1)
+        with m.If(valid_ra):
+            m.d.sync += Display("DCACHE virt mode %d ra %x pte %x",
+                                r0.req.virt_mode, ra, pte)
+            m.d.sync += Display("       perm ref=%d", perm_attr.reference)
+            m.d.sync += Display("       perm chg=%d", perm_attr.changed)
+            m.d.sync += Display("       perm noc=%d", perm_attr.nocache)
+            m.d.sync += Display("       perm prv=%d", perm_attr.priv)
+            m.d.sync += Display("       perm rdp=%d", perm_attr.rd_perm)
+            m.d.sync += Display("       perm wrp=%d", perm_attr.wr_perm)
 
     def tlb_update(self, m, r0_valid, r0, dtlb_valid_bits, tlb_req_index,
                     tlb_hit_way, tlb_hit, tlb_plru_victim, tlb_tag_way,
@@ -932,10 +947,15 @@ class DCache(Elaboratable):
         comb += op.eq(Op.OP_NONE)
         with m.If(go):
             with m.If(~access_ok):
+                m.d.sync += Display("DCACHE access fail valid_ra=%d p=%d rc=%d",
+                                 valid_ra, perm_ok, rc_ok)
                 comb += op.eq(Op.OP_BAD)
             with m.Elif(cancel_store):
+                m.d.sync += Display("DCACHE cancel store")
                 comb += op.eq(Op.OP_STCX_FAIL)
             with m.Else():
+                m.d.sync += Display("DCACHE valid_ra=%d nc=%d ld=%d",
+                                 valid_ra, nc, r0.req.load)
                 comb += opsel.eq(Cat(is_hit, nc, r0.req.load))
                 with m.Switch(opsel):
                     with m.Case(0b101): comb += op.eq(Op.OP_LOAD_HIT)
@@ -1073,8 +1093,8 @@ class DCache(Elaboratable):
 
             # Slow ops (i.e. load miss)
             with m.If(r1.slow_valid):
-                sync += Display("completing MMU load miss, data=%x",
-                                m_out.data)
+                sync += Display("completing MMU load miss, adr=%x data=%x",
+                                r1.req.real_addr, m_out.data)
 
     def rams(self, m, r1, early_req_row, cache_out_row, replace_way):
         """rams

diff --git a/src/soc/experiment/test/test_dcache_tlb.py b/src/soc/experiment/test/test_dcache_tlb.py
index c9793ea642648272b2e8c4dbac444ac4a82cab46..3f32a28143aa819e2332d46e7473bb1e0fd87c40 100644 (file)
--- a/src/soc/experiment/test/test_dcache_tlb.py
+++ b/src/soc/experiment/test/test_dcache_tlb.py
@@ -213,8 +213,13 @@ def dcache_sim(dut, mem):
 
     # Cacheable read of address 4
     data = yield from dcache_load_m(dut, 0x58)
-    addr = yield dut.d_in.addr
-    print ("dcache m_load 0x58", addr)
+    print ("dcache m_load 0x58", hex(data))
+    yield
+    yield
+
+    # Cacheable read of address 4
+    data = yield from dcache_load_m(dut, 0x58)
+    print ("dcache m_load 0x58", hex(data))
     yield
     yield
 

diff --git a/src/soc/experiment/test/test_ldst_pi.py b/src/soc/experiment/test/test_ldst_pi.py
index ee90c585b0496235271d56d22c4e6488f9ba6c54..d460f41ee45dc421f8e39956b6e0438ba9e4df5a 100644 (file)
--- a/src/soc/experiment/test/test_ldst_pi.py
+++ b/src/soc/experiment/test/test_ldst_pi.py
@@ -119,16 +119,15 @@ def ldst_sim(dut):
     yield mmu.rin.prtbl.eq(0x1000000) # set process table
     yield
 
-    addr = 0x10000
-    data = 0
-    print("pi_st")
+    addr = 0x1000
+    print("pi_ld")
 
     # TODO mmu_lookup using port interface
     # set inputs 
-    phys_addr = yield from mmu_lookup(dut, 0x10000)
+    phys_addr = yield from mmu_lookup(dut, addr)
     assert phys_addr == 0x40000
 
-    phys_addr = yield from mmu_lookup(dut, 0x10000)
+    phys_addr = yield from mmu_lookup(dut, addr)
     assert phys_addr == 0x40000
 
     stop = True