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side by side
(parent:
3bd1b71
)
and now for something completely different...
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 23 Jan 2021 19:19:47 +0000
(19:19 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 23 Jan 2021 19:19:47 +0000
(19:19 +0000)
src/soc/sv/trans/svp64.py
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diff --git
a/src/soc/sv/trans/svp64.py
b/src/soc/sv/trans/svp64.py
index 034c2eaec4d87294ec4cd2e2575203dcaa58d77a..7fe923170e0a25e73b5f6d2b348675068c665560 100644
(file)
--- a/
src/soc/sv/trans/svp64.py
+++ b/
src/soc/sv/trans/svp64.py
@@
-410,6
+410,8
@@
class SVP64:
svp64_rm += (srcwid << 6) # srcwid: bits 6-7
svp64_rm += (destwid << 4) # destwid: bits 4-5
+ # nice debug printout. (and now for something completely different)
+ # https://youtu.be/u0WOIwlXE9g?t=146
print ("svp64_rm", hex(svp64_rm), bin(svp64_rm))
print (" mmode 0 :", bin(mmode))
print (" pmask 1-3 :", bin(pmask))