"""Simple sequential shifter
Prev port data:
- * p.data_i.data: value to be shifted
- * p.data_i.shift: shift amount
+ * p.i_data.data: value to be shifted
+ * p.i_data.shift: shift amount
* When zero, no shift occurs.
* On POWER, range is 0 to 63 for 32-bit,
* and 0 to 127 for 64-bit.
* op.sdir: shift direction (0 = left, 1 = right)
Next port data:
- * n.data_o.data: shifted value
+ * n.o_data.data: shifted value
"""
class PrevData:
def __init__(self, width):
- self.data = Signal(width, name="p_data_i")
+ self.data = Signal(width, name="p_i_data")
self.shift = Signal(width, name="p_shift_i")
self.ctx = Dummy() # comply with CompALU API
class NextData:
def __init__(self, width):
- self.data = Signal(width, name="n_data_o")
+ self.data = Signal(width, name="n_o_data")
def _get_data(self):
return [self.data]
self.width = width
self.p = PrevControl()
self.n = NextControl()
- self.p.data_i = Shifter.PrevData(width)
- self.n.data_o = Shifter.NextData(width)
+ self.p.i_data = Shifter.PrevData(width)
+ self.n.o_data = Shifter.NextData(width)
# more pieces to make this example class comply with the CompALU API
self.op = CompFSMOpSubset(name="op")
- self.p.data_i.ctx.op = self.op
- self.i = self.p.data_i._get_data()
- self.out = self.n.data_o._get_data()
+ self.p.i_data.ctx.op = self.op
+ self.i = self.p.i_data._get_data()
+ self.out = self.n.o_data._get_data()
def elaborate(self, platform):
m = Module()
# build the data flow
m.d.comb += [
# connect input and output
- shift_in.eq(self.p.data_i.data),
- self.n.data_o.data.eq(shift_reg),
+ shift_in.eq(self.p.i_data.data),
+ self.n.o_data.data.eq(shift_reg),
# generate shifted views of the register
shift_left_by_1.eq(Cat(0, shift_reg[:-1])),
shift_right_by_1.eq(Cat(shift_reg[1:], 0)),
self.p.o_ready.eq(1),
# keep loading the shift register and shift count
load.eq(1),
- next_count.eq(self.p.data_i.shift),
+ next_count.eq(self.p.i_data.shift),
]
# capture the direction bit as well
m.d.sync += direction.eq(self.op.sdir)
def __iter__(self):
yield self.op.sdir
- yield self.p.data_i.data
- yield self.p.data_i.shift
+ yield self.p.i_data.data
+ yield self.p.i_data.shift
yield self.p.i_valid
yield self.p.o_ready
yield self.n.i_ready
yield self.n.o_valid
- yield self.n.data_o.data
+ yield self.n.o_data.data
def ports(self):
return list(self)
{'comment': 'Shifter Demonstration'},
('prev port', [
('op__sdir', 'in'),
- ('p_data_i[7:0]', 'in'),
+ ('p_i_data[7:0]', 'in'),
('p_shift_i[7:0]', 'in'),
({'submodule': 'p'}, [
('p_i_valid', 'in'),
'count[3:0]',
'shift_reg[7:0]']),
('next port', [
- ('n_data_o[7:0]', 'out'),
+ ('n_o_data[7:0]', 'out'),
({'submodule': 'n'}, [
('n_o_valid', 'out'),
('n_i_ready', 'in')])])]
def send(data, shift, direction):
# present input data and assert i_valid
- yield dut.p.data_i.data.eq(data)
- yield dut.p.data_i.shift.eq(shift)
+ yield dut.p.i_data.data.eq(data)
+ yield dut.p.i_data.shift.eq(shift)
yield dut.op.sdir.eq(direction)
yield dut.p.i_valid.eq(1)
yield
yield
# clear input data and negate p.i_valid
yield dut.p.i_valid.eq(0)
- yield dut.p.data_i.data.eq(0)
- yield dut.p.data_i.shift.eq(0)
+ yield dut.p.i_data.data.eq(0)
+ yield dut.p.i_data.shift.eq(0)
yield dut.op.sdir.eq(0)
def receive(expected):
while not (yield dut.n.o_valid):
yield
# read result
- result = yield dut.n.data_o.data
+ result = yield dut.n.o_data.data
# negate n.i_ready
yield dut.n.i_ready.eq(0)
# check result
class DummyALU(Elaboratable):
def __init__(self, width):
self.p = Dummy() # make look like nmutil pipeline API
- self.p.data_i = Dummy()
- self.p.data_i.ctx = Dummy()
+ self.p.i_data = Dummy()
+ self.p.i_data.ctx = Dummy()
self.n = Dummy() # make look like nmutil pipeline API
- self.n.data_o = Dummy()
+ self.n.o_data = Dummy()
self.p.i_valid = Signal()
self.p.o_ready = Signal()
self.n.i_ready = Signal()
self.o = self.out[0]
self.width = width
# more "look like nmutil pipeline API"
- self.p.data_i.ctx.op = self.op
- self.p.data_i.a = self.a
- self.p.data_i.b = self.b
- self.p.data_i.c = self.c
- self.n.data_o.o = self.o
+ self.p.i_data.ctx.op = self.op
+ self.p.i_data.a = self.a
+ self.p.i_data.b = self.b
+ self.p.i_data.c = self.c
+ self.n.o_data.o = self.o
def elaborate(self, platform):
m = Module()
class ALU(Elaboratable):
def __init__(self, width):
self.p = Dummy() # make look like nmutil pipeline API
- self.p.data_i = Dummy()
- self.p.data_i.ctx = Dummy()
+ self.p.i_data = Dummy()
+ self.p.i_data.ctx = Dummy()
self.n = Dummy() # make look like nmutil pipeline API
- self.n.data_o = Dummy()
+ self.n.o_data = Dummy()
self.p.i_valid = Signal()
self.p.o_ready = Signal()
self.n.i_ready = Signal()
self.cr = self.out[1]
self.width = width
# more "look like nmutil pipeline API"
- self.p.data_i.ctx.op = self.op
- self.p.data_i.a = self.a
- self.p.data_i.b = self.b
- self.n.data_o.o = self.o
- self.n.data_o.cr = self.cr
+ self.p.i_data.ctx.op = self.op
+ self.p.i_data.a = self.a
+ self.p.i_data.b = self.b
+ self.n.o_data.o = self.o
+ self.n.o_data.cr = self.cr
def elaborate(self, platform):
m = Module()
class BranchALU(Elaboratable):
def __init__(self, width):
self.p = Dummy() # make look like nmutil pipeline API
- self.p.data_i = Dummy()
- self.p.data_i.ctx = Dummy()
+ self.p.i_data = Dummy()
+ self.p.i_data.ctx = Dummy()
self.n = Dummy() # make look like nmutil pipeline API
- self.n.data_o = Dummy()
+ self.n.o_data = Dummy()
self.p.i_valid = Signal()
self.p.o_ready = Signal()
self.n.i_ready = Signal()
self.src2_i = Signal(rwid, reset_less=True) # oper2 in
self.busy_o = Signal(reset_less=True) # fn busy out
- self.data_o = Signal(rwid, reset_less=True) # Dest out
+ self.o_data = Signal(rwid, reset_less=True) # Dest out
self.rd_rel_o = Signal(reset_less=True) # release src1/src2 request
# release request out (o_valid)
self.req_rel_o = Signal(reset_less=True)
# output the data from the latch on go_write
with m.If(self.go_wr_i):
- m.d.comb += self.data_o.eq(data_r)
+ m.d.comb += self.o_data.eq(data_r)
return m
yield self.busy_o
yield self.rd_rel_o
yield self.req_rel_o
- yield self.data_o
+ yield self.o_data
def ports(self):
return list(self)
yield
yield dut.go_rd_i.eq(0)
req_rel_o = yield dut.req_rel_o
- result = yield dut.data_o
+ result = yield dut.o_data
print("req_rel", req_rel_o, result)
while True:
req_rel_o = yield dut.req_rel_o
- result = yield dut.data_o
+ result = yield dut.o_data
print("req_rel", req_rel_o, result)
if req_rel_o:
break
yield
yield dut.go_wr_i.eq(1)
yield
- result = yield dut.data_o
+ result = yield dut.o_data
print("result", result)
yield dut.go_wr_i.eq(0)
yield
self.busy_o = cu.busy_o
self.dest = cu._dest
- self.data_o = self.dest[0] # Dest out
+ self.o_data = self.dest[0] # Dest out
self.done_o = cu.done_o
def _mux_op(self, m, sl, op_is_imm, imm, i):
yield self.busy_o
yield self.rd.rel_o
yield self.wr.rel_o
- yield self.data_o
+ yield self.o_data
def ports(self):
return list(self)
Data (outputs)
--------------
- * :data_o: Dest out (LD) - managed by wr[0] go/req
+ * :o_data: Dest out (LD) - managed by wr[0] go/req
* :addr_o: Address out (LD or ST) - managed by wr[1] go/req
* :exc_o: Address/Data Exception occurred. LD/ST must terminate
self.oper_i = cu.oper_i
self.src_i = cu._src_i
- self.data_o = Data(self.data_wid, name="o") # Dest1 out: RT
+ self.o_data = Data(self.data_wid, name="o") # Dest1 out: RT
self.addr_o = Data(self.data_wid, name="ea") # Addr out: Update => RA
self.exc_o = cu.exc_o
self.done_o = cu.done_o
# Data/Address outputs
# put the LD-output register directly onto the output bus on a go_write
- comb += self.data_o.data.eq(self.dest[0])
+ comb += self.o_data.data.eq(self.dest[0])
with m.If(self.wr.go_i[0]):
comb += self.dest[0].eq(ldd_r)
to LDSTOutputData o and o1 respectively.
"""
if i == 0:
- return self.data_o # LDSTOutputData.regspec o
+ return self.o_data # LDSTOutputData.regspec o
if i == 1:
return self.addr_o # LDSTOutputData.regspec o1
# return self.dest[i]
yield self.adr_rel_o
yield self.sto_rel_o
yield self.wr.rel_o
- yield from self.data_o.ports()
+ yield from self.o_data.ports()
yield from self.addr_o.ports()
yield self.load_mem_o
yield self.stwd_mem_o
yield from wait_for(dut.wr.rel_o[0], test1st=True)
yield dut.wr.go.eq(1)
yield
- data = yield dut.data_o
+ data = yield dut.o_data
print(data)
yield dut.wr.go.eq(0)
yield from wait_for(dut.busy_o)
# merge (OR) all integer FU / ALU outputs to a single value
# bit of a hack: treereduce needs a list with an item named "dest_o"
dest_o = treereduce(int_alus)
- m.d.sync += int_dest.data_i.eq(dest_o)
+ m.d.sync += int_dest.i_data.eq(dest_o)
# connect ALUs
for i, alu in enumerate(int_alus):
m.d.comb += alu.go_wr_i.eq(intpick1.go_wr_o[i])
m.d.comb += alu.issue_i.eq(fn_issue_l[i])
# m.d.comb += fn_busy_l[i].eq(alu.busy_o) # XXX ignore, use fnissue
- m.d.comb += alu.src1_i.eq(int_src1.data_o)
- m.d.comb += alu.src2_i.eq(int_src2.data_o)
+ m.d.comb += alu.src1_i.eq(int_src1.o_data)
+ m.d.comb += alu.src2_i.eq(int_src2.o_data)
m.d.comb += if_l[i].req_rel_i.eq(alu.req_rel_o) # pipe out ready
return m
:addr_array_i: an NxN Array of Signals with bits set indicating address
match. bits across the diagonal (addr_array_i[x][x])
will always be set, to indicate "active".
- :data_i: an Nx Array of Records {data: 128 bit, byte_enable: 16 bit}
- :data_o: an Output Record of same type
+ :i_data: an Nx Array of Records {data: 128 bit, byte_enable: 16 bit}
+ :o_data: an Output Record of same type
{data: 128 bit, byte_enable: 16 bit}
"""
self.array_size = array_size
ul = []
for i in range(array_size):
ul.append(DataMergerRecord())
- self.data_i = Array(ul)
- self.data_o = DataMergerRecord()
+ self.i_data = Array(ul)
+ self.o_data = DataMergerRecord()
def elaborate(self, platform):
m = Module()
select = self.addr_array_i[idx][j]
r = DataMergerRecord()
with m.If(select):
- comb += r.eq(self.data_i[j])
+ comb += r.eq(self.i_data[j])
l.append(r)
- comb += self.data_o.data.eq(ortreereduce(l, "data"))
- comb += self.data_o.en.eq(ortreereduce(l, "en"))
+ comb += self.o_data.data.eq(ortreereduce(l, "data"))
+ comb += self.o_data.en.eq(ortreereduce(l, "en"))
return m
for j in range(self.n_units):
inp = self.input_array[j]
- m.d.comb += dm_even.data_i[j].en.eq(inp.bytemask_even)
- m.d.comb += dm_odd.data_i[j].en.eq(inp.bytemask_odd)
- m.d.comb += dm_even.data_i[j].data.eq(inp.data_even)
- m.d.comb += dm_odd.data_i[j].data.eq(inp.data_odd)
+ m.d.comb += dm_even.i_data[j].en.eq(inp.bytemask_even)
+ m.d.comb += dm_odd.i_data[j].en.eq(inp.bytemask_odd)
+ m.d.comb += dm_even.i_data[j].data.eq(inp.data_even)
+ m.d.comb += dm_odd.i_data[j].data.eq(inp.data_odd)
m.d.comb += dm_even.addr_array_i[j].eq(self.addr_match(j,addr_even))
m.d.comb += dm_odd.addr_array_i[j].eq(self.addr_match(j,addr_odd))
- m.d.comb += self.data_odd.eq(dm_odd.data_o.data)
- m.d.comb += self.data_even.eq(dm_even.data_o.data)
+ m.d.comb += self.data_odd.eq(dm_odd.o_data.data)
+ m.d.comb += self.data_even.eq(dm_even.o_data.data)
return m
def data_merger_merge(dut):
# starting with all inputs zero
yield Settle()
- en = yield dut.data_o.en
- data = yield dut.data_o.data
+ en = yield dut.o_data.en
+ data = yield dut.o_data.data
assert en == 0, "en must be zero"
assert data == 0, "data must be zero"
yield
yield dut.addr_array_i[0].eq(0xFF)
for j in range(dut.array_size):
- yield dut.data_i[j].en.eq(1 << j)
- yield dut.data_i[j].data.eq(0xFF << (16*j))
+ yield dut.i_data[j].en.eq(1 << j)
+ yield dut.i_data[j].data.eq(0xFF << (16*j))
yield Settle()
- en = yield dut.data_o.en
- data = yield dut.data_o.data
+ en = yield dut.o_data.en
+ data = yield dut.o_data.data
assert data == 0xff00ff00ff00ff00ff00ff00ff00ff
assert en == 0xff
yield
self.addr_o = Signal(rwid, reset_less=True)
# in/out register data (note: not register#, actual data)
- self.data_o = Signal(rwid, reset_less=True)
+ self.o_data = Signal(rwid, reset_less=True)
self.src1_i = Signal(rwid, reset_less=True)
self.src2_i = Signal(rwid, reset_less=True)
# input operand
# merge (OR) all integer FU / ALU outputs to a single value
if self.units:
- data_o = treereduce(self.units, "data_o")
- comb += self.data_o.eq(data_o)
+ o_data = treereduce(self.units, "o_data")
+ comb += self.o_data.eq(o_data)
if self.ldstmode:
addr_o = treereduce(self.units, "addr_o")
comb += self.addr_o.eq(addr_o)
# branch is active (TODO: a better signal: this is over-using the
# go_write signal - actually the branch should not be "writing")
with m.If(br1.go_wr_i):
- sync += self.branch_direction_o.eq(br1.data_o+Const(1, 2))
+ sync += self.branch_direction_o.eq(br1.o_data+Const(1, 2))
sync += bspec.active_i.eq(0)
comb += bspec.br_i.eq(1)
# branch occurs if data == 1, failed if data == 0
- comb += bspec.br_ok_i.eq(br1.data_o == 1)
+ comb += bspec.br_ok_i.eq(br1.o_data == 1)
for i in range(n_intfus):
# *expected* direction of the branch matched against *actual*
comb += bshadow.s_good_i[i][0].eq(bspec.match_g_o[i])
comb += int_src2.ren.eq(intfus.src2_rsel_o)
# connect ALUs to regfile
- comb += int_dest.data_i.eq(cu.data_o)
- comb += cu.src1_i.eq(int_src1.data_o)
- comb += cu.src2_i.eq(int_src2.data_o)
+ comb += int_dest.i_data.eq(cu.o_data)
+ comb += cu.src1_i.eq(int_src1.o_data)
+ comb += cu.src2_i.eq(int_src2.o_data)
# connect ALU Computation Units
comb += cu.go_rd_i[0:n_intfus].eq(go_rd_o[0:n_intfus])
self.n_regs = n_regs
mqbits = unsigned(int(log(qlen) / log(2))+2)
- self.p_add_i = Signal(mqbits) # instructions to add (from data_i)
+ self.p_add_i = Signal(mqbits) # instructions to add (from i_data)
self.p_o_ready = Signal() # instructions were added
- self.data_i = Instruction._nq(n_in, "data_i")
+ self.i_data = Instruction._nq(n_in, "i_data")
self.busy_o = Signal(reset_less=True) # at least one CU is busy
self.qlen_o = Signal(mqbits, reset_less=True)
comb += iq.p_add_i.eq(self.p_add_i)
comb += self.p_o_ready.eq(iq.p_o_ready)
for i in range(self.n_in):
- comb += eq(iq.data_i[i], self.data_i[i])
+ comb += eq(iq.i_data[i], self.i_data[i])
# take instruction and process it. note that it's possible to
# "inspect" the queue contents *without* actually removing the
# "resetting" done above (insn_i=0) could be re-ASSERTed.
with m.If(iq.qlen_o != 0):
# get the operands and operation
- instr = iq.data_o[0]
+ instr = iq.o_data[0]
imm = instr.imm_data.data
dest = instr.write_reg.data
src1 = instr.read_reg1.data
def __iter__(self):
yield self.p_o_ready
- for o in self.data_i:
+ for o in self.i_data:
yield from list(o)
yield self.p_add_i
sendlen = 1
for idx, instr in enumerate(instrs):
- yield dut.data_i[idx].eq(instr)
+ yield dut.i_data[idx].eq(instr)
insn_type = yield instr.insn_type
fn_unit = yield instr.fn_unit
print("senddata ", idx, insn_type, fn_unit, instr)
dest = instr['write_reg']
insn_type = instr['insn_type']
fn_unit = instr['fn_unit']
- yield dut.data_i[idx].insn_type.eq(insn_type)
- yield dut.data_i[idx].fn_unit.eq(fn_unit)
- yield dut.data_i[idx].read_reg1.data.eq(reg1)
- yield dut.data_i[idx].read_reg1.ok.eq(1) # XXX TODO
- yield dut.data_i[idx].read_reg2.data.eq(reg2)
- yield dut.data_i[idx].read_reg2.ok.eq(1) # XXX TODO
- yield dut.data_i[idx].write_reg.data.eq(dest)
- yield dut.data_i[idx].write_reg.ok.eq(1) # XXX TODO
- yield dut.data_i[idx].imm_data.data.eq(imm)
- yield dut.data_i[idx].imm_data.ok.eq(op_imm)
- di = yield dut.data_i[idx]
+ yield dut.i_data[idx].insn_type.eq(insn_type)
+ yield dut.i_data[idx].fn_unit.eq(fn_unit)
+ yield dut.i_data[idx].read_reg1.data.eq(reg1)
+ yield dut.i_data[idx].read_reg1.ok.eq(1) # XXX TODO
+ yield dut.i_data[idx].read_reg2.data.eq(reg2)
+ yield dut.i_data[idx].read_reg2.ok.eq(1) # XXX TODO
+ yield dut.i_data[idx].write_reg.data.eq(dest)
+ yield dut.i_data[idx].write_reg.ok.eq(1) # XXX TODO
+ yield dut.i_data[idx].imm_data.data.eq(imm)
+ yield dut.i_data[idx].imm_data.ok.eq(op_imm)
+ di = yield dut.i_data[idx]
print("senddata %d %x" % (idx, di))
yield dut.p_add_i.eq(sendlen)
yield
self.addr_o = Signal(rwid, reset_less=True)
# in/out register data (note: not register#, actual data)
- self.data_o = Signal(rwid, reset_less=True)
+ self.o_data = Signal(rwid, reset_less=True)
self.src1_i = Signal(rwid, reset_less=True)
self.src2_i = Signal(rwid, reset_less=True)
# input operand
# protected by a single go_wr. multi-issue requires a bus
# to be inserted here.
if self.units:
- data_o = ortreereduce(self.units, "data_o")
- comb += self.data_o.eq(data_o)
+ o_data = ortreereduce(self.units, "o_data")
+ comb += self.o_data.eq(o_data)
if self.ldstmode:
addr_o = ortreereduce(self.units, "addr_o")
comb += self.addr_o.eq(addr_o)
# branch is active (TODO: a better signal: this is over-using the
# go_write signal - actually the branch should not be "writing")
with m.If(br1.go_wr_i):
- sync += self.branch_direction_o.eq(br1.data_o+Const(1, 2))
+ sync += self.branch_direction_o.eq(br1.o_data+Const(1, 2))
sync += bspec.active_i.eq(0)
comb += bspec.br_i.eq(1)
# branch occurs if data == 1, failed if data == 0
- comb += bspec.br_ok_i.eq(br1.data_o == 1)
+ comb += bspec.br_ok_i.eq(br1.o_data == 1)
for i in range(n_intfus):
# *expected* direction of the branch matched against *actual*
comb += bshadow.s_good_i[i][0].eq(bspec.match_g_o[i])
comb += int_src2.ren.eq(intfus.src_rsel_o[1])
# connect ALUs to regfile
- comb += int_dest.data_i.eq(cu.data_o)
- comb += cu.src1_i.eq(int_src1.data_o)
- comb += cu.src2_i.eq(int_src2.data_o)
+ comb += int_dest.i_data.eq(cu.o_data)
+ comb += cu.src1_i.eq(int_src1.o_data)
+ comb += cu.src2_i.eq(int_src2.o_data)
# connect ALU Computation Units
for i in range(fu_n_src):
self.n_regs = n_regs
mqbits = unsigned(int(log(qlen) / log(2))+2)
- self.p_add_i = Signal(mqbits) # instructions to add (from data_i)
+ self.p_add_i = Signal(mqbits) # instructions to add (from i_data)
self.p_o_ready = Signal() # instructions were added
- self.data_i = Instruction._nq(n_in, "data_i")
+ self.i_data = Instruction._nq(n_in, "i_data")
self.busy_o = Signal(reset_less=True) # at least one CU is busy
self.qlen_o = Signal(mqbits, reset_less=True)
comb += iq.p_add_i.eq(self.p_add_i)
comb += self.p_o_ready.eq(iq.p_o_ready)
for i in range(self.n_in):
- comb += eq(iq.data_i[i], self.data_i[i])
+ comb += eq(iq.i_data[i], self.i_data[i])
# take instruction and process it. note that it's possible to
# "inspect" the queue contents *without* actually removing the
# "resetting" done above (insn_i=0) could be re-ASSERTed.
with m.If(iq.qlen_o != 0):
# get the operands and operation
- instr = iq.data_o[0]
+ instr = iq.o_data[0]
imm = instr.imm_data.data
dest = instr.write_reg.data
src1 = instr.read_reg1.data
def __iter__(self):
yield self.p_o_ready
- for o in self.data_i:
+ for o in self.i_data:
yield from list(o)
yield self.p_add_i
sendlen = 1
for idx, instr in enumerate(instrs):
- yield dut.data_i[idx].eq(instr)
+ yield dut.i_data[idx].eq(instr)
insn_type = yield instr.insn_type
fn_unit = yield instr.fn_unit
print("senddata ", idx, insn_type, fn_unit, instr)
dest = instr['write_reg']
insn_type = instr['insn_type']
fn_unit = instr['fn_unit']
- yield dut.data_i[idx].insn_type.eq(insn_type)
- yield dut.data_i[idx].fn_unit.eq(fn_unit)
- yield dut.data_i[idx].read_reg1.data.eq(reg1)
- yield dut.data_i[idx].read_reg1.ok.eq(1) # XXX TODO
- yield dut.data_i[idx].read_reg2.data.eq(reg2)
- yield dut.data_i[idx].read_reg2.ok.eq(1) # XXX TODO
- yield dut.data_i[idx].write_reg.data.eq(dest)
- yield dut.data_i[idx].write_reg.ok.eq(1) # XXX TODO
- yield dut.data_i[idx].imm_data.data.eq(imm)
- yield dut.data_i[idx].imm_data.ok.eq(op_imm)
- di = yield dut.data_i[idx]
+ yield dut.i_data[idx].insn_type.eq(insn_type)
+ yield dut.i_data[idx].fn_unit.eq(fn_unit)
+ yield dut.i_data[idx].read_reg1.data.eq(reg1)
+ yield dut.i_data[idx].read_reg1.ok.eq(1) # XXX TODO
+ yield dut.i_data[idx].read_reg2.data.eq(reg2)
+ yield dut.i_data[idx].read_reg2.ok.eq(1) # XXX TODO
+ yield dut.i_data[idx].write_reg.data.eq(dest)
+ yield dut.i_data[idx].write_reg.ok.eq(1) # XXX TODO
+ yield dut.i_data[idx].imm_data.data.eq(imm)
+ yield dut.i_data[idx].imm_data.ok.eq(op_imm)
+ di = yield dut.i_data[idx]
print("senddata %d %x" % (idx, di))
yield dut.p_add_i.eq(sendlen)
yield
def set_alu_inputs(alu, dec2, sim):
# TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
# detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
- # and place it into data_i.b
+ # and place it into i_data.b
inp = yield from get_cu_inputs(dec2, sim)
yield from ALUHelpers.set_int_ra(alu, dec2, inp)
pspec = ALUPipeSpec(id_wid=2)
m.submodules.alu = alu = ALUBasePipe(pspec)
- comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
+ comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
comb += alu.n.ready_i.eq(1)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
sim = Simulator(m)
oe_ok = yield dec2.e.do.oe.ok
if not oe or not oe_ok:
# if OE not enabled, XER SO and OV must correspondingly be false
- so_ok = yield alu.n.data_o.xer_so.ok
- ov_ok = yield alu.n.data_o.xer_ov.ok
+ so_ok = yield alu.n.o_data.xer_so.ok
+ ov_ok = yield alu.n.o_data.xer_ov.ok
self.assertEqual(so_ok, False, code)
self.assertEqual(ov_ok, False, code)
pspec = BranchPipeSpec(id_wid=2)
m.submodules.branch = branch = BranchBasePipe(pspec)
- comb += branch.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
+ comb += branch.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
comb += branch.p.valid_i.eq(1)
comb += branch.n.ready_i.eq(1)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
sim.run()
def assert_outputs(self, branch, dec2, sim, prev_nia, code):
- branch_taken = yield branch.n.data_o.nia.ok
+ branch_taken = yield branch.n.o_data.nia.ok
sim_branch_taken = prev_nia != sim.pc.CIA
self.assertEqual(branch_taken, sim_branch_taken, code)
if branch_taken:
- branch_addr = yield branch.n.data_o.nia.data
+ branch_addr = yield branch.n.o_data.nia.data
print(f"real: {branch_addr:x}, sim: {sim.pc.CIA.value:x}")
self.assertEqual(branch_addr, sim.pc.CIA.value, code)
# TODO: this should be checking write_fast2
lk = yield dec2.e.do.lk
- branch_lk = yield branch.n.data_o.lr.ok
+ branch_lk = yield branch.n.o_data.lr.ok
self.assertEqual(lk, branch_lk, code)
if lk:
- branch_lr = yield branch.n.data_o.lr.data
+ branch_lr = yield branch.n.o_data.lr.data
self.assertEqual(sim.spr['LR'], branch_lr, code)
def set_inputs(self, branch, dec2, sim):
# then the alu data should be output
with m.If(Past(wr_rel) & Past(go_wr)):
# the alu data is output
- comb += Assert((dut.data_o == alu_temp)
- | (dut.data_o == dut.alu.o))
+ comb += Assert((dut.o_data == alu_temp)
+ | (dut.o_data == dut.alu.o))
# wr_rel is dropped
comb += Assert(wr_rel == 0)
# busy is dropped.
fast_out2 = yield pdecode2.e.write_fast2.data
fast_out2_ok = yield pdecode2.e.write_fast2.ok
print("lk:", lk, fast_out2, fast_out2_ok)
- op_lk = yield cu.alu.pipe1.p.data_i.ctx.op.lk
+ op_lk = yield cu.alu.pipe1.p.i_data.ctx.op.lk
print("op_lk:", op_lk)
- print(dir(cu.alu.pipe1.n.data_o))
+ print(dir(cu.alu.pipe1.n.o_data))
fn_unit = yield pdecode2.e.do.fn_unit
fuval = self.funit.value
self.assertEqual(fn_unit & fuval, fuval)
# debugging issue with branch
if self.funit == Function.BRANCH:
- lr = yield cu.alu.pipe1.n.data_o.lr.data
- lr_ok = yield cu.alu.pipe1.n.data_o.lr.ok
+ lr = yield cu.alu.pipe1.n.o_data.lr.data
+ lr_ok = yield cu.alu.pipe1.n.o_data.lr.ok
print("lr:", hex(lr), lr_ok)
if self.funit == Function.LDST:
cr_en = yield dec2.e.write_cr.ok
if whole_reg_ok:
- full_cr = yield alu.n.data_o.full_cr.data & full_cr_mask
+ full_cr = yield alu.n.o_data.full_cr.data & full_cr_mask
expected_cr = simulator.cr.value
print("CR whole: expected %x, actual: %x mask: %x" % \
(expected_cr, full_cr, full_cr_mask))
expected_cr = simulator.cr.value
print(f"CR whole: {expected_cr:x}, sel {cr_sel}")
expected_cr = simulator.crl[cr_sel].get_range().value
- real_cr = yield alu.n.data_o.cr.data
+ real_cr = yield alu.n.o_data.cr.data
print(f"CR part: expected {expected_cr:x}, actual: {real_cr:x}")
self.assertEqual(expected_cr, real_cr, code)
- alu_out = yield alu.n.data_o.o.data
+ alu_out = yield alu.n.o_data.o.data
out_reg_valid = yield dec2.e.write_reg.ok
if out_reg_valid:
write_reg_idx = yield dec2.e.write_reg.data
pspec = CRPipeSpec(id_wid=2)
m.submodules.alu = alu = CRBasePipe(pspec)
- comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
+ comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
comb += alu.n.ready_i.eq(1)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
sim = Simulator(m)
def __init__(self, pspec):
super().__init__()
self.pspec = pspec
- self.p.data_i = CoreInputData(pspec)
- self.n.data_o = CoreOutputData(pspec)
+ self.p.i_data = CoreInputData(pspec)
+ self.n.o_data = CoreOutputData(pspec)
self.saved_input_data = CoreInputData(pspec)
self.empty = Signal(reset=1)
self.saved_state = DivState(64, name="saved_state")
m = super().elaborate(platform)
m.submodules.div_state_next = self.div_state_next
m.submodules.div_state_init = self.div_state_init
- data_i = self.p.data_i
- data_o = self.n.data_o
- core_i = data_i.core
- core_o = data_o.core
+ i_data = self.p.i_data
+ o_data = self.n.o_data
+ core_i = i_data.core
+ core_o = o_data.core
core_saved_i = self.saved_input_data.core
m.d.comb += self.div_state_init.dividend.eq(core_i.dividend)
- m.d.comb += data_o.eq_without_core(self.saved_input_data)
+ m.d.comb += o_data.eq_without_core(self.saved_input_data)
m.d.comb += core_o.quotient_root.eq(self.div_state_next.o.quotient)
# fract width of `DivPipeCoreOutputData.remainder`
remainder_fract_width = 64 * 3
m.d.comb += self.div_state_next.divisor.eq(core_i.divisor_radicand)
with m.If(self.p.i_valid):
m.d.sync += self.empty.eq(0)
- m.d.sync += self.saved_input_data.eq(data_i)
+ m.d.sync += self.saved_input_data.eq(i_data)
with m.Else():
m.d.comb += [
self.div_state_next.i.eq(self.saved_state),
def set_alu_inputs(alu, dec2, sim):
# TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
# detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
- # and place it into data_i.b
+ # and place it into i_data.b
inp = yield from get_cu_inputs(dec2, sim)
yield from ALUHelpers.set_int_ra(alu, dec2, inp)
pspec = DivPipeSpec(id_wid=2, div_pipe_kind=div_pipe_kind)
m.submodules.alu = alu = DivBasePipe(pspec)
- comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
+ comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
comb += alu.n.ready_i.eq(1)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
sim = Simulator(m)
print("oe, oe_ok", oe, oe_ok)
if not oe or not oe_ok:
# if OE not enabled, XER SO and OV must not be activated
- so_ok = yield alu.n.data_o.xer_so.ok
- ov_ok = yield alu.n.data_o.xer_ov.ok
+ so_ok = yield alu.n.o_data.xer_so.ok
+ ov_ok = yield alu.n.o_data.xer_ov.ok
print("so, ov", so_ok, ov_ok)
self.assertEqual(ov_ok, False, code)
self.assertEqual(so_ok, False, code)
def set_alu_inputs(alu, dec2, sim):
# TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
# detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
- # and place it into data_i.b
+ # and place it into i_data.b
inp = yield from get_cu_inputs(dec2, sim)
print ("set alu inputs", inp)
pspec = LogicalPipeSpec(id_wid=2)
m.submodules.alu = alu = LogicalBasePipe(pspec)
- comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
+ comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
comb += alu.n.ready_i.eq(1)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
sim = Simulator(m)
self.pspec = pspec
# set up p/n data
- self.p.data_i = MMUInputData(pspec)
- self.n.data_o = MMUOutputData(pspec)
+ self.p.i_data = MMUInputData(pspec)
+ self.n.o_data = MMUOutputData(pspec)
self.mmu = MMU()
self.illegal = Signal()
# for SPR field number access
- i = self.p.data_i
+ i = self.p.i_data
self.fields = DecodeFields(SignalBitRange, [i.ctx.op.insn])
self.fields.create_specs()
comb += l_in.eq(ldst.m_out)
comb += ldst.m_in.eq(l_out)
- data_i, data_o = self.p.data_i, self.n.data_o
- a_i, b_i, o, spr1_o = data_i.ra, data_i.rb, data_o.o, data_o.spr1
- op = data_i.ctx.op
+ i_data, o_data = self.p.i_data, self.n.o_data
+ a_i, b_i, o, spr1_o = i_data.ra, i_data.rb, o_data.o, o_data.spr1
+ op = i_data.ctx.op
msr_i = op.msr
- spr1_i = data_i.spr1
+ spr1_i = i_data.spr1
# these are set / got here *ON BEHALF* of LoadStore1
dsisr, dar = ldst.dsisr, ldst.dar
def set_fsm_inputs(alu, dec2, sim):
# TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
# detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
- # and place it into data_i.b
+ # and place it into i_data.b
print("Error here")
inp = yield from get_cu_inputs(dec2, sim)
#print("oe, oe_ok", oe, oe_ok)
#if not oe or not oe_ok:
# # if OE not enabled, XER SO and OV must not be activated
- # so_ok = yield alu.n.data_o.xer_so.ok
- # ov_ok = yield alu.n.data_o.xer_ov.ok
+ # so_ok = yield alu.n.o_data.xer_so.ok
+ # ov_ok = yield alu.n.o_data.xer_ov.ok
# print("so, ov", so_ok, ov_ok)
# self.assertEqual(ov_ok, False, code)
# self.assertEqual(so_ok, False, code)
#FIXME connect fsm inputs
- comb += fsm.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
+ comb += fsm.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
comb += fsm.p.valid_i.eq(1)
comb += fsm.n.ready_i.eq(1)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
def set_alu_inputs(alu, dec2, sim, has_third_input):
# TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
# detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
- # and place it into data_i.b
+ # and place it into i_data.b
inp = yield from get_cu_inputs(dec2, sim)
print("set alu inputs", inp)
pspec = MulPipeSpec(id_wid=2)
m.submodules.alu = alu = MulBasePipe(pspec)
- comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
+ comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
comb += alu.n.ready_i.eq(1)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
sim = Simulator(m)
oe_ok = yield dec2.e.do.oe.ok
if not oe or not oe_ok:
# if OE not enabled, XER SO and OV must correspondingly be false
- so_ok = yield alu.n.data_o.xer_so.ok
- ov_ok = yield alu.n.data_o.xer_ov.ok
+ so_ok = yield alu.n.o_data.xer_so.ok
+ ov_ok = yield alu.n.o_data.xer_ov.ok
self.assertEqual(so_ok, False, code)
self.assertEqual(ov_ok, False, code)
if isinstance(self.rwid, int): # old - testing - API (rwid is int)
return self.alu.out[i]
# regspec-based API: look up variable through regspec thru row number
- return getattr(self.alu.n.data_o, self.get_out_name(i))
+ return getattr(self.alu.n.o_data, self.get_out_name(i))
def get_in(self, i):
if isinstance(self.rwid, int): # old - testing - API (rwid is int)
return self.alu.i[i]
# regspec-based API: look up variable through regspec thru row number
- return getattr(self.alu.p.data_i, self.get_in_name(i))
+ return getattr(self.alu.p.i_data, self.get_in_name(i))
def get_op(self):
if isinstance(self.rwid, int): # old - testing - API (rwid is int)
return self.alu.op
- return self.alu.p.data_i.ctx.op
+ return self.alu.p.i_data.ctx.op
def set_alu_inputs(alu, dec2, sim):
# TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
# detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
- # and place it into data_i.b
+ # and place it into i_data.b
inp = yield from get_cu_inputs(dec2, sim)
yield from ALUHelpers.set_int_ra(alu, dec2, inp)
yield
vld = yield alu.n.valid_o
yield
- alu_out = yield alu.n.data_o.o.data
+ alu_out = yield alu.n.o_data.o.data
yield from self.check_alu_outputs(alu, pdecode2,
simulator, code)
pspec = ShiftRotPipeSpec(id_wid=2)
m.submodules.alu = alu = ShiftRotBasePipe(pspec)
- comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
+ comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
comb += alu.n.ready_i.eq(1)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
sim = Simulator(m)
def set_alu_inputs(alu, dec2, sim):
# TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
# detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
- # and place it into data_i.b
+ # and place it into i_data.b
inp = yield from get_cu_inputs(dec2, sim)
yield from ALUHelpers.set_int_ra(alu, dec2, inp)
pspec = SPRPipeSpec(id_wid=2)
m.submodules.alu = alu = SPRBasePipe(pspec)
- comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
+ comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
comb += alu.p.valid_i.eq(1)
comb += alu.n.ready_i.eq(1)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
def set_alu_inputs(alu, dec2, sim):
# TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
# detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
- # and place it into data_i.b
+ # and place it into i_data.b
inp = yield from get_cu_inputs(dec2, sim)
yield from ALUHelpers.set_int_ra(alu, dec2, inp)
pspec = TrapPipeSpec(id_wid=2)
m.submodules.alu = alu = TrapBasePipe(pspec)
- comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
+ comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
comb += alu.p.valid_i.eq(1)
comb += alu.n.ready_i.eq(1)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
def read_port(self, name=None):
port = RecordObject([("ren", 1),
- ("data_o", self.width)],
+ ("o_data", self.width)],
name=name)
self._rdports.append(port)
return port
def write_port(self, name=None):
port = RecordObject([("wen", 1),
- ("data_i", self.width)],
+ ("i_data", self.width)],
name=name)
self._wrports.append(port)
return port
# read ports. has write-through detection (returns data written)
for rp in self._rdports:
- domain += rp.data_o.eq(0)
+ domain += rp.o_data.eq(0)
with m.If(rp.ren):
if self.writethru:
wr_detect = Signal(reset_less=False)
m.d.comb += wr_detect.eq(0)
for wp in self._wrports:
with m.If(wp.wen):
- domain += rp.data_o.eq(wp.data_i)
+ domain += rp.o_data.eq(wp.i_data)
m.d.comb += wr_detect.eq(1)
with m.If(~wr_detect):
- domain += rp.data_o.eq(reg)
+ domain += rp.o_data.eq(reg)
else:
- domain += rp.data_o.eq(reg)
+ domain += rp.o_data.eq(reg)
# write ports, delayed by 1 cycle
for wp in self._wrports:
with m.If(wp.wen):
- m.d.sync += reg.eq(wp.data_i)
+ m.d.sync += reg.eq(wp.i_data)
return m
res = list(self)
-def ortreereduce(tree, attr="data_o"):
+def ortreereduce(tree, attr="o_data"):
return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
regs = self.read_reg_port(name)
regs = Array(regs)
port = RecordObject([("ren", self.depth),
- ("data_o", self.width)], name)
+ ("o_data", self.width)], name)
self._rdports.append((regs, port))
return port
regs = self.write_reg_port(name)
regs = Array(regs)
port = RecordObject([("wen", self.depth),
- ("data_i", self.width)])
+ ("i_data", self.width)])
self._wrports.append((regs, port))
return port
ren_delay = Signal.like(p.ren)
m.d.sync += ren_delay.eq(p.ren)
with m.If(ren_delay):
- m.d.comb += p.data_o.eq(ror)
+ m.d.comb += p.o_data.eq(ror)
else:
- m.d.comb += p.data_o.eq(ror)
+ m.d.comb += p.o_data.eq(ror)
for (regs, p) in self._wrports:
m.d.comb += self._get_en_sig(regs, 'wen').eq(p.wen)
for r in regs:
- m.d.comb += r.data_i.eq(p.data_i)
+ m.d.comb += r.i_data.eq(p.i_data)
return m
bsz = log2_int(self.depth, False)
port = RecordObject([("addr", bsz),
("ren", 1),
- ("data_o", self.width)], name=name)
+ ("o_data", self.width)], name=name)
if self.synced:
domain = "sync"
else:
bsz = log2_int(self.depth, False)
port = RecordObject([("addr", bsz),
("wen", 1),
- ("data_i", self.width)], name=name)
+ ("i_data", self.width)], name=name)
self._wrports[name] = (port, self.memory.write_port())
return port
addrmatch = Signal(reset_less=False)
m.d.comb += addrmatch.eq(wp.addr == rp.addr)
with m.If(wp.wen & addrmatch):
- m.d.comb += rp.data_o.eq(wp.data_i)
+ m.d.comb += rp.o_data.eq(wp.i_data)
m.d.comb += wr_detect.eq(1)
with m.If(~wr_detect):
- m.d.comb += rp.data_o.eq(rport.data)
+ m.d.comb += rp.o_data.eq(rport.data)
else:
if self.synced:
ren_delay = Signal.like(rp.ren)
m.d.sync += ren_delay.eq(rp.ren)
with m.If(ren_delay):
- m.d.comb += rp.data_o.eq(rport.data)
+ m.d.comb += rp.o_data.eq(rport.data)
else:
- m.d.comb += rp.data_o.eq(rport.data)
+ m.d.comb += rp.o_data.eq(rport.data)
# write ports, delayed by one cycle (in the memory itself)
for name, (port, wp) in self._wrports.items():
setattr(m.submodules, "wp_"+name, wp)
comb += wp.addr.eq(port.addr)
comb += wp.en.eq(port.wen)
- comb += wp.data.eq(port.data_i)
+ comb += wp.data.eq(port.i_data)
return m
bsz = int(log(self.width) / log(2))
port = RecordObject([("addr", bsz),
("ren", 1),
- ("data_o", self.width)], name=name)
+ ("o_data", self.width)], name=name)
self._rdports.append(port)
return port
bsz = int(log(self.width) / log(2))
port = RecordObject([("addr", bsz),
("wen", 1),
- ("data_i", self.width)], name=name)
+ ("i_data", self.width)], name=name)
self._wrports.append(port)
return port
addrmatch = Signal(reset_less=False)
m.d.comb += addrmatch.eq(wp.addr == rp.addr)
with m.If(wp.wen & addrmatch):
- m.d.comb += rp.data_o.eq(wp.data_i)
+ m.d.comb += rp.o_data.eq(wp.i_data)
m.d.comb += wr_detect.eq(1)
with m.If(~wr_detect):
- m.d.comb += rp.data_o.eq(regs[rp.addr])
+ m.d.comb += rp.o_data.eq(regs[rp.addr])
# write ports, delayed by one cycle
for wp in self._wrports:
with m.If(wp.wen):
- m.d.sync += regs[wp.addr].eq(wp.data_i)
+ m.d.sync += regs[wp.addr].eq(wp.i_data)
return m
def regfile_sim(dut, rp, wp):
yield wp.addr.eq(1)
- yield wp.data_i.eq(2)
+ yield wp.i_data.eq(2)
yield wp.wen.eq(1)
yield
yield wp.wen.eq(0)
yield rp.ren.eq(1)
yield rp.addr.eq(1)
yield Settle()
- data = yield rp.data_o
+ data = yield rp.o_data
print(data)
yield
- data = yield rp.data_o
+ data = yield rp.o_data
print(data)
yield
- data2 = yield rp.data_o
+ data2 = yield rp.o_data
print(data2)
assert data == 2
yield
yield rp.addr.eq(5)
yield rp.ren.eq(1)
yield wp.wen.eq(1)
- yield wp.data_i.eq(6)
+ yield wp.i_data.eq(6)
yield
- data = yield rp.data_o
+ data = yield rp.o_data
print(data)
assert data == 6
yield
yield wp.wen.eq(0)
yield rp.ren.eq(0)
yield
- data = yield rp.data_o
+ data = yield rp.o_data
print(data)
assert data == 0
yield
- data = yield rp.data_o
+ data = yield rp.o_data
print(data)
def regfile_array_sim(dut, rp1, rp2, wp, wp2):
print("regfile_array_sim")
- yield wp.data_i.eq(2)
+ yield wp.i_data.eq(2)
yield wp.wen.eq(1 << 1)
yield
yield wp.wen.eq(0)
yield rp1.ren.eq(1 << 1)
yield Settle()
- data = yield rp1.data_o
+ data = yield rp1.o_data
print(data)
assert data == 2
yield
yield rp1.ren.eq(1 << 5)
yield rp2.ren.eq(1 << 1)
yield wp.wen.eq(1 << 5)
- yield wp.data_i.eq(6)
+ yield wp.i_data.eq(6)
yield Settle()
- data = yield rp1.data_o
+ data = yield rp1.o_data
assert data == 6
print(data)
yield
yield rp1.ren.eq(0)
yield rp2.ren.eq(0)
yield Settle()
- data1 = yield rp1.data_o
+ data1 = yield rp1.o_data
print(data1)
assert data1 == 0
- data2 = yield rp2.data_o
+ data2 = yield rp2.o_data
print(data2)
assert data2 == 0
yield
- data = yield rp1.data_o
+ data = yield rp1.o_data
print(data)
assert data == 0
# "full" depth variant of the "external" port
self.full_wr = RecordObject([("wen", n_regs),
- ("data_i", bitwidth)], # *full* wid
+ ("i_data", bitwidth)], # *full* wid
name="full_wr")
self.full_rd = RecordObject([("ren", n_regs),
- ("data_o", bitwidth)], # *full* wid
+ ("o_data", bitwidth)], # *full* wid
name="full_rd")
if not rd2:
return
self.full_rd2 = RecordObject([("ren", n_regs),
- ("data_o", bitwidth)], # *full* wid
+ ("o_data", bitwidth)], # *full* wid
name="full_rd2")
def connect_full_rd(self, m, rfull, name):
rd_regs = self.read_reg_port(name)
# wire up the enable signals and chain-accumulate the data
- l = map(lambda port: port.data_o, rd_regs) # get port data(s)
+ l = map(lambda port: port.o_data, rd_regs) # get port data(s)
le = map(lambda port: port.ren, rd_regs) # get port ren(s)
- comb += rfull.data_o.eq(Cat(*l)) # we like Cat on lists
+ comb += rfull.o_data.eq(Cat(*l)) # we like Cat on lists
comb += Cat(*le).eq(rfull.ren)
def elaborate(self, platform):
wfull = self.full_wr
# wire up the enable signals from the large (full) port
- l = map(lambda port: port.data_i, wr_regs)
+ l = map(lambda port: port.i_data, wr_regs)
le = map(lambda port: port.wen, wr_regs) # get port wen(s)
- # get list of all data_i (and wens) and assign to them via Cat
- comb += Cat(*l).eq(wfull.data_i)
+ # get list of all i_data (and wens) and assign to them via Cat
+ comb += Cat(*l).eq(wfull.i_data)
comb += Cat(*le).eq(wfull.wen)
return m
def regfile_array_sim(dut, rp1, rp2, rp3, wp):
# part-port write
- yield wp.data_i.eq(2)
+ yield wp.i_data.eq(2)
yield wp.wen.eq(1 << 1)
yield
yield wp.wen.eq(0)
# part-port read
yield rp1.ren.eq(1 << 1)
yield
- data = yield rp1.data_o
+ data = yield rp1.o_data
print(data)
assert data == 2
yield rp1.ren.eq(1 << 5)
yield rp2.ren.eq(1 << 1)
yield wp.wen.eq(1 << 5)
- yield wp.data_i.eq(6)
+ yield wp.i_data.eq(6)
yield
yield wp.wen.eq(0)
yield rp1.ren.eq(0)
yield rp2.ren.eq(0)
- data1 = yield rp1.data_o
+ data1 = yield rp1.o_data
print(data1)
assert data1 == 6, data1
- data2 = yield rp2.data_o
+ data2 = yield rp2.o_data
print(data2)
assert data2 == 2, data2
yield
- data = yield rp1.data_o
+ data = yield rp1.o_data
print(data)
# full port read (whole reg)
yield dut.full_rd.ren.eq(0xff)
yield
yield dut.full_rd.ren.eq(0)
- data = yield dut.full_rd.data_o
+ data = yield dut.full_rd.o_data
print(hex(data))
# full port read (part reg)
yield dut.full_rd.ren.eq(0x1 << 5)
yield
yield dut.full_rd.ren.eq(0)
- data = yield dut.full_rd.data_o
+ data = yield dut.full_rd.o_data
print(hex(data))
# full port part-write (part masked reg)
yield dut.full_wr.wen.eq(0x1 << 1)
- yield dut.full_wr.data_i.eq(0xe0)
+ yield dut.full_wr.i_data.eq(0xe0)
yield
yield dut.full_wr.wen.eq(0x0)
yield dut.full_rd.ren.eq(0xff)
yield
yield dut.full_rd.ren.eq(0)
- data = yield dut.full_rd.data_o
+ data = yield dut.full_rd.o_data
print(hex(data))
# full port write
yield dut.full_wr.wen.eq(0xff)
- yield dut.full_wr.data_i.eq(0xcafeface)
+ yield dut.full_wr.i_data.eq(0xcafeface)
yield
yield dut.full_wr.wen.eq(0x0)
yield dut.full_rd.ren.eq(0xff)
yield
yield dut.full_rd.ren.eq(0)
- data = yield dut.full_rd.data_o
+ data = yield dut.full_rd.o_data
print(hex(data))
# part write
- yield wp.data_i.eq(2)
+ yield wp.i_data.eq(2)
yield wp.wen.eq(1 << 1)
yield
yield wp.wen.eq(0)
yield rp1.ren.eq(1 << 1)
yield
- data = yield rp1.data_o
+ data = yield rp1.o_data
print(hex(data))
assert data == 2
yield dut.full_rd.ren.eq(0xff)
yield
yield dut.full_rd.ren.eq(0)
- data = yield dut.full_rd.data_o
+ data = yield dut.full_rd.o_data
print(hex(data))
# simultaneous read/write: full-write, part-write, 3x part-read
yield rp2.ren.eq(1 << 1)
yield rp3.ren.eq(1 << 3)
yield wp.wen.eq(1 << 3)
- yield wp.data_i.eq(6)
+ yield wp.i_data.eq(6)
yield dut.full_wr.wen.eq((1 << 1) | (1 << 5))
- yield dut.full_wr.data_i.eq((0xa << (1*4)) | (0x3 << (5*4)))
+ yield dut.full_wr.i_data.eq((0xa << (1*4)) | (0x3 << (5*4)))
yield
yield dut.full_wr.wen.eq(0)
yield wp.wen.eq(0)
yield rp1.ren.eq(0)
yield rp2.ren.eq(0)
yield rp3.ren.eq(0)
- data1 = yield rp1.data_o
+ data1 = yield rp1.o_data
print(hex(data1))
assert data1 == 0x3
- data2 = yield rp2.data_o
+ data2 = yield rp2.o_data
print(hex(data2))
assert data2 == 0xa
- data3 = yield rp3.data_o
+ data3 = yield rp3.o_data
print(hex(data3))
assert data3 == 0x6
self.n_out = n_out
mqbits = (int(log(iqlen) / log(2))+2, False)
- self.p_add_i = Signal(mqbits) # instructions to add (from data_i)
+ self.p_add_i = Signal(mqbits) # instructions to add (from i_data)
self.p_o_ready = Signal() # instructions were added
- self.data_i = Instruction._nq(n_in, "data_i")
+ self.i_data = Instruction._nq(n_in, "i_data")
- self.data_o = Instruction._nq(n_out, "data_o")
+ self.o_data = Instruction._nq(n_out, "o_data")
self.n_sub_i = Signal(mqbits) # number of instructions to remove
self.n_sub_o = Signal(mqbits) # number of instructions removed
- self.qsz = shape(self.data_o[0])[0]
+ self.qsz = shape(self.o_data[0])[0]
q = []
for i in range(iqlen):
q.append(Signal(self.qsz, name="q%d" % i))
for i in range(self.n_out):
opos = Signal(mqbits)
comb += opos.eq(end_q + i)
- comb += cat(self.data_o[i]).eq(self.q[opos])
+ comb += cat(self.o_data[i]).eq(self.q[opos])
with m.If(self.n_sub_o):
# ok now the end's moved
with m.If(self.p_add_i > Const(i, len(self.p_add_i))):
ipos = Signal(mqbits)
comb += ipos.eq(start_q + i) # should roll round
- sync += self.q[ipos].eq(cat(self.data_i[i]))
+ sync += self.q[ipos].eq(cat(self.i_data[i]))
sync += start_q.eq(start_q + self.p_add_i)
with m.If(self.p_o_ready):
yield from self.q
yield self.p_o_ready
- for o in self.data_i:
+ for o in self.i_data:
yield from list(o)
yield self.p_add_i
- for o in self.data_o:
+ for o in self.o_data:
yield from list(o)
yield self.n_sub_i
yield self.n_sub_o
print("sendlen", len(self.iq)-i, sendlen)
for idx in range(sendlen):
instr = self.iq[i+idx]
- yield from eq(self.dut.data_i[idx], instr)
- di = yield self.dut.data_i[idx] # .src1_i
+ yield from eq(self.dut.i_data[idx], instr)
+ di = yield self.dut.i_data[idx] # .src1_i
print("senddata %d %x" % ((i+idx), di))
self.oq.append(di)
yield self.dut.p_add_i.eq(sendlen)
n_sub_o = yield self.dut.n_sub_o
print("recv", n_sub_o)
for j in range(n_sub_o):
- r = yield self.dut.data_o[j] # .src1_i
+ r = yield self.dut.o_data[j] # .src1_i
print("recvdata %x %s" % (r, repr(self.iq[i+j])))
assert r == self.oq[i+j]
yield
# branch is active (TODO: a better signal: this is over-using the
# go_write signal - actually the branch should not be "writing")
with m.If(br1.go_wr_i):
- sync += self.branch_direction_o.eq(br1.data_o+Const(1, 2))
+ sync += self.branch_direction_o.eq(br1.o_data+Const(1, 2))
sync += bspec.active_i.eq(0)
comb += bspec.br_i.eq(1)
# branch occurs if data == 1, failed if data == 0
- comb += bspec.br_ok_i.eq(br1.data_o == 1)
+ comb += bspec.br_ok_i.eq(br1.o_data == 1)
for i in range(n_intfus):
# *expected* direction of the branch matched against *actual*
comb += bshadow.s_good_i[i][0].eq(bspec.match_g_o[i])
comb += int_src2.ren.eq(intfus.src2_rsel_o)
# connect ALUs to regfule
- comb += int_dest.data_i.eq(cu.data_o)
- comb += cu.src1_i.eq(int_src1.data_o)
- comb += cu.src2_i.eq(int_src2.data_o)
+ comb += int_dest.i_data.eq(cu.o_data)
+ comb += cu.src1_i.eq(int_src1.o_data)
+ comb += cu.src2_i.eq(int_src2.o_data)
# connect ALU Computation Units
comb += cu.go_rd_i[0:n_intfus].eq(go_rd_o[0:n_intfus])
# branch is active (TODO: a better signal: this is over-using the
# go_write signal - actually the branch should not be "writing")
with m.If(br1.go_wr_i):
- sync += self.branch_direction_o.eq(br1.data_o+Const(1, 2))
+ sync += self.branch_direction_o.eq(br1.o_data+Const(1, 2))
sync += bspec.active_i.eq(0)
comb += bspec.br_i.eq(1)
# branch occurs if data == 1, failed if data == 0
- comb += bspec.br_ok_i.eq(br1.data_o == 1)
+ comb += bspec.br_ok_i.eq(br1.o_data == 1)
for i in range(n_intfus):
# *expected* direction of the branch matched against *actual*
comb += bshadow.s_good_i[i][0].eq(bspec.match_g_o[i])
comb += int_src2.ren.eq(intfus.src2_rsel_o)
# connect ALUs to regfule
- comb += int_dest.data_i.eq(cu.data_o)
- comb += cu.src1_i.eq(int_src1.data_o)
- comb += cu.src2_i.eq(int_src2.data_o)
+ comb += int_dest.i_data.eq(cu.o_data)
+ comb += cu.src1_i.eq(int_src1.o_data)
+ comb += cu.src2_i.eq(int_src2.o_data)
# connect ALU Computation Units
comb += cu.go_rd_i[0:n_intfus].eq(go_rd_o[0:n_intfus])
# helper function for reducing a list of signals down to a parallel
# ORed single signal.
-def ortreereduce(tree, attr="data_o"):
+def ortreereduce(tree, attr="o_data"):
return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
src = fu.src_i[idx]
print("reg connect widths",
regfile, regname, pi, funame,
- src.shape(), rport.data_o.shape())
+ src.shape(), rport.o_data.shape())
# all FUs connect to same port
- comb += src.eq(rport.data_o)
+ comb += src.eq(rport.o_data)
# or-reduce the muxed read signals
if rfile.unary:
# connect regfile port to input
print("reg connect widths",
regfile, regname, pi, funame,
- dest.shape(), wport.data_i.shape())
+ dest.shape(), wport.i_data.shape())
wsigs.append(fu_dest_latch)
# here is where we create the Write Broadcast Bus. simple, eh?
- comb += wport.data_i.eq(ortreereduce_sig(wsigs))
+ comb += wport.i_data.eq(ortreereduce_sig(wsigs))
if rfile.unary:
# for unary-addressed
comb += wport.wen.eq(ortreereduce_sig(wens))
comb += regfile.ren.eq(1<<regnum)
# ... but on a 1-clock delay
with m.If(res_ok_delay):
- comb += res.eq(regfile.data_o)
+ comb += res.eq(regfile.o_data)
return res
def get_predint(m, mask, name):
# one cycle later, msr/sv read arrives. valid only once.
with m.If(~msr_read):
sync += msr_read.eq(1) # yeah don't read it again
- sync += cur_state.msr.eq(self.state_r_msr.data_o)
+ sync += cur_state.msr.eq(self.state_r_msr.o_data)
with m.If(self.imem.f_busy_o): # zzz...
# busy: stay in wait-read
comb += self.imem.a_i_valid.eq(1)
with m.If(dunary):
# set selected mask bit for 1<<r3 mode
dst_shift = Signal(range(64))
- comb += dst_shift.eq(self.int_pred.data_o & 0b111111)
+ comb += dst_shift.eq(self.int_pred.o_data & 0b111111)
sync += new_dstmask.eq(1 << dst_shift)
with m.Else():
# invert mask if requested
- sync += new_dstmask.eq(self.int_pred.data_o ^ inv)
+ sync += new_dstmask.eq(self.int_pred.o_data ^ inv)
# skip fetching source mask register, when zero
with m.If(sall1s):
sync += new_srcmask.eq(-1)
with m.If(sunary):
# set selected mask bit for 1<<r3 mode
src_shift = Signal(range(64))
- comb += src_shift.eq(self.int_pred.data_o & 0b111111)
+ comb += src_shift.eq(self.int_pred.o_data & 0b111111)
sync += new_srcmask.eq(1 << src_shift)
with m.Else():
# invert mask if requested
- sync += new_srcmask.eq(self.int_pred.data_o ^ inv)
+ sync += new_srcmask.eq(self.int_pred.o_data ^ inv)
m.next = "FETCH_PRED_SHIFT_MASK"
# fetch masks from the CR register file
cr_field = Signal(4)
scr_bit = Signal()
dcr_bit = Signal()
- comb += cr_field.eq(cr_pred.data_o)
+ comb += cr_field.eq(cr_pred.o_data)
comb += scr_bit.eq(cr_field.bit_select(sidx, 1) ^ scrinvert)
comb += dcr_bit.eq(cr_field.bit_select(didx, 1) ^ dcrinvert)
# set the corresponding mask bit
# while stopped, allow updating the PC and SVSTATE
with m.If(self.pc_i.ok):
comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
- comb += self.state_w_pc.data_i.eq(self.pc_i.data)
+ comb += self.state_w_pc.i_data.eq(self.pc_i.data)
sync += pc_changed.eq(1)
with m.If(self.svstate_i.ok):
comb += new_svstate.eq(self.svstate_i.data)
# since we are in a VL==0 loop, no instruction was
# executed that we could be overwriting
comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
- comb += self.state_w_pc.data_i.eq(nia)
+ comb += self.state_w_pc.i_data.eq(nia)
comb += self.insn_done.eq(1)
m.next = "ISSUE_START"
with m.Else():
(skip_dststep >= cur_vl)):
# end of VL loop. Update PC and reset src/dst step
comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
- comb += self.state_w_pc.data_i.eq(nia)
+ comb += self.state_w_pc.i_data.eq(nia)
comb += new_svstate.srcstep.eq(0)
comb += new_svstate.dststep.eq(0)
comb += update_svstate.eq(1)
# TODO: this just blithely overwrites whatever
# pipeline updated the PC
comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
- comb += self.state_w_pc.data_i.eq(nia)
+ comb += self.state_w_pc.i_data.eq(nia)
# reset SRCSTEP before returning to Fetch
if self.svp64_en:
with m.If(pdecode2.loop_continue):
# while stopped, allow updating the PC and SVSTATE
with m.If(self.pc_i.ok):
comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
- comb += self.state_w_pc.data_i.eq(self.pc_i.data)
+ comb += self.state_w_pc.i_data.eq(self.pc_i.data)
sync += pc_changed.eq(1)
with m.If(self.svstate_i.ok):
comb += new_svstate.eq(self.svstate_i.data)
# check if svstate needs updating: if so, write it to State Regfile
with m.If(update_svstate):
comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
- comb += self.state_w_sv.data_i.eq(new_svstate)
+ comb += self.state_w_sv.i_data.eq(new_svstate)
sync += cur_state.svstate.eq(new_svstate) # for next clock
def execute_fsm(self, m, core, pc_changed, sv_changed,
# don't write pc every cycle
comb += self.state_w_pc.wen.eq(0)
- comb += self.state_w_pc.data_i.eq(0)
+ comb += self.state_w_pc.i_data.eq(0)
# don't read msr every cycle
comb += self.state_r_msr.ren.eq(0)
sync += d_reg_delay.eq(d_reg.req)
with m.If(d_reg_delay):
# data arrives one clock later
- comb += d_reg.data.eq(self.int_r.data_o)
+ comb += d_reg.data.eq(self.int_r.o_data)
comb += d_reg.ack.eq(1)
# sigh same thing for CR debug
sync += d_cr_delay.eq(d_cr.req)
with m.If(d_cr_delay):
# data arrives one clock later
- comb += d_cr.data.eq(self.cr_r.data_o)
+ comb += d_cr.data.eq(self.cr_r.o_data)
comb += d_cr.ack.eq(1)
# aaand XER...
sync += d_xer_delay.eq(d_xer.req)
with m.If(d_xer_delay):
# data arrives one clock later
- comb += d_xer.data.eq(self.xer_r.data_o)
+ comb += d_xer.data.eq(self.xer_r.o_data)
comb += d_xer.ack.eq(1)
def tb_dec_fsm(self, m, spr_dec):
with m.State("DEC_WRITE"):
new_dec = Signal(64)
# TODO: MSR.LPCR 32-bit decrement mode
- comb += new_dec.eq(fast_r_dectb.data_o - 1)
+ comb += new_dec.eq(fast_r_dectb.o_data - 1)
comb += fast_w_dectb.addr.eq(FastRegs.DEC)
comb += fast_w_dectb.wen.eq(1)
- comb += fast_w_dectb.data_i.eq(new_dec)
+ comb += fast_w_dectb.i_data.eq(new_dec)
sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
m.next = "TB_READ"
# waits for read TB to arrive, initiates write of current TB
with m.State("TB_WRITE"):
new_tb = Signal(64)
- comb += new_tb.eq(fast_r_dectb.data_o + 1)
+ comb += new_tb.eq(fast_r_dectb.o_data + 1)
comb += fast_w_dectb.addr.eq(FastRegs.TB)
comb += fast_w_dectb.wen.eq(1)
- comb += fast_w_dectb.data_i.eq(new_tb)
+ comb += fast_w_dectb.i_data.eq(new_tb)
m.next = "DEC_READ"
return m
# Check the PC as well
state = core.regs.state
- pc = yield state.r_ports['cia'].data_o
+ pc = yield state.r_ports['cia'].o_data
e_pc = sim.pc.CIA.value
dut.assertEqual(e_pc, pc)
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