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authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 7 Jul 2019 13:02:40 +0000 (14:02 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 7 Jul 2019 13:02:40 +0000 (14:02 +0100)
src/ieee754/div_rem_sqrt_rsqrt/core.py patch | blob | history

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py
index c17a2be64031ad73126fb08f5be7a34c5ebb0a43..afc331de6a0fb72de753fda50e98b6776cf77db8 100644 (file)
--- a/src/ieee754/div_rem_sqrt_rsqrt/core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py
@@ -362,9 +362,7 @@ class DivPipeCoreCalculateStage(Elaboratable):
             test = Signal(reset_less=True)
             # XXX TODO: check the width on this
             m.d.comb += test.eq((pass_flags[i] & ~next_flag))
-            m.d.comb += flag.eq(Mux(test,
-                                    trial_compare_rhs_values[i],
-                                    0))
+            m.d.comb += flag.eq(Mux(test, trial_compare_rhs_values[i], 0))
             l.append(flag)
 
         m.d.comb += next_compare_rhs.eq(Cat(*l))