debugging trap pipeline

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index aac9383867f66301a39493c96853f86094672336..f69b679295bd9d40b1d064d9e44900a2629a6d52 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -115,6 +115,7 @@ class TrapMainStage(PipeModBase):
 
         # convenience variables
         a_i, b_i, cia_i, msr_i = self.i.a, self.i.b, self.i.cia, self.i.msr
+        srr0_i, srr1_i = self.i.srr0, self.i.srr1
         o, msr_o, nia_o = self.o.o, self.o.msr, self.o.nia
         srr0_o, srr1_o = self.o.srr0, self.o.srr1
         traptype, trapaddr = op.traptype, op.trapaddr
@@ -185,7 +186,7 @@ class TrapMainStage(PipeModBase):
                         comb += srr1_o.data[PI_ADR].eq(1)
 
             # move to MSR
-            with m.Case(InternalOp.OP_MTMSR):
+            with m.Case(InternalOp.OP_MTMSRD):
                 L = self.fields.FormX.L[0:-1] # X-Form field L
                 with m.If(L):
                     # just update EE and RI
@@ -217,12 +218,13 @@ class TrapMainStage(PipeModBase):
                 msr_check_pr(m, msr_o.data)
                 comb += msr_o.ok.eq(1)
 
-            with m.Case(InternalOp.OP_SC):
-                # TODO: scv must generate illegal instruction.  this is
-                # the decoder's job, not ours, here.
-
-                # jump to the trap address, return at cia+4
-                self.trap(m, 0xc00, cia_i+4)
+            # TODO (later) - add OP_SC
+            #with m.Case(InternalOp.OP_SC):
+            #    # TODO: scv must generate illegal instruction.  this is
+            #    # the decoder's job, not ours, here.
+            #
+            #    # jump to the trap address, return at cia+4
+            #    self.trap(m, 0xc00, cia_i+4)
 
             # TODO (later)
             #with m.Case(InternalOp.OP_ADDPCIS):

diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py
index 99fe070943a6211eeceb893ad04d1bf1c9f19bf0..3b336e2ba6049fb2f32ec7b2d6eeae25cc3d39d9 100644 (file)
--- a/src/soc/fu/trap/pipe_data.py
+++ b/src/soc/fu/trap/pipe_data.py
@@ -6,12 +6,14 @@ class TrapInputData(IntegerData):
     regspec = [('INT', 'ra', '0:63'),  # RA
                ('INT', 'rb', '0:63'),  # RB/immediate
                ('FAST', 'spr1', '0:63'), # SRR0
+               ('FAST', 'spr2', '0:63'), # SRR1
                ('FAST', 'cia', '0:63'),  # Program counter (current)
                ('FAST', 'msr', '0:63')]  # MSR
     def __init__(self, pspec):
         super().__init__(pspec, False)
         # convenience
-        self.srr0, self.a, self.b = self.spr1, self.ra, self.rb
+        self.srr0, self.srr1 = self.spr1, self.spr2
+        self.a, self.b = self.ra, self.rb
 
 
 class TrapOutputData(IntegerData):