--- /dev/null
+TARGET_ISA = 'riscv'
+CPU_MODELS = 'AtomicSimpleCPU'
+PROTOCOL = 'MI_example'
#define EM_X86_64 62 /* Advanced Micro Devices x86-64 */
#define EM_AMD64 EM_X86_64 /* Advanced Micro Devices x86-64 (compat) */
#define EM_AARCH64 183 /* AArch64 64 bit ARM. */
+#define EM_RISCV 243 /* Berkeley RISC-V */
/* Non-standard or deprecated. */
#define EM_486 6 /* Intel i486. */
--- /dev/null
+# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2014 Sven Karlsson
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2016 RISC-V Foundation
+# Copyright (c) 2016 The University of Virginia
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+# Sven Karlsson
+# Alec Roelke
+
+from m5.SimObject import SimObject
+
+class RiscvISA(SimObject):
+ type = 'RiscvISA'
+ cxx_class = 'RiscvISA::ISA'
+ cxx_header = "arch/riscv/isa.hh"
--- /dev/null
+# Copyright (c) 2008 The Regents of The University of Michigan
+# Copyright (c) 2014 Sven Karlsson
+# Copyright (c) 2016 RISC-V Foundation
+# Copyright (c) 2016 The University of Virginia
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+# Sven Karlsson
+# Alec Roelke
+
+from m5.SimObject import SimObject
+
+class RiscvInterrupts(SimObject):
+ type = 'RiscvInterrupts'
+ cxx_class = 'RiscvISA::Interrupts'
+ cxx_header = 'arch/riscv/interrupts.hh'
--- /dev/null
+# -*- mode:python -*-
+
+# Copyright (c) 2016 RISC-V Foundation
+# Copyright (c) 2016 The University of Virginia
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Alec Roelke
+
+from System import System
+
+class RiscvSystem(System):
+ type = 'RiscvSystem'
+ cxx_header = 'arch/riscv/system.hh'
+ load_addr_mask = 0xFFFFFFFFFFFFFFFF
--- /dev/null
+# -*- mode:python -*-
+
+# Copyright (c) 2007 MIPS Technologies, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jaidev Patwardhan
+# Korey Sewell
+
+from m5.SimObject import SimObject
+from m5.params import *
+
+from BaseTLB import BaseTLB
+
+class RiscvTLB(BaseTLB):
+ type = 'RiscvTLB'
+ cxx_class = 'RiscvISA::TLB'
+ cxx_header = 'arch/riscv/tlb.hh'
+ size = Param.Int(64, "TLB size")
--- /dev/null
+# -*- mode:python -*-
+
+# Copyright (c) 2013 ARM Limited
+# Copyright (c) 2014 Sven Karlsson
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2016 The University of Virginia
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Hansson
+# Sven Karlsson
+# Alec Roelke
+
+Import('*')
+
+if env['TARGET_ISA'] == 'riscv':
+ Source('decoder.cc')
+ Source('faults.cc')
+ Source('isa.cc')
+ Source('interrupts.cc')
+ Source('process.cc')
+ Source('pagetable.cc')
+ Source('remote_gdb.cc')
+ Source('stacktrace.cc')
+ Source('tlb.cc')
+ Source('system.cc')
+
+ Source('linux/process.cc')
+ Source('linux/linux.cc')
+
+ SimObject('RiscvInterrupts.py')
+ SimObject('RiscvISA.py')
+ SimObject('RiscvTLB.py')
+ SimObject('RiscvSystem.py')
+
+ DebugFlag('RiscvMisc')
+ DebugFlag('RiscvTLB')
+
+ # Add in files generated by the ISA description.
+ env.ISADesc('isa/main.isa')
--- /dev/null
+# -*- mode:python -*-
+
+# Copyright (c) 2004-2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+Import('*')
+
+all_isa_list.append('riscv')
--- /dev/null
+/*
+ * Copyright (c) 2012 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/riscv/decoder.hh"
+
+namespace RiscvISA
+{
+
+GenericISA::BasicDecodeCache Decoder::defaultCache;
+
+}
--- /dev/null
+/*
+ * Copyright (c) 2012 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_RISCV_DECODER_HH__
+#define __ARCH_RISCV_DECODER_HH__
+
+#include "arch/generic/decode_cache.hh"
+#include "arch/riscv/types.hh"
+#include "base/misc.hh"
+#include "base/types.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+class ISA;
+class Decoder
+{
+ protected:
+ //The extended machine instruction being generated
+ ExtMachInst emi;
+ bool instDone;
+
+ public:
+ Decoder(ISA* isa = nullptr) : instDone(false)
+ {}
+
+ void
+ process()
+ {
+ }
+
+ void
+ reset()
+ {
+ instDone = false;
+ }
+
+ //Use this to give data to the decoder. This should be used
+ //when there is control flow.
+ void
+ moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
+ {
+ emi = inst;
+ instDone = true;
+ }
+
+ bool
+ needMoreBytes()
+ {
+ return true;
+ }
+
+ bool
+ instReady()
+ {
+ return instDone;
+ }
+
+ void takeOverFrom(Decoder *old) {}
+
+ protected:
+ /// A cache of decoded instruction objects.
+ static GenericISA::BasicDecodeCache defaultCache;
+
+ public:
+ StaticInstPtr decodeInst(ExtMachInst mach_inst);
+
+ /// Decode a machine instruction.
+ /// @param mach_inst The binary instruction to decode.
+ /// @retval A pointer to the corresponding StaticInst object.
+ StaticInstPtr
+ decode(ExtMachInst mach_inst, Addr addr)
+ {
+ return defaultCache.decode(this, mach_inst, addr);
+ }
+
+ StaticInstPtr
+ decode(RiscvISA::PCState &nextPC)
+ {
+ if (!instDone)
+ return nullptr;
+ instDone = false;
+ return decode(emi, nextPC.instAddr());
+ }
+};
+
+} // namespace RiscvISA
+
+#endif // __ARCH_RISCV_DECODER_HH__
--- /dev/null
+/*
+ * Copyright (c) 2016 RISC-V Foundation
+ * Copyright (c) 2016 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alec Roelke
+ */
+#include "arch/riscv/faults.hh"
+
+#include "arch/riscv/utility.hh"
+#include "cpu/thread_context.hh"
+#include "sim/debug.hh"
+#include "sim/full_system.hh"
+
+using namespace RiscvISA;
+
+void
+RiscvFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
+{
+ panic("Fault %s encountered at pc 0x%016llx.", name(), tc->pcState().pc());
+}
+
+void
+RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
+{
+ if (FullSystem) {
+ panic("Full system mode not supported for RISC-V.");
+ } else {
+ invoke_se(tc, inst);
+ PCState pcState = tc->pcState();
+ advancePC(pcState, inst);
+ tc->pcState(pcState);
+ }
+}
+
+void
+UnknownInstFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
+{
+ panic("Unknown instruction 0x%08x at pc 0x%016llx", inst->machInst,
+ tc->pcState().pc());
+}
+
+void
+UnimplementedFault::invoke_se(ThreadContext *tc,
+ const StaticInstPtr &inst)
+{
+ panic("Unimplemented instruction %s at pc 0x%016llx", instName,
+ tc->pcState().pc());
+}
+
+void
+BreakpointFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
+{
+ schedRelBreak(0);
+}
+
+void
+SyscallFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
+{
+ tc->syscall(tc->readIntReg(SyscallNumReg));
+}
--- /dev/null
+/*
+ * Copyright (c) 2016 RISC-V Foundation
+ * Copyright (c) 2016 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alec Roelke
+ */
+
+#ifndef __ARCH_RISCV_FAULTS_HH__
+#define __ARCH_RISCV_FAULTS_HH__
+
+#include <string>
+
+#include "cpu/thread_context.hh"
+#include "sim/faults.hh"
+
+namespace RiscvISA
+{
+
+enum ExceptionCode {
+ INST_ADDR_MISALIGNED = 0,
+ INST_ACCESS = 1,
+ INST_ILLEGAL = 2,
+ BREAKPOINT = 3,
+ LOAD_ADDR_MISALIGNED = 4,
+ LOAD_ACCESS = 5,
+ STORE_ADDR_MISALIGNED = 6,
+ AMO_ADDR_MISALIGNED = 6,
+ STORE_ACCESS = 7,
+ AMO_ACCESS = 7,
+ ECALL_USER = 8,
+ ECALL_SUPER = 9,
+ ECALL_HYPER = 10,
+ ECALL_MACH = 11
+};
+
+enum InterruptCode {
+ SOFTWARE,
+ TIMER
+};
+
+class RiscvFault : public FaultBase
+{
+ protected:
+ const FaultName _name;
+ const ExceptionCode _code;
+ const InterruptCode _int;
+
+ RiscvFault(FaultName n, ExceptionCode c, InterruptCode i)
+ : _name(n), _code(c), _int(i)
+ {}
+
+ FaultName
+ name() const
+ {
+ return _name;
+ }
+
+ ExceptionCode
+ exception() const
+ {
+ return _code;
+ }
+
+ InterruptCode
+ interrupt() const
+ {
+ return _int;
+ }
+
+ virtual void
+ invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
+
+ void
+ invoke(ThreadContext *tc, const StaticInstPtr &inst);
+};
+
+
+class UnknownInstFault : public RiscvFault
+{
+ public:
+ UnknownInstFault() : RiscvFault("Unknown instruction", INST_ILLEGAL,
+ SOFTWARE)
+ {}
+
+ void
+ invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
+};
+
+class UnimplementedFault : public RiscvFault
+{
+ private:
+ const std::string instName;
+ public:
+ UnimplementedFault(std::string name)
+ : RiscvFault("Unimplemented instruction", INST_ILLEGAL, SOFTWARE),
+ instName(name)
+ {}
+
+ void
+ invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
+};
+
+class BreakpointFault : public RiscvFault
+{
+ public:
+ BreakpointFault() : RiscvFault("Breakpoint", BREAKPOINT, SOFTWARE)
+ {}
+
+ void
+ invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
+};
+
+class SyscallFault : public RiscvFault
+{
+ public:
+ // TODO: replace ECALL_USER with the appropriate privilege level of the
+ // caller
+ SyscallFault() : RiscvFault("System call", ECALL_USER, SOFTWARE)
+ {}
+
+ void
+ invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
+};
+
+} // namespace RiscvISA
+
+#endif // __ARCH_RISCV_FAULTS_HH__
--- /dev/null
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Lisa Hsu
+ * Ali Saidi
+ */
+
+#include "arch/riscv/idle_event.hh"
+
+#include "arch/riscv/kernel_stats.hh"
+#include "cpu/thread_context.hh"
+
+using namespace RiscvISA;
+
+void
+IdleStartEvent::process(ThreadContext *tc)
+{
+ fatal("Idle Start Event Not Defined for RISCV ISA ");
+}
--- /dev/null
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Lisa Hsu
+ * Ali Saidi
+ */
+
+#ifndef __KERN_RISCV_IDLE_EVENT_HH__
+#define __KERN_RISCV_IDLE_EVENT_HH__
+
+#include "cpu/pc_event.hh"
+
+class IdleStartEvent : public PCEvent
+{
+ public:
+ IdleStartEvent(PCEventQueue *q, const std::string &desc, Addr addr)
+ : PCEvent(q, desc, addr)
+ {}
+ virtual void process(ThreadContext *tc);
+};
+
+#endif // __KERN_RISCV_IDLE_EVENT_HH__
--- /dev/null
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/riscv/interrupts.hh"
+
+RiscvISA::Interrupts *
+RiscvInterruptsParams::create()
+{
+ return new RiscvISA::Interrupts(this);
+}
--- /dev/null
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_RISCV_INTERRUPT_HH__
+#define __ARCH_RISCV_INTERRUPT_HH__
+
+#include "base/misc.hh"
+#include "params/RiscvInterrupts.hh"
+#include "sim/sim_object.hh"
+
+class ThreadContext;
+
+namespace RiscvISA {
+
+class Interrupts : public SimObject
+{
+ private:
+ BaseCPU * cpu;
+
+ public:
+ typedef RiscvInterruptsParams Params;
+
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
+
+ Interrupts(Params * p) : SimObject(p), cpu(nullptr)
+ {}
+
+ void
+ setCPU(BaseCPU * _cpu)
+ {
+ cpu = _cpu;
+ }
+
+ void
+ post(int int_num, int index)
+ {
+ panic("Interrupts::post not implemented.\n");
+ }
+
+ void
+ clear(int int_num, int index)
+ {
+ panic("Interrupts::clear not implemented.\n");
+ }
+
+ void
+ clearAll()
+ {
+ panic("Interrupts::clearAll not implemented.\n");
+ }
+
+ bool
+ checkInterrupts(ThreadContext *tc) const
+ {
+ panic("Interrupts::checkInterrupts not implemented.\n");
+ }
+
+ Fault
+ getInterrupt(ThreadContext *tc)
+ {
+ assert(checkInterrupts(tc));
+ panic("Interrupts::getInterrupt not implemented.\n");
+ }
+
+ void
+ updateIntrInfo(ThreadContext *tc)
+ {
+ panic("Interrupts::updateIntrInfo not implemented.\n");
+ }
+};
+
+} // namespace RiscvISA
+
+#endif // __ARCH_RISCV_INTERRUPT_HH__
+
--- /dev/null
+/*
+ * Copyright (c) 2016 RISC-V Foundation
+ * Copyright (c) 2016 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alec Roelke
+ */
+#include "arch/riscv/isa.hh"
+
+#include <ctime>
+#include <set>
+
+#include "arch/riscv/registers.hh"
+#include "base/bitfield.hh"
+#include "cpu/base.hh"
+#include "debug/RiscvMisc.hh"
+#include "params/RiscvISA.hh"
+#include "sim/core.hh"
+#include "sim/pseudo_inst.hh"
+
+namespace RiscvISA
+{
+
+std::map<int, std::string> ISA::miscRegNames = {
+ {MISCREG_FFLAGS, "fflags"},
+ {MISCREG_FRM, "frm"},
+ {MISCREG_FCSR, "fcsr"},
+ {MISCREG_CYCLE, "cycle"},
+ {MISCREG_TIME, "time"},
+ {MISCREG_INSTRET, "instret"},
+ {MISCREG_CYCLEH, "cycleh"},
+ {MISCREG_TIMEH, "timeh"},
+ {MISCREG_INSTRETH, "instreth"},
+
+ {MISCREG_SSTATUS, "sstatus"},
+ {MISCREG_STVEC, "stvec"},
+ {MISCREG_SIE, "sie"},
+ {MISCREG_STIMECMP, "stimecmp"},
+ {MISCREG_STIME, "stime"},
+ {MISCREG_STIMEH, "stimeh"},
+ {MISCREG_SSCRATCH, "sscratch"},
+ {MISCREG_SEPC, "sepc"},
+ {MISCREG_SCAUSE, "scause"},
+ {MISCREG_SBADADDR, "sbadaddr"},
+ {MISCREG_SIP, "sip"},
+ {MISCREG_SPTBR, "sptbr"},
+ {MISCREG_SASID, "sasid"},
+ {MISCREG_CYCLEW, "cyclew"},
+ {MISCREG_TIMEW, "timew"},
+ {MISCREG_INSTRETW, "instretw"},
+ {MISCREG_CYCLEHW, "cyclehw"},
+ {MISCREG_TIMEHW, "timehw"},
+ {MISCREG_INSTRETHW, "instrethw"},
+
+ {MISCREG_HSTATUS, "hstatus"},
+ {MISCREG_HTVEC, "htvec"},
+ {MISCREG_HTDELEG, "htdeleg"},
+ {MISCREG_HTIMECMP, "htimecmp"},
+ {MISCREG_HTIME, "htime"},
+ {MISCREG_HTIMEH, "htimeh"},
+ {MISCREG_HSCRATCH, "hscratch"},
+ {MISCREG_HEPC, "hepc"},
+ {MISCREG_HCAUSE, "hcause"},
+ {MISCREG_HBADADDR, "hbadaddr"},
+ {MISCREG_STIMEW, "stimew"},
+ {MISCREG_STIMEHW, "stimehw"},
+
+ {MISCREG_MCPUID, "mcpuid"},
+ {MISCREG_MIMPID, "mimpid"},
+ {MISCREG_MHARTID, "mhartid"},
+ {MISCREG_MSTATUS, "mstatus"},
+ {MISCREG_MTVEC, "mtvec"},
+ {MISCREG_MTDELEG, "mtdeleg"},
+ {MISCREG_MIE, "mie"},
+ {MISCREG_MTIMECMP, "mtimecmp"},
+ {MISCREG_MTIME, "mtime"},
+ {MISCREG_MTIMEH, "mtimeh"},
+ {MISCREG_MSCRATCH, "mscratch"},
+ {MISCREG_MEPC, "mepc"},
+ {MISCREG_MCAUSE, "mcause"},
+ {MISCREG_MBADADDR, "mbadaddr"},
+ {MISCREG_MIP, "mip"},
+ {MISCREG_MBASE, "mbase"},
+ {MISCREG_MBOUND, "mbound"},
+ {MISCREG_MIBASE, "mibase"},
+ {MISCREG_MIBOUND, "mibound"},
+ {MISCREG_MDBASE, "mdbase"},
+ {MISCREG_MDBOUND, "mdbound"},
+ {MISCREG_HTIMEW, "htimew"},
+ {MISCREG_HTIMEHW, "htimehw"},
+ {MISCREG_MTOHOST, "mtohost"},
+ {MISCREG_MFROMHOST, "mfromhost"}
+};
+
+ISA::ISA(Params *p) : SimObject(p)
+{
+ miscRegFile.resize(NumMiscRegs);
+ clear();
+}
+
+const RiscvISAParams *
+ISA::params() const
+{
+ return dynamic_cast<const Params *>(_params);
+}
+
+void ISA::clear()
+{
+ std::fill(miscRegFile.begin(), miscRegFile.end(), 0);
+}
+
+
+MiscReg
+ISA::readMiscRegNoEffect(int misc_reg) const
+{
+ DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n", miscRegNames[misc_reg],
+ miscRegFile[misc_reg]);
+ switch (misc_reg) {
+ case MISCREG_FFLAGS:
+ return bits(miscRegFile[MISCREG_FCSR], 4, 0);
+ case MISCREG_FRM:
+ return bits(miscRegFile[MISCREG_FCSR], 7, 5);
+ case MISCREG_FCSR:
+ return bits(miscRegFile[MISCREG_FCSR], 31, 0);
+ case MISCREG_CYCLE:
+ warn("Use readMiscReg to read the cycle CSR.");
+ return 0;
+ case MISCREG_TIME:
+ return std::time(nullptr);
+ case MISCREG_INSTRET:
+ warn("Use readMiscReg to read the instret CSR.");
+ return 0;
+ case MISCREG_CYCLEH:
+ warn("Use readMiscReg to read the cycleh CSR.");
+ return 0;
+ case MISCREG_TIMEH:
+ return std::time(nullptr) >> 32;
+ case MISCREG_INSTRETH:
+ warn("Use readMiscReg to read the instreth CSR.");
+ return 0;
+ default:
+ return miscRegFile[misc_reg];
+ }
+}
+
+MiscReg
+ISA::readMiscReg(int misc_reg, ThreadContext *tc)
+{
+ switch (misc_reg) {
+ case MISCREG_INSTRET:
+ DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
+ miscRegNames[misc_reg], miscRegFile[misc_reg]);
+ return tc->getCpuPtr()->totalInsts();
+ case MISCREG_CYCLE:
+ DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
+ miscRegNames[misc_reg], miscRegFile[misc_reg]);
+ return tc->getCpuPtr()->curCycle();
+ case MISCREG_INSTRETH:
+ DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
+ miscRegNames[misc_reg], miscRegFile[misc_reg]);
+ return tc->getCpuPtr()->totalInsts() >> 32;
+ case MISCREG_CYCLEH:
+ DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
+ miscRegNames[misc_reg], miscRegFile[misc_reg]);
+ return tc->getCpuPtr()->curCycle() >> 32;
+ default:
+ return readMiscRegNoEffect(misc_reg);
+ }
+}
+
+void
+ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+{
+ DPRINTF(RiscvMisc, "Setting CSR %s to 0x%016llx.\n",
+ miscRegNames[misc_reg], miscRegNames[misc_reg], val);
+ switch (misc_reg) {
+ case MISCREG_FFLAGS:
+ miscRegFile[MISCREG_FCSR] &= ~0x1F;
+ miscRegFile[MISCREG_FCSR] |= bits(val, 4, 0);
+ break;
+ case MISCREG_FRM:
+ miscRegFile[MISCREG_FCSR] &= ~0x70;
+ miscRegFile[MISCREG_FCSR] |= bits(val, 2, 0) << 5;
+ break;
+ case MISCREG_FCSR:
+ miscRegFile[MISCREG_FCSR] = bits(val, 7, 0);
+ break;
+ default:
+ miscRegFile[misc_reg] = val;
+ break;
+ }
+}
+
+void
+ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
+{
+ if (bits((unsigned)misc_reg, 11, 10) == 0x3) {
+ warn("Ignoring write to read-only CSR.");
+ return;
+ }
+ setMiscRegNoEffect(misc_reg, val);
+}
+
+}
+
+RiscvISA::ISA *
+RiscvISAParams::create()
+{
+ return new RiscvISA::ISA(this);
+}
--- /dev/null
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * Copyright (c) 2009 The University of Edinburgh
+ * Copyright (c) 2014 Sven Karlsson
+ * Copyright (c) 2016 RISC-V Foundation
+ * Copyright (c) 2016 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ * Timothy M. Jones
+ * Sven Karlsson
+ * Alec Roelke
+ */
+
+#ifndef __ARCH_RISCV_ISA_HH__
+#define __ARCH_RISCV_ISA_HH__
+
+#include <map>
+#include <string>
+
+#include "arch/riscv/registers.hh"
+#include "arch/riscv/types.hh"
+#include "base/misc.hh"
+#include "sim/sim_object.hh"
+
+struct RiscvISAParams;
+class ThreadContext;
+class Checkpoint;
+class EventManager;
+
+namespace RiscvISA
+{
+
+class ISA : public SimObject
+{
+ protected:
+ std::vector<MiscReg> miscRegFile;
+
+ public:
+ typedef RiscvISAParams Params;
+ static std::map<int, std::string> miscRegNames;
+
+ void
+ clear();
+
+ MiscReg
+ readMiscRegNoEffect(int misc_reg) const;
+
+ MiscReg
+ readMiscReg(int misc_reg, ThreadContext *tc);
+
+ void
+ setMiscRegNoEffect(int misc_reg, const MiscReg &val);
+
+ void
+ setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
+
+ int
+ flattenIntIndex(int reg) const
+ {
+ return reg;
+ }
+
+ int
+ flattenFloatIndex(int reg) const
+ {
+ return reg;
+ }
+
+ // dummy
+ int
+ flattenCCIndex(int reg) const
+ {
+ return reg;
+ }
+
+ int
+ flattenMiscIndex(int reg) const
+ {
+ return reg;
+ }
+
+ void startup(ThreadContext *tc) {}
+
+ /// Explicitly import the otherwise hidden startup
+ using SimObject::startup;
+
+ const Params *
+ params() const;
+
+ ISA(Params *p);
+};
+
+} // namespace RiscvISA
+
+#endif // __ARCH_RISCV_ISA_HH__
--- /dev/null
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Maxwell Walter
+// Alec Roelke
+
+////////////////////////////////////////////////////////////////////
+//
+// Base class for Riscv instructions, and some support functions
+//
+
+//Outputs to decoder.hh
+output header {{
+ using namespace RiscvISA;
+
+ /**
+ * Base class for all RISC-V static instructions.
+ */
+ class RiscvStaticInst : public StaticInst
+ {
+ protected:
+ // Constructor
+ RiscvStaticInst(const char *mnem, MachInst _machInst,
+ OpClass __opClass) : StaticInst(mnem, _machInst, __opClass)
+ {}
+
+ std::string
+ regName(RegIndex reg) const;
+
+ virtual std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
+
+ public:
+ void
+ advancePC(RiscvISA::PCState &pc) const
+ {
+ pc.advance();
+ }
+ };
+}};
+
+//Ouputs to decoder.cc
+output decoder {{
+ std::string
+ RiscvStaticInst::regName(RegIndex reg) const
+ {
+ if (reg < FP_Reg_Base) {
+ return std::string(RegisterNames[reg]);
+ } else {
+ return std::string("f") + std::to_string(reg - FP_Reg_Base);
+ }
+ }
+}};
--- /dev/null
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Maxwell Walter
+// Alec Roelke
+
+////////////////////////////////////////////////////////////////////
+//
+// Bitfield definitions.
+//
+
+def bitfield OPCODE <6:0>;
+def bitfield NONOPCODE <31:7>;
+
+// R-Type
+def bitfield ALL <31:0>;
+def bitfield RD <11:7>;
+def bitfield FUNCT3 <14:12>;
+def bitfield RS1 <19:15>;
+def bitfield RS2 <24:20>;
+def bitfield FUNCT7 <31:25>;
+
+// Bit shifts
+def bitfield SRTYPE <30>;
+def bitfield SHAMT5 <24:20>;
+def bitfield SHAMT6 <25:20>;
+
+// I-Type
+def bitfield IMM12 <31:20>;
+
+// S-Type
+def bitfield IMM5 <11:7>;
+def bitfield IMM7 <31:25>;
+
+// U-Type
+def bitfield IMM20 <31:12>;
+
+// SB-Type
+def bitfield BIMM12BIT11 <7>;
+def bitfield BIMM12BITS4TO1<11:8>;
+def bitfield IMMSIGN <31>;
+def bitfield BIMM12BITS10TO5 <30:25>;
+
+// UJ-Type
+def bitfield UJIMMBITS10TO1 <30:21>;
+def bitfield UJIMMBIT11 <20>;
+def bitfield UJIMMBITS19TO12 <19:12>;
+
+// System
+def bitfield FUNCT12 <31:20>;
+def bitfield ZIMM <19:15>;
--- /dev/null
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Alec Roelke
+
+////////////////////////////////////////////////////////////////////
+//
+// The RISC-V ISA decoder
+//
+
+decode OPCODE default Unknown::unknown() {
+ 0x03: decode FUNCT3 {
+ format Load {
+ 0x0: lb({{
+ Rd_sd = Mem_sb;
+ }});
+ 0x1: lh({{
+ Rd_sd = Mem_sh;
+ }});
+ 0x2: lw({{
+ Rd_sd = Mem_sw;
+ }});
+ 0x3: ld({{
+ Rd_sd = Mem_sd;
+ }});
+ 0x4: lbu({{
+ Rd = Mem_ub;
+ }});
+ 0x5: lhu({{
+ Rd = Mem_uh;
+ }});
+ 0x6: lwu({{
+ Rd = Mem_uw;
+ }});
+ }
+ }
+
+ 0x0f: decode FUNCT3 {
+ format IOp {
+ 0x0: fence({{
+ }}, IsNonSpeculative, IsMemBarrier, No_OpClass);
+ 0x1: fence_i({{
+ }}, IsNonSpeculative, IsSerializeAfter, No_OpClass);
+ }
+ }
+
+ 0x13: decode FUNCT3 {
+ format IOp {
+ 0x0: addi({{
+ Rd_sd = Rs1_sd + imm;
+ }});
+ 0x1: slli({{
+ Rd = Rs1 << SHAMT6;
+ }});
+ 0x2: slti({{
+ Rd = (Rs1_sd < imm) ? 1 : 0;
+ }});
+ 0x3: sltiu({{
+ Rd = (Rs1 < (uint64_t)imm) ? 1 : 0;
+ }});
+ 0x4: xori({{
+ Rd = Rs1 ^ (uint64_t)imm;
+ }});
+ 0x5: decode SRTYPE {
+ 0x0: srli({{
+ Rd = Rs1 >> SHAMT6;
+ }});
+ 0x1: srai({{
+ Rd_sd = Rs1_sd >> SHAMT6;
+ }});
+ }
+ 0x6: ori({{
+ Rd = Rs1 | (uint64_t)imm;
+ }});
+ 0x7: andi({{
+ Rd = Rs1 & (uint64_t)imm;
+ }});
+ }
+ }
+
+ 0x17: UOp::auipc({{
+ Rd = PC + imm;
+ }});
+
+ 0x1b: decode FUNCT3 {
+ format IOp {
+ 0x0: addiw({{
+ Rd_sd = (int32_t)Rs1 + (int32_t)imm;
+ }});
+ 0x1: slliw({{
+ Rd_sd = Rs1_sw << SHAMT5;
+ }});
+ 0x5: decode SRTYPE {
+ 0x0: srliw({{
+ Rd = Rs1_uw >> SHAMT5;
+ }});
+ 0x1: sraiw({{
+ Rd_sd = Rs1_sw >> SHAMT5;
+ }});
+ }
+ }
+ }
+
+ 0x23: decode FUNCT3 {
+ format Store {
+ 0x0: sb({{
+ Mem_ub = Rs2_ub;
+ }});
+ 0x1: sh({{
+ Mem_uh = Rs2_uh;
+ }});
+ 0x2: sw({{
+ Mem_uw = Rs2_uw;
+ }});
+ 0x3: sd({{
+ Mem_ud = Rs2_ud;
+ }});
+ }
+ }
+
+ 0x33: decode FUNCT3 {
+ format ROp {
+ 0x0: decode FUNCT7 {
+ 0x0: add({{
+ Rd = Rs1_sd + Rs2_sd;
+ }});
+ 0x20: sub({{
+ Rd = Rs1_sd - Rs2_sd;
+ }});
+ }
+ 0x1: decode FUNCT7 {
+ 0x0: sll({{
+ Rd = Rs1 << Rs2<5:0>;
+ }});
+ }
+ 0x2: decode FUNCT7 {
+ 0x0: slt({{
+ Rd = (Rs1_sd < Rs2_sd) ? 1 : 0;
+ }});
+ }
+ 0x3: decode FUNCT7 {
+ 0x0: sltu({{
+ Rd = (Rs1 < Rs2) ? 1 : 0;
+ }});
+ }
+ 0x4: decode FUNCT7 {
+ 0x0: xor({{
+ Rd = Rs1 ^ Rs2;
+ }});
+ }
+ 0x5: decode FUNCT7 {
+ 0x0: srl({{
+ Rd = Rs1 >> Rs2<5:0>;
+ }});
+ 0x20: sra({{
+ Rd_sd = Rs1_sd >> Rs2<5:0>;
+ }});
+ }
+ 0x6: decode FUNCT7 {
+ 0x0: or({{
+ Rd = Rs1 | Rs2;
+ }});
+ }
+ 0x7: decode FUNCT7 {
+ 0x0: and({{
+ Rd = Rs1 & Rs2;
+ }});
+ }
+ }
+ }
+
+ 0x37: UOp::lui({{
+ Rd = (uint64_t)imm;
+ }});
+
+ 0x3b: decode FUNCT3 {
+ format ROp {
+ 0x0: decode FUNCT7 {
+ 0x0: addw({{
+ Rd_sd = Rs1_sw + Rs2_sw;
+ }});
+ 0x20: subw({{
+ Rd_sd = Rs1_sw - Rs2_sw;
+ }});
+ }
+ 0x1: sllw({{
+ Rd_sd = Rs1_sw << Rs2<4:0>;
+ }});
+ 0x5: decode FUNCT7 {
+ 0x0: srlw({{
+ Rd_uw = Rs1_uw >> Rs2<4:0>;
+ }});
+ 0x20: sraw({{
+ Rd_sd = Rs1_sw >> Rs2<4:0>;
+ }});
+ }
+ }
+ }
+
+ 0x63: decode FUNCT3 {
+ format SBOp {
+ 0x0: beq({{
+ if (Rs1 == Rs2) {
+ NPC = PC + imm;
+ } else {
+ NPC = NPC;
+ }
+ }}, IsDirectControl, IsCondControl);
+ 0x1: bne({{
+ if (Rs1 != Rs2) {
+ NPC = PC + imm;
+ } else {
+ NPC = NPC;
+ }
+ }}, IsDirectControl, IsCondControl);
+ 0x4: blt({{
+ if (Rs1_sd < Rs2_sd) {
+ NPC = PC + imm;
+ } else {
+ NPC = NPC;
+ }
+ }}, IsDirectControl, IsCondControl);
+ 0x5: bge({{
+ if (Rs1_sd >= Rs2_sd) {
+ NPC = PC + imm;
+ } else {
+ NPC = NPC;
+ }
+ }}, IsDirectControl, IsCondControl);
+ 0x6: bltu({{
+ if (Rs1 < Rs2) {
+ NPC = PC + imm;
+ } else {
+ NPC = NPC;
+ }
+ }}, IsDirectControl, IsCondControl);
+ 0x7: bgeu({{
+ if (Rs1 >= Rs2) {
+ NPC = PC + imm;
+ } else {
+ NPC = NPC;
+ }
+ }}, IsDirectControl, IsCondControl);
+ }
+ }
+
+ 0x67: decode FUNCT3 {
+ 0x0: Jump::jalr({{
+ Rd = NPC;
+ NPC = (imm + Rs1) & (~0x1);
+ }}, IsIndirectControl, IsUncondControl, IsCall);
+ }
+
+ 0x6f: UJOp::jal({{
+ Rd = NPC;
+ NPC = PC + imm;
+ }}, IsDirectControl, IsUncondControl, IsCall);
+
+ 0x73: decode FUNCT3 {
+ format IOp {
+ 0x0: decode FUNCT12 {
+ 0x0: ecall({{
+ fault = std::make_shared<SyscallFault>();
+ }}, IsSerializeAfter, IsNonSpeculative, IsSyscall, No_OpClass);
+ 0x1: ebreak({{
+ fault = std::make_shared<BreakpointFault>();
+ }}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
+ 0x100: eret({{
+ fault = std::make_shared<UnimplementedFault>("eret");
+ }}, No_OpClass);
+ }
+ 0x1: csrrw({{
+ Rd = xc->readMiscReg(FUNCT12);
+ xc->setMiscReg(FUNCT12, Rs1);
+ }}, IsNonSpeculative, No_OpClass);
+ 0x2: csrrs({{
+ Rd = xc->readMiscReg(FUNCT12);
+ if (Rs1 != 0) {
+ xc->setMiscReg(FUNCT12, Rd | Rs1);
+ }
+ }}, IsNonSpeculative, No_OpClass);
+ 0x3: csrrc({{
+ Rd = xc->readMiscReg(FUNCT12);
+ if (Rs1 != 0) {
+ xc->setMiscReg(FUNCT12, Rd & ~Rs1);
+ }
+ }}, IsNonSpeculative, No_OpClass);
+ 0x5: csrrwi({{
+ Rd = xc->readMiscReg(FUNCT12);
+ xc->setMiscReg(FUNCT12, ZIMM);
+ }}, IsNonSpeculative, No_OpClass);
+ 0x6: csrrsi({{
+ Rd = xc->readMiscReg(FUNCT12);
+ if (ZIMM != 0) {
+ xc->setMiscReg(FUNCT12, Rd | ZIMM);
+ }
+ }}, IsNonSpeculative, No_OpClass);
+ 0x7: csrrci({{
+ Rd = xc->readMiscReg(FUNCT12);
+ if (ZIMM != 0) {
+ xc->setMiscReg(FUNCT12, Rd & ~ZIMM);
+ }
+ }}, IsNonSpeculative, No_OpClass);
+ }
+ }
+}
--- /dev/null
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Maxwell Walter
+// Alec Roelke
+
+// Declarations for execute() methods.
+def template BasicExecDeclare {{
+ Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+}};
+
+// Basic instruction class declaration template.
+def template BasicDeclare {{
+ //
+ // Static instruction class for "%(mnemonic)s".
+ //
+ class %(class_name)s : public %(base_class)s
+ {
+ public:
+ /// Constructor.
+ %(class_name)s(MachInst machInst);
+ %(BasicExecDeclare)s
+ using %(base_class)s::generateDisassembly;
+ };
+}};
+
+// Basic instruction class constructor template.
+def template BasicConstructor {{
+ %(class_name)s::%(class_name)s(MachInst machInst)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+ {
+ %(constructor)s;
+ }
+}};
+
+
+// Basic instruction class execute method template.
+def template BasicExecute {{
+ Fault
+ %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+ %(op_rd)s;
+ if (fault == NoFault) {
+ %(code)s;
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+ }
+ return fault;
+ }
+}};
+
+// Basic decode template.
+def template BasicDecode {{
+ return new %(class_name)s(machInst);
+}};
+
+// Basic decode template, passing mnemonic in as string arg to constructor.
+def template BasicDecodeWithMnemonic {{
+ return new %(class_name)s("%(mnemonic)s", machInst);
+}};
+
+// The most basic instruction format...
+def format BasicOp(code, *flags) {{
+ iop = InstObjParams(name, Name, 'RiscvStaticInst', code, flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
--- /dev/null
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Maxwell Walter
+// Alec Roelke
+
+// Include the basic format
+##include "basic.isa"
+
+//Include the type formats
+##include "type.isa"
+##include "mem.isa"
+
+// Include the unknown
+##include "unknown.isa"
+
--- /dev/null
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Alec Roelke
+
+////////////////////////////////////////////////////////////////////
+//
+// Memory operation instructions
+//
+output header {{
+ class Load : public RiscvStaticInst
+ {
+ public:
+ /// Displacement for EA calculation (signed).
+ int64_t ldisp;
+
+ protected:
+ /// Memory request flags. See mem_req_base.hh.
+ Request::Flags memAccessFlags;
+
+ /// Constructor
+ Load(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
+ : RiscvStaticInst(mnem, _machInst, __opClass), ldisp(IMM12)
+ {
+ if (IMMSIGN > 0)
+ ldisp |= ~((uint64_t)0xFFF);
+ }
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+ class Store : public RiscvStaticInst
+ {
+ public:
+ /// Displacement for EA calculation (signed).
+ int64_t sdisp;
+
+ protected:
+ /// Memory request flags. See mem_req_base.hh.
+ Request::Flags memAccessFlags;
+
+ /// Constructor
+ Store(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
+ : RiscvStaticInst(mnem, _machInst, __opClass), sdisp(IMM5)
+ {
+ sdisp |= IMM7 << 5;
+ if (IMMSIGN > 0)
+ sdisp |= ~((uint64_t)0xFFF);
+ }
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+}};
+
+
+output decoder {{
+ std::string
+ Load::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+ ss << mnemonic << ' ' << regName(_destRegIdx[0]) << ", " << ldisp <<
+ '(' << regName(_srcRegIdx[0]) << ')';
+ return ss.str();
+ }
+
+ std::string
+ Store::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+ ss << mnemonic << ' ' << regName(_srcRegIdx[1]) << ", " << sdisp <<
+ '(' << regName(_srcRegIdx[0]) << ')';
+ return ss.str();
+ }
+}};
+
+def template LoadStoreDeclare {{
+ /**
+ * Static instruction class for "%(mnemonic)s".
+ */
+ class %(class_name)s : public %(base_class)s
+ {
+ public:
+ /// Constructor.
+ %(class_name)s(ExtMachInst machInst);
+
+ %(BasicExecDeclare)s
+
+ %(EACompDeclare)s
+
+ %(InitiateAccDeclare)s
+
+ %(CompleteAccDeclare)s
+ };
+}};
+
+def template EACompDeclare {{
+ Fault
+ eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+}};
+
+def template InitiateAccDeclare {{
+ Fault
+ initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+}};
+
+
+def template CompleteAccDeclare {{
+ Fault
+ completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
+}};
+
+def template LoadStoreConstructor {{
+ %(class_name)s::%(class_name)s(ExtMachInst machInst):
+ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+ {
+ %(constructor)s;
+ }
+}};
+
+def template EACompExecute {{
+ Fault
+ %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Addr EA;
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ xc->setEA(EA);
+ }
+
+ return fault;
+ }
+}};
+
+let {{
+def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+ base_class, postacc_code='', decode_template=BasicDecode,
+ exec_template_base=''):
+ # Make sure flags are in lists (convert to lists if not).
+ mem_flags = makeList(mem_flags)
+ inst_flags = makeList(inst_flags) # + ['IsNonSpeculative']
+
+ iop = InstObjParams(name, Name, base_class,
+ { 'ea_code':ea_code, 'memacc_code':memacc_code,
+ 'postacc_code':postacc_code }, inst_flags)
+
+ if mem_flags:
+ mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
+ s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
+ iop.constructor += s
+
+ # select templates
+
+ fullExecTemplate = eval(exec_template_base + 'Execute')
+ initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
+ completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
+
+ # (header_output, decoder_output, decode_block, exec_output)
+ return (LoadStoreDeclare.subst(iop),
+ LoadStoreConstructor.subst(iop),
+ decode_template.subst(iop),
+ fullExecTemplate.subst(iop) +
+ EACompExecute.subst(iop) +
+ initiateAccTemplate.subst(iop) +
+ completeAccTemplate.subst(iop))
+}};
+
+def template LoadExecute {{
+ Fault
+ %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Addr EA;
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+
+ if (fault == NoFault) {
+ fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
+ %(memacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+
+ return fault;
+ }
+}};
+
+def template LoadInitiateAcc {{
+ Fault
+ %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Addr EA;
+ Fault fault = NoFault;
+
+ %(op_src_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+
+ if (fault == NoFault) {
+ fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags);
+ }
+
+ return fault;
+ }
+}};
+
+def template LoadCompleteAcc {{
+ Fault
+ %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+ %(op_rd)s;
+
+ getMem(pkt, Mem, traceData);
+
+ if (fault == NoFault) {
+ %(memacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+
+ return fault;
+ }
+}};
+
+def template StoreExecute {{
+ Fault
+ %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Addr EA;
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+
+ if (fault == NoFault) {
+ %(memacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
+ nullptr);
+ }
+
+ if (fault == NoFault) {
+ %(postacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+
+ return fault;
+ }
+}};
+
+def template StoreInitiateAcc {{
+ Fault
+ %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Addr EA;
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+
+ if (fault == NoFault) {
+ %(memacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ fault = writeMemTiming(xc, traceData, Mem, EA,
+ memAccessFlags, nullptr);
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+
+ return fault;
+ }
+}};
+
+def template StoreCompleteAcc {{
+ Fault
+ %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT *xc,
+ Trace::InstRecord *traceData) const
+ {
+ return NoFault;
+ }
+}};
+
+def format Load(memacc_code, ea_code = {{EA = Rs1 + ldisp;}}, mem_flags=[],
+ inst_flags=[]) {{
+ (header_output, decoder_output, decode_block, exec_output) = \
+ LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+ 'Load', exec_template_base='Load')
+}};
+
+def format Store(memacc_code, ea_code={{EA = Rs1 + sdisp;}}, mem_flags=[],
+ inst_flags=[]) {{
+ (header_output, decoder_output, decode_block, exec_output) = \
+ LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+ 'Store', exec_template_base='Store')
+}};
--- /dev/null
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Alec Roelke
+
+////////////////////////////////////////////////////////////////////
+//
+// Integer instructions
+//
+output header {{
+ #include <iostream>
+ /**
+ * Base class for R-type operations
+ */
+ class ROp : public RiscvStaticInst
+ {
+ protected:
+ /// Constructor
+ ROp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : RiscvStaticInst(mnem, _machInst, __opClass)
+ {}
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+ /**
+ * Base class for I-type operations
+ */
+ class IOp : public RiscvStaticInst
+ {
+ protected:
+ int64_t imm;
+
+ /// Constructor
+ IOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : RiscvStaticInst(mnem, _machInst, __opClass),imm(IMM12)
+ {
+ if (IMMSIGN > 0)
+ imm |= ~((uint64_t)0x7FF);
+ }
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+ /**
+ * Class for jalr instructions
+ */
+ class Jump : public IOp
+ {
+ protected:
+ Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : IOp(mnem, _machInst, __opClass)
+ {}
+
+ RiscvISA::PCState
+ branchTarget(ThreadContext *tc) const;
+
+ using StaticInst::branchTarget;
+ using IOp::generateDisassembly;
+ };
+
+ /**
+ * Base class for S-type operations
+ */
+ class SOp : public RiscvStaticInst
+ {
+ protected:
+ int64_t imm;
+
+ /// Constructor
+ SOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : RiscvStaticInst(mnem, _machInst, __opClass),imm(0)
+ {
+ imm |= IMM5;
+ imm |= IMM7 << 5;
+ if (IMMSIGN > 0)
+ imm |= ~((uint64_t)0x7FF);
+ }
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+ /**
+ * Base class for SB-type operations
+ */
+ class SBOp : public RiscvStaticInst
+ {
+ protected:
+ int64_t imm;
+
+ /// Constructor
+ SBOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : RiscvStaticInst(mnem, _machInst, __opClass),imm(0)
+ {
+ imm |= BIMM12BIT11 << 11;
+ imm |= BIMM12BITS4TO1 << 1;
+ imm |= BIMM12BITS10TO5 << 5;
+ if (IMMSIGN > 0)
+ imm |= ~((uint64_t)0xFFF);
+ }
+
+ RiscvISA::PCState
+ branchTarget(const RiscvISA::PCState &branchPC) const;
+
+ using StaticInst::branchTarget;
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+ /**
+ * Base class for U-type operations
+ */
+ class UOp : public RiscvStaticInst
+ {
+ protected:
+ int64_t imm;
+
+ /// Constructor
+ UOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
+ {
+ int32_t temp = IMM20 << 12;
+ imm = temp;
+ }
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+ /**
+ * Base class for UJ-type operations
+ */
+ class UJOp : public RiscvStaticInst
+ {
+ protected:
+ int64_t imm;
+
+ /// Constructor
+ UJOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : RiscvStaticInst(mnem, _machInst, __opClass),imm(0)
+ {
+ imm |= UJIMMBITS19TO12 << 12;
+ imm |= UJIMMBIT11 << 11;
+ imm |= UJIMMBITS10TO1 << 1;
+ if (IMMSIGN > 0)
+ imm |= ~((uint64_t)0xFFFFF);
+ }
+
+ RiscvISA::PCState
+ branchTarget(const RiscvISA::PCState &branchPC) const;
+
+ using StaticInst::branchTarget;
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+}};
+
+//Outputs to decoder.cc
+output decoder {{
+ std::string
+ ROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+ ss << mnemonic << ' ' << regName(_destRegIdx[0]) << ", " <<
+ regName(_srcRegIdx[0]) << ", " << regName(_srcRegIdx[1]);
+ return ss.str();
+ }
+
+ std::string
+ IOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+ ss << mnemonic << ' ' << regName(_destRegIdx[0]) << ", " <<
+ regName(_srcRegIdx[0]) << ", " << imm;
+ return ss.str();
+ }
+
+ RiscvISA::PCState
+ Jump::branchTarget(ThreadContext *tc) const
+ {
+ PCState pc = tc->pcState();
+ IntReg Rs1 = tc->readIntReg(_srcRegIdx[0]);
+ pc.set((Rs1 + imm)&~0x1);
+ return pc;
+ }
+
+ std::string
+ SOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+ ss << mnemonic << ' ' << regName(_srcRegIdx[1]) << ", " << imm <<
+ '(' << regName(_srcRegIdx[0]) << ')';
+ return ss.str();
+ }
+
+ RiscvISA::PCState
+ SBOp::branchTarget(const RiscvISA::PCState &branchPC) const
+ {
+ return branchPC.pc() + imm;
+ }
+
+ std::string
+ SBOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+ ss << mnemonic << ' ' << regName(_srcRegIdx[0]) << ", " <<
+ regName(_srcRegIdx[1]) << ", " << imm;
+ return ss.str();
+ }
+
+ std::string
+ UOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+ ss << mnemonic << ' ' << regName(_destRegIdx[0]) << ", " << imm;
+ return ss.str();
+ }
+
+ RiscvISA::PCState
+ UJOp::branchTarget(const RiscvISA::PCState &branchPC) const
+ {
+ return branchPC.pc() + imm;
+ }
+
+ std::string
+ UJOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+ ss << mnemonic << ' ' << regName(_destRegIdx[0]) << ", " << imm;
+ return ss.str();
+ }
+}};
+
+def format ROp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'ROp', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
+
+def format IOp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'IOp', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
+
+def format Jump(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'Jump', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
+
+def format SOp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'SOp', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
+
+def format SBOp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'SBOp', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
+
+def format UOp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'UOp', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
+
+def format UJOp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'UJOp', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
--- /dev/null
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Maxwell Walter
+// Alec Roelke
+
+////////////////////////////////////////////////////////////////////
+//
+// Unknown instructions
+//
+
+output header {{
+ /**
+ * Static instruction class for unknown (illegal) instructions.
+ * These cause simulator termination if they are executed in a
+ * non-speculative mode. This is a leaf class.
+ */
+ class Unknown : public RiscvStaticInst
+ {
+ public:
+ /// Constructor
+ Unknown(MachInst _machInst)
+ : RiscvStaticInst("unknown", _machInst, No_OpClass)
+ {
+ flags[IsNonSpeculative] = true;
+ }
+
+ %(BasicExecDeclare)s
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+}};
+
+output decoder {{
+ std::string
+ Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ return csprintf("unknown opcode 0x%02x", OPCODE);
+ }
+}};
+
+output exec {{
+ Fault
+ Unknown::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = std::make_shared<UnknownInstFault>();
+ return fault;
+ }
+}};
+
+def format Unknown() {{
+ decode_block = 'return new Unknown(machInst);\n'
+}};
--- /dev/null
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Maxwell Walter
+// Alec Roelke
+
+////////////////////////////////////////////////////////////////////
+//
+// Output include file directives.
+//
+
+output header {{
+#include <iomanip>
+#include <sstream>
+#include <string>
+#include <tuple>
+#include <vector>
+
+#include "cpu/static_inst.hh"
+#include "mem/packet.hh"
+#include "mem/request.hh"
+
+}};
+
+output decoder {{
+#include <cfenv>
+#include <cmath>
+#include <limits>
+#include <string>
+
+#include "arch/riscv/decoder.hh"
+#include "arch/riscv/faults.hh"
+#include "arch/riscv/tlb.hh"
+#include "base/cprintf.hh"
+#include "base/loader/symtab.hh"
+#include "cpu/thread_context.hh"
+#include "mem/packet.hh"
+#include "mem/request.hh"
+#include "sim/full_system.hh"
+
+using namespace RiscvISA;
+}};
+
+output exec {{
+#include <cmath>
+#include <string>
+
+#include "arch/generic/memhelpers.hh"
+#include "arch/riscv/faults.hh"
+#include "arch/riscv/registers.hh"
+#include "base/condcodes.hh"
+#include "cpu/base.hh"
+#include "cpu/exetrace.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+#include "mem/request.hh"
+#include "sim/eventq.hh"
+#include "sim/full_system.hh"
+#include "sim/sim_events.hh"
+#include "sim/sim_exit.hh"
+#include "sim/system.hh"
+
+using namespace RiscvISA;
+}};
--- /dev/null
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Maxwell Walter
+// Alec Roelke
+
+////////////////////////////////////////////////////////////////////
+//
+// RISCV ISA description file.
+//
+////////////////////////////////////////////////////////////////////
+
+//Include the C++ include directives
+##include "includes.isa"
+
+////////////////////////////////////////////////////////////////////
+//
+// Namespace statement. Everything below this line will be in the
+// RiscvISAInst namespace.
+//
+
+namespace RiscvISA;
+
+//Include the bitfield definitions
+##include "bitfields.isa"
+
+//Include the operand_types and operand definitions
+##include "operands.isa"
+
+//Include the base class for riscv instructions, and some support code
+##include "base.isa"
+
+//Include the definitions for the instruction formats
+##include "formats/formats.isa"
+
+//Include the decoder definition
+##include "decoder.isa"
--- /dev/null
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Maxwell Walter
+// Alec Roelke
+
+def operand_types {{
+ 'sb' : 'int8_t',
+ 'ub' : 'uint8_t',
+ 'sh' : 'int16_t',
+ 'uh' : 'uint16_t',
+ 'sw' : 'int32_t',
+ 'uw' : 'uint32_t',
+ 'sd' : 'int64_t',
+ 'ud' : 'uint64_t',
+}};
+
+def operands {{
+#General Purpose Integer Reg Operands
+ 'Rd': ('IntReg', 'ud', 'RD', 'IsInteger', 1),
+ 'Rs1': ('IntReg', 'ud', 'RS1', 'IsInteger', 2),
+ 'Rs2': ('IntReg', 'ud', 'RS2', 'IsInteger', 3),
+
+#Memory Operand
+ 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 5),
+
+#Program Counter Operands
+ 'PC': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 7),
+ 'NPC': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 8),
+}};
--- /dev/null
+/*
+ * Copyright (c) 2013 ARM Limited
+ * Copyright (c) 2014-2015 Sven Karlsson
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2016 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Hansson
+ * Sven Karlsson
+ * Alec Roelke
+ */
+
+#ifndef __ARCH_RISCV_ISA_TRAITS_HH__
+#define __ARCH_RISCV_ISA_TRAITS_HH__
+
+#include "arch/riscv/types.hh"
+#include "base/types.hh"
+#include "cpu/static_inst_fwd.hh"
+
+namespace LittleEndianGuest {}
+
+namespace RiscvISA
+{
+
+using namespace LittleEndianGuest;
+
+// Riscv does NOT have a delay slot
+#define ISA_HAS_DELAY_SLOT 0
+
+const Addr PageShift = 12;
+const Addr PageBytes = ULL(1) << PageShift;
+
+// Memory accesses can not be unaligned
+const bool HasUnalignedMemAcc = false;
+
+const bool CurThreadInfoImplemented = false;
+const int CurThreadInfoReg = -1;
+
+}
+
+#endif //__ARCH_RISCV_ISA_TRAITS_HH__
--- /dev/null
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Lisa Hsu
+ * Nathan Binkert
+ */
+
+#ifndef __ARCH_RISCV_KERNEL_STATS_HH__
+#define __ARCH_RISCV_KERNEL_STATS_HH__
+
+#include "kern/kernel_stats.hh"
+
+namespace RiscvISA {
+namespace Kernel {
+
+enum cpu_mode { kernel, user, idle, cpu_mode_num };
+extern const char *modestr[];
+
+class Statistics : public ::Kernel::Statistics
+{
+ public:
+ Statistics(System *system) : ::Kernel::Statistics(system)
+ {}
+};
+
+
+} // namespace RiscvISA::Kernel
+} // namespace RiscvISA
+
+#endif // __ARCH_RISCV_KERNEL_STATS_HH__
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
+ */
+
+#include "arch/riscv/linux/linux.hh"
+
+#include <fcntl.h>
+#include <sys/mman.h>
+
+#define TARGET RiscvLinux
+#include "kern/linux/flag_tables.hh"
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
+ */
+
+#ifndef __ARCH_RISCV_LINUX_LINUX_HH__
+#define __ARCH_RISCV_LINUX_LINUX_HH__
+
+#include "kern/linux/linux.hh"
+
+class RiscvLinux : public Linux
+{
+ public:
+
+ static const int TGT_SIGHUP = 0x000001;
+ static const int TGT_SIGINT = 0x000002;
+ static const int TGT_SIGQUIT = 0x000003;
+ static const int TGT_SIGILL = 0x000004;
+ static const int TGT_SIGTRAP = 0x000005;
+ static const int TGT_SIGIOT = 0x000006;
+ static const int TGT_SIGABRT = 0x000006;
+ static const int TGT_SIGEMT = 0x000007;
+ static const int TGT_SIGFPE = 0x000008;
+ static const int TGT_SIGKILL = 0x000009;
+ static const int TGT_SIGBUS = 0x00000a;
+ static const int TGT_SIGSEGV = 0x00000b;
+ static const int TGT_SIGSYS = 0x00000c;
+ static const int TGT_SIGPIPE = 0x00000d;
+ static const int TGT_SIGALRM = 0x00000e;
+ static const int TGT_SIGTERM = 0x00000f;
+ static const int TGT_SIGUSR1 = 0x000010;
+ static const int TGT_SIGUSR2 = 0x000011;
+ static const int TGT_SIGCHLD = 0x000012;
+ static const int TGT_SIGCLD = 0x000012;
+ static const int TGT_SIGPWR = 0x000013;
+ static const int TGT_SIGWINCH = 0x000014;
+ static const int TGT_SIGURG = 0x000015;
+ static const int TGT_SIGIO = 0x000016;
+ static const int TGT_SIGPOLL = 0x000016;
+ static const int TGT_SIGSTOP = 0x000017;
+ static const int TGT_SIGTSTP = 0x000018;
+ static const int TGT_SIGCONT = 0x000019;
+ static const int TGT_SIGTTIN = 0x00001a;
+ static const int TGT_SIGTTOU = 0x00001b;
+ static const int TGT_SIGVTALRM = 0x00001c;
+ static const int TGT_SIGPROF = 0x00001d;
+ static const int TGT_SIGXCPU = 0x00001e;
+ static const int TGT_SIGXFSZ = 0x00001f;
+
+ /// This table maps the target open() flags to the corresponding
+ /// host open() flags.
+ static SyscallFlagTransTable openFlagTable[];
+
+ /// Number of entries in openFlagTable[].
+ static const int NUM_OPEN_FLAGS;
+
+ //@{
+ /// open(2) flag values.
+ static const int TGT_O_RDONLY = 0x00000000; //!< O_RDONLY
+ static const int TGT_O_WRONLY = 0x00000001; //!< O_WRONLY
+ static const int TGT_O_RDWR = 0x00000002; //!< O_RDWR
+ static const int TGT_O_CREAT = 0x00000100; //!< O_CREAT
+ static const int TGT_O_EXCL = 0x00000400; //!< O_EXCL
+ static const int TGT_O_NOCTTY = 0x00000800; //!< O_NOCTTY
+ static const int TGT_O_TRUNC = 0x00000200; //!< O_TRUNC
+ static const int TGT_O_APPEND = 0x00000008; //!< O_APPEND
+ static const int TGT_O_NONBLOCK = 0x00000080; //!< O_NONBLOCK
+ static const int TGT_O_DSYNC = 0x00000010; //!< O_DSYNC
+ static const int TGT_FASYNC = 0x00001000; //!< O_FASYNC
+ static const int TGT_O_DIRECT = 0x00008000; //!< O_DIRECT
+ static const int TGT_O_LARGEFILE = 0x00002000; //!< O_LARGEFILE
+ static const int TGT_O_DIRECTORY = 0x00010000; //!< O_DIRECTORY
+ static const int TGT_O_NOFOLLOW = 0x00020000; //!< O_NOFOLLOW
+ static const int TGT_O_NOATIME = 0x00040000; //!< O_NOATIME
+ static const int TGT_O_CLOEXEC = 0x00080000; //!< O_CLOEXEC
+ static const int TGT_O_SYNC = 0x00004010; //!< O_SYNC
+ static const int TGT_O_PATH = 0x00200000; //!< O_PATH
+ //@}
+
+ static const unsigned TGT_MAP_SHARED = 0x00001;
+ static const unsigned TGT_MAP_PRIVATE = 0x00002;
+ static const unsigned TGT_MAP_ANON = 0x00800;
+ static const unsigned TGT_MAP_DENYWRITE = 0x02000;
+ static const unsigned TGT_MAP_EXECUTABLE = 0x04000;
+ static const unsigned TGT_MAP_FILE = 0x00000;
+ static const unsigned TGT_MAP_GROWSDOWN = 0x01000;
+ static const unsigned TGT_MAP_HUGETLB = 0x80000;
+ static const unsigned TGT_MAP_LOCKED = 0x08000;
+ static const unsigned TGT_MAP_NONBLOCK = 0x20000;
+ static const unsigned TGT_MAP_NORESERVE = 0x00400;
+ static const unsigned TGT_MAP_POPULATE = 0x10000;
+ static const unsigned TGT_MAP_STACK = 0x40000;
+ static const unsigned TGT_MAP_ANONYMOUS = 0x00800;
+ static const unsigned TGT_MAP_FIXED = 0x00010;
+
+ static const unsigned NUM_MMAP_FLAGS;
+
+ //@{
+ /// For getsysinfo().
+ static const unsigned GSI_PLATFORM_NAME = 103; //!< platform name as string
+ static const unsigned GSI_CPU_INFO = 59; //!< CPU information
+ static const unsigned GSI_PROC_TYPE = 60; //!< get proc_type
+ static const unsigned GSI_MAX_CPU = 30; //!< max # cpus
+ static const unsigned GSI_CPUS_IN_BOX = 55; //!< # of CPUs in system
+ static const unsigned GSI_PHYSMEM = 19; //!< Physical memory in KB
+ static const unsigned GSI_CLK_TCK = 42; //!< clock freq in Hz
+ //@}
+
+ //@{
+ /// For setsysinfo().
+ static const unsigned SSI_IEEE_FP_CONTROL = 14; //!< ieee_set_fp_control()
+ //@}
+
+ //@{
+ /// ioctl() command codes.
+ static const unsigned TGT_TCGETA = 0x5401;
+ static const unsigned TGT_TCSETAW = 0x5403;
+ static const unsigned TGT_TCGETS = 0x540d;
+ static const unsigned TGT_FIONREAD = 0x467f;
+ static const unsigned TGT_TIOCGETP = 0x7408;
+ static const unsigned TGT_TIOCSETP = 0x7409;
+ static const unsigned TGT_TIOCSETN = 0x740a;
+ //@}
+
+ static bool
+ isTtyReq(unsigned req)
+ {
+ switch (req) {
+ case TGT_TIOCGETP:
+ case TGT_TIOCSETP:
+ case TGT_TIOCSETN:
+ case TGT_FIONREAD:
+ case TGT_TCGETS:
+ case TGT_TCGETA:
+ case TGT_TCSETAW:
+ return true;
+ default:
+ return false;
+ }
+ }
+
+ /// For table().
+ static const int TBL_SYSINFO = 12;
+
+ /// Resource constants for getrlimit() (overide some generics).
+ static const unsigned TGT_RLIMIT_NPROC = 8;
+ static const unsigned TGT_RLIMIT_AS = 6;
+ static const unsigned TGT_RLIMIT_RSS = 7;
+ static const unsigned TGT_RLIMIT_NOFILE = 5;
+ static const unsigned TGT_RLIMIT_MEMLOCK = 9;
+
+ /// Offset used to make sure that processes don't
+ /// assign themselves to process IDs reserved for
+ /// the root users.
+ static const int NUM_ROOT_PROCS = 2;
+
+ typedef struct {
+ int32_t uptime; /* Seconds since boot */
+ uint32_t loads[3]; /* 1, 5, and 15 minute load averages */
+ uint32_t totalram; /* Total usable main memory size */
+ uint32_t freeram; /* Available memory size */
+ uint32_t sharedram; /* Amount of shared memory */
+ uint32_t bufferram; /* Memory used by buffers */
+ uint32_t totalswap; /* Total swap space size */
+ uint32_t freeswap; /* swap space still available */
+ uint16_t procs; /* Number of current processes */
+ uint32_t totalhigh; /* Total high memory size */
+ uint32_t freehigh; /* Available high memory size */
+ uint32_t mem_unit; /* Memory unit size in bytes */
+ } tgt_sysinfo;
+
+};
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * Copyright (c) 2016 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ * Korey Sewell
+ * Alec Roelke
+ */
+
+#include "arch/riscv/linux/process.hh"
+
+#include <map>
+
+#include "arch/riscv/isa_traits.hh"
+#include "arch/riscv/linux/linux.hh"
+#include "base/trace.hh"
+#include "cpu/thread_context.hh"
+#include "debug/SyscallVerbose.hh"
+#include "kern/linux/linux.hh"
+#include "sim/eventq.hh"
+#include "sim/process.hh"
+#include "sim/syscall_emul.hh"
+#include "sim/system.hh"
+
+using namespace std;
+using namespace RiscvISA;
+
+/// Target uname() handler.
+static SyscallReturn
+unameFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
+ ThreadContext *tc)
+{
+ int index = 0;
+ TypedBufferArg<Linux::utsname> name(process->getSyscallArg(tc, index));
+
+ strcpy(name->sysname, "Linux");
+ strcpy(name->nodename,"sim.gem5.org");
+ strcpy(name->release, "3.0.0");
+ strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
+ strcpy(name->machine, "riscv");
+
+ name.copyOut(tc->getMemProxy());
+ return 0;
+}
+
+std::map<int, SyscallDesc> RiscvLinuxProcess::syscallDescs = {
+ {17, SyscallDesc("getcwd", getcwdFunc)},
+ {23, SyscallDesc("dup", dupFunc)},
+ {25, SyscallDesc("fcntl", fcntlFunc)},
+ {29, SyscallDesc("ioctl", ioctlFunc<RiscvLinux>)},
+ {34, SyscallDesc("mkdirat", unimplementedFunc)},
+ {35, SyscallDesc("unlinkat", unlinkatFunc<RiscvLinux>)},
+ {37, SyscallDesc("linkat", unimplementedFunc)},
+ {38, SyscallDesc("renameat", renameatFunc<RiscvLinux>)},
+ {46, SyscallDesc("ftruncate", ftruncateFunc)},
+ {48, SyscallDesc("faccessat", faccessatFunc<RiscvLinux>)},
+ {49, SyscallDesc("chdir", unimplementedFunc)},
+ {56, SyscallDesc("openat", openatFunc<RiscvLinux>)},
+ {57, SyscallDesc("close", closeFunc)},
+ {61, SyscallDesc("getdents", unimplementedFunc)},
+ {62, SyscallDesc("lseek", lseekFunc)},
+ {63, SyscallDesc("read", readFunc)},
+ {64, SyscallDesc("write", writeFunc)},
+ {66, SyscallDesc("writev", writevFunc<RiscvLinux>)},
+ {67, SyscallDesc("pread", unimplementedFunc)},
+ {68, SyscallDesc("pwrite", unimplementedFunc)},
+ {78, SyscallDesc("readlinkat", readlinkatFunc<RiscvLinux>)},
+ {79, SyscallDesc("fstatat", unimplementedFunc)},
+ {80, SyscallDesc("fstat", fstatFunc<RiscvLinux>)},
+ {93, SyscallDesc("exit", exitFunc)},
+ {94, SyscallDesc("exit_group", exitGroupFunc)},
+ {113, SyscallDesc("clock_gettime", clock_gettimeFunc<RiscvLinux>)},
+ {129, SyscallDesc("kill", unimplementedFunc)},
+ {134, SyscallDesc("rt_sigaction", ignoreFunc, SyscallDesc::WarnOnce)},
+ {135, SyscallDesc("rt_sigprocmask", ignoreFunc, SyscallDesc::WarnOnce)},
+ {153, SyscallDesc("times", timesFunc<RiscvLinux>)},
+ {160, SyscallDesc("uname", unameFunc)},
+ {163, SyscallDesc("getrlimit", getrlimitFunc<RiscvLinux>)},
+ {164, SyscallDesc("setrlimit", ignoreFunc)},
+ {165, SyscallDesc("getrusage", getrusageFunc<RiscvLinux>)},
+ {169, SyscallDesc("gettimeofday", gettimeofdayFunc<RiscvLinux>)},
+ {172, SyscallDesc("getpid", getpidFunc)},
+ {174, SyscallDesc("getuid", getuidFunc)},
+ {175, SyscallDesc("geteuid", geteuidFunc)},
+ {176, SyscallDesc("getgid", getgidFunc)},
+ {177, SyscallDesc("getegid", getegidFunc)},
+ {214, SyscallDesc("brk", brkFunc)},
+ {215, SyscallDesc("munmap", munmapFunc)},
+ {216, SyscallDesc("mremap", mremapFunc<RiscvLinux>)},
+ {222, SyscallDesc("mmap", mmapFunc<RiscvLinux>)},
+ {226, SyscallDesc("mprotect", ignoreFunc)},
+ {1024, SyscallDesc("open", openFunc<RiscvLinux>)},
+ {1025, SyscallDesc("link", unimplementedFunc)},
+ {1026, SyscallDesc("unlink", unlinkFunc)},
+ {1030, SyscallDesc("mkdir", mkdirFunc)},
+ {1033, SyscallDesc("access", accessFunc)},
+ {1038, SyscallDesc("stat", statFunc<RiscvLinux>)},
+ {1039, SyscallDesc("lstat", lstatFunc<RiscvLinux>)},
+ {1062, SyscallDesc("time", timeFunc<RiscvLinux>)},
+ {2011, SyscallDesc("getmainvars", unimplementedFunc)},
+};
+
+RiscvLinuxProcess::RiscvLinuxProcess(LiveProcessParams * params,
+ ObjectFile *objFile) : RiscvLiveProcess(params, objFile)
+{}
+
+SyscallDesc*
+RiscvLinuxProcess::getDesc(int callnum)
+{
+ return syscallDescs.find(callnum) != syscallDescs.end() ?
+ &syscallDescs.at(callnum) : nullptr;
+}
--- /dev/null
+/*
+ * Copyright (c) 2004 The Regents of The University of Michigan
+ * Copyright (c) 2016 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ * Korey Sewell
+ * Alec Roelke
+ */
+
+#ifndef __RISCV_LINUX_PROCESS_HH__
+#define __RISCV_LINUX_PROCESS_HH__
+
+#include <map>
+
+#include "arch/riscv/linux/linux.hh"
+#include "arch/riscv/process.hh"
+#include "sim/eventq.hh"
+
+/// A process with emulated Riscv/Linux syscalls.
+class RiscvLinuxProcess : public RiscvLiveProcess
+{
+ public:
+ /// Constructor.
+ RiscvLinuxProcess(LiveProcessParams * params, ObjectFile *objFile);
+
+ virtual SyscallDesc* getDesc(int callnum);
+
+ /// The target system's hostname.
+ static const char *hostname;
+
+ /// ID of the thread group leader for the process
+ uint64_t __tgid;
+
+ /// Array of syscall descriptors, indexed by call number.
+ static std::map<int, SyscallDesc> syscallDescs;
+};
+
+#endif // __RISCV_LINUX_PROCESS_HH__
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2007-2008 The Florida State University
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ * Stephen Hines
+ * Timothy M. Jones
+ */
+
+#ifndef __ARCH_RISCV_LOCKED_MEM_HH__
+#define __ARCH_RISCV_LOCKED_MEM_HH__
+
+/**
+ * @file
+ *
+ * ISA-specific helper functions for locked memory accesses.
+ */
+
+#include "mem/packet.hh"
+#include "mem/request.hh"
+
+namespace RiscvISA
+{
+
+template <class XC>
+inline void
+handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
+{
+}
+
+template <class XC>
+inline void
+handleLockedRead(XC *xc, Request *req)
+{
+}
+
+template <class XC>
+inline void
+handleLockedSnoopHit(XC *xc)
+{
+}
+
+template <class XC>
+inline bool
+handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
+{
+ return true;
+}
+
+} // namespace RiscvISA
+
+#endif // __ARCH_RISCV_LOCKED_MEM_HH__
--- /dev/null
+/*
+ * Copyright (c) 2008 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_RISCV_MICROCODE_ROM_HH__
+#define __ARCH_RISCV_MICROCODE_ROM_HH__
+
+#include "sim/microcode_rom.hh"
+
+namespace RiscvISA
+{
+ using ::MicrocodeRom;
+}
+
+#endif // __ARCH_RISCV_MICROCODE_ROM_HH__
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#ifndef __ARCH_RISCV_MMAPPED_IPR_HH__
+#define __ARCH_RISCV_MMAPPED_IPR_HH__
+
+/**
+ * @file
+ *
+ * ISA-specific helper functions for memory mapped IPR accesses.
+ */
+
+#include "arch/generic/mmapped_ipr.hh"
+
+class ThreadContext;
+
+namespace RiscvISA
+{
+ using GenericISA::handleIprRead;
+ using GenericISA::handleIprWrite;
+} // namespace RiscvISA
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Steve Reinhardt
+ * Jaidev Patwardhan
+ */
+
+#include "arch/riscv/pagetable.hh"
+
+#include "sim/serialize.hh"
+
+namespace RiscvISA
+{
+
+void
+PTE::serialize(CheckpointOut &cp) const
+{
+ SERIALIZE_SCALAR(Mask);
+ SERIALIZE_SCALAR(VPN);
+ SERIALIZE_SCALAR(asid);
+ SERIALIZE_SCALAR(G);
+ SERIALIZE_SCALAR(PFN0);
+ SERIALIZE_SCALAR(D0);
+ SERIALIZE_SCALAR(V0);
+ SERIALIZE_SCALAR(C0);
+ SERIALIZE_SCALAR(PFN1);
+ SERIALIZE_SCALAR(D1);
+ SERIALIZE_SCALAR(V1);
+ SERIALIZE_SCALAR(C1);
+ SERIALIZE_SCALAR(AddrShiftAmount);
+ SERIALIZE_SCALAR(OffsetMask);
+}
+
+void
+PTE::unserialize(CheckpointIn &cp)
+{
+ UNSERIALIZE_SCALAR(Mask);
+ UNSERIALIZE_SCALAR(VPN);
+ UNSERIALIZE_SCALAR(asid);
+ UNSERIALIZE_SCALAR(G);
+ UNSERIALIZE_SCALAR(PFN0);
+ UNSERIALIZE_SCALAR(D0);
+ UNSERIALIZE_SCALAR(V0);
+ UNSERIALIZE_SCALAR(C0);
+ UNSERIALIZE_SCALAR(PFN1);
+ UNSERIALIZE_SCALAR(D1);
+ UNSERIALIZE_SCALAR(V1);
+ UNSERIALIZE_SCALAR(C1);
+ UNSERIALIZE_SCALAR(AddrShiftAmount);
+ UNSERIALIZE_SCALAR(OffsetMask);
+}
+
+}
--- /dev/null
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Steve Reinhardt
+ * Jaidev Patwardhan
+ */
+
+#ifndef __ARCH_RISCV_PAGETABLE_H__
+#define __ARCH_RISCV_PAGETABLE_H__
+
+#include "base/misc.hh"
+#include "base/types.hh"
+#include "sim/serialize.hh"
+
+namespace RiscvISA {
+
+struct VAddr
+{
+};
+
+// ITB/DTB page table entry
+struct PTE
+{
+ Addr Mask;
+ Addr VPN;
+ uint8_t asid;
+
+ bool G;
+
+ /* Contents of Entry Lo0 */
+ Addr PFN0; // Physical Frame Number - Even
+ bool D0; // Even entry Dirty Bit
+ bool V0; // Even entry Valid Bit
+ uint8_t C0; // Cache Coherency Bits - Even
+
+ /* Contents of Entry Lo1 */
+ Addr PFN1; // Physical Frame Number - Odd
+ bool D1; // Odd entry Dirty Bit
+ bool V1; // Odd entry Valid Bit
+ uint8_t C1; // Cache Coherency Bits (3 bits)
+
+ /*
+ * The next few variables are put in as optimizations to reduce
+ * TLB lookup overheads. For a given Mask, what is the address shift
+ * amount, and what is the OffsetMask
+ */
+ int AddrShiftAmount;
+ int OffsetMask;
+
+ bool Valid() { return (V0 | V1); };
+ void serialize(CheckpointOut &cp) const;
+ void unserialize(CheckpointIn &cp);
+};
+
+// WARN: This particular TLB entry is not necessarily conformed to RISC-V ISA
+struct TlbEntry
+{
+ Addr _pageStart;
+ TlbEntry() {}
+ TlbEntry(Addr asn, Addr vaddr, Addr paddr,
+ bool uncacheable, bool read_only)
+ : _pageStart(paddr)
+ {
+ if (uncacheable || read_only)
+ warn("RISC-V TlbEntry does not support uncacheable"
+ " or read-only mappings\n");
+ }
+
+ Addr pageStart()
+ {
+ return _pageStart;
+ }
+
+ void
+ updateVaddr(Addr new_vaddr) {}
+
+ void serialize(CheckpointOut &cp) const
+ {
+ SERIALIZE_SCALAR(_pageStart);
+ }
+
+ void unserialize(CheckpointIn &cp)
+ {
+ UNSERIALIZE_SCALAR(_pageStart);
+ }
+
+};
+
+};
+#endif // __ARCH_RISCV_PAGETABLE_H__
+
--- /dev/null
+/*
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Jaidev Patwardhan
+ */
+
+#ifndef __ARCH_RISCV_PRA_CONSTANTS_HH__
+#define __ARCH_RISCV_PRA_CONSTANTS_HH__
+
+#include "arch/riscv/types.hh"
+#include "base/bitunion.hh"
+
+namespace RiscvISA
+{
+
+BitUnion32(IndexReg)
+ Bitfield<31> p;
+ // Need to figure out how to put in the TLB specific bits here
+ // For now, we assume that the entire length is used by the index
+ // field In reality, Index_HI = N-1, where
+ // N = Ceiling(log2(TLB Entries))
+ Bitfield<30, 0> index;
+EndBitUnion(IndexReg)
+
+BitUnion32(RandomReg)
+ // This has a problem similar to the IndexReg index field. We'll keep
+ // both consistent at 30 for now
+ Bitfield<30, 0> random;
+EndBitUnion(RandomReg)
+
+BitUnion64(EntryLoReg)
+ Bitfield<63, 30> fill;
+ Bitfield<29, 6> pfn; // Page frame number
+ Bitfield<5, 3> c; // Coherency attribute
+ Bitfield<2> d; // Dirty Bit
+ Bitfield<1> v; // Valid Bit
+ Bitfield<0> g; // Global Bit
+EndBitUnion(EntryLoReg)
+
+BitUnion64(ContextReg)
+ Bitfield<63, 23> pteBase;
+ Bitfield<22, 4> badVPN2;
+ // Bits 3-0 are 0
+EndBitUnion(ContextReg)
+
+BitUnion32(PageMaskReg)
+ // Bits 31-29 are 0
+ Bitfield<28, 13> mask;
+ Bitfield<12, 11> maskx;
+ // Bits 10-0 are zero
+EndBitUnion(PageMaskReg)
+
+BitUnion32(PageGrainReg)
+ Bitfield<31, 30> aseUp;
+ Bitfield<29> elpa;
+ Bitfield<28> esp;
+ // Bits 27-13 are zeros
+ Bitfield<12, 8> aseDn;
+ // Bits 7-0 are zeros
+EndBitUnion(PageGrainReg)
+
+BitUnion32(WiredReg)
+ // See note on Index register above
+ Bitfield<30, 0> wired;
+EndBitUnion(WiredReg)
+
+BitUnion32(HWREnaReg)
+ Bitfield<31, 30> impl;
+ Bitfield<3, 0> mask;
+EndBitUnion(HWREnaReg)
+
+BitUnion64(EntryHiReg)
+ Bitfield<63, 62> r;
+ Bitfield<61, 40> fill;
+ Bitfield<39, 13> vpn2;
+ Bitfield<12, 11> vpn2x;
+ Bitfield<7, 0> asid;
+EndBitUnion(EntryHiReg)
+
+BitUnion32(StatusReg)
+ SubBitUnion(cu, 31, 28)
+ Bitfield<31> cu3;
+ Bitfield<30> cu2;
+ Bitfield<29> cu1;
+ Bitfield<28> cu0;
+ EndSubBitUnion(cu)
+ Bitfield<27> rp;
+ Bitfield<26> fr;
+ Bitfield<25> re;
+ Bitfield<24> mx;
+ Bitfield<23> px;
+ Bitfield<22> bev;
+ Bitfield<21> ts;
+ Bitfield<20> sr;
+ Bitfield<19> nmi;
+ // Bit 18 is zero
+ Bitfield<17, 16> impl;
+ Bitfield<15, 10> ipl;
+ SubBitUnion(im, 15, 8)
+ Bitfield<15> im7;
+ Bitfield<14> im6;
+ Bitfield<13> im5;
+ Bitfield<12> im4;
+ Bitfield<11> im3;
+ Bitfield<10> im2;
+ Bitfield<9> im1;
+ Bitfield<8> im0;
+ EndSubBitUnion(im)
+ Bitfield<7> kx;
+ Bitfield<6> sx;
+ Bitfield<5> ux;
+ Bitfield<4, 3> ksu;
+ Bitfield<4> um;
+ Bitfield<3> r0;
+ Bitfield<2> erl;
+ Bitfield<1> exl;
+ Bitfield<0> ie;
+EndBitUnion(StatusReg)
+
+BitUnion32(IntCtlReg)
+ Bitfield<31, 29> ipti;
+ Bitfield<28, 26> ippci;
+ // Bits 26-10 are zeros
+ Bitfield<9, 5> vs;
+ // Bits 4-0 are zeros
+EndBitUnion(IntCtlReg)
+
+BitUnion32(SRSCtlReg)
+ // Bits 31-30 are zeros
+ Bitfield<29, 26> hss;
+ // Bits 25-22 are zeros
+ Bitfield<21, 18> eicss;
+ // Bits 17-16 are zeros
+ Bitfield<15, 12> ess;
+ // Bits 11-10 are zeros
+ Bitfield<9, 6> pss;
+ // Bits 5-4 are zeros
+ Bitfield<3, 0> css;
+EndBitUnion(SRSCtlReg)
+
+BitUnion32(SRSMapReg)
+ Bitfield<31, 28> ssv7;
+ Bitfield<27, 24> ssv6;
+ Bitfield<23, 20> ssv5;
+ Bitfield<19, 16> ssv4;
+ Bitfield<15, 12> ssv3;
+ Bitfield<11, 8> ssv2;
+ Bitfield<7, 4> ssv1;
+ Bitfield<3, 0> ssv0;
+EndBitUnion(SRSMapReg)
+
+BitUnion32(CauseReg)
+ Bitfield<31> bd;
+ Bitfield<30> ti;
+ Bitfield<29, 28> ce;
+ Bitfield<27> dc;
+ Bitfield<26> pci;
+ // Bits 25-24 are zeros
+ Bitfield<23> iv;
+ Bitfield<22> wp;
+ // Bits 21-16 are zeros
+ Bitfield<15, 10> ripl;
+ SubBitUnion(ip, 15, 8)
+ Bitfield<15> ip7;
+ Bitfield<14> ip6;
+ Bitfield<13> ip5;
+ Bitfield<12> ip4;
+ Bitfield<11> ip3;
+ Bitfield<10> ip2;
+ Bitfield<9> ip1;
+ Bitfield<8> ip0;
+ EndSubBitUnion(ip);
+ // Bit 7 is zero
+ Bitfield<6, 2> excCode;
+ // Bits 1-0 are zeros
+EndBitUnion(CauseReg)
+
+BitUnion32(PRIdReg)
+ Bitfield<31, 24> coOp;
+ Bitfield<23, 16> coId;
+ Bitfield<15, 8> procId;
+ Bitfield<7, 0> rev;
+EndBitUnion(PRIdReg)
+
+BitUnion32(EBaseReg)
+ // Bit 31 is one
+ // Bit 30 is zero
+ Bitfield<29, 12> exceptionBase;
+ // Bits 11-10 are zeros
+ Bitfield<9, 9> cpuNum;
+EndBitUnion(EBaseReg)
+
+BitUnion32(ConfigReg)
+ Bitfield<31> m;
+ Bitfield<30, 28> k23;
+ Bitfield<27, 25> ku;
+ Bitfield<24, 16> impl;
+ Bitfield<15> be;
+ Bitfield<14, 13> at;
+ Bitfield<12, 10> ar;
+ Bitfield<9, 7> mt;
+ // Bits 6-4 are zeros
+ Bitfield<3> vi;
+ Bitfield<2, 0> k0;
+EndBitUnion(ConfigReg)
+
+BitUnion32(Config1Reg)
+ Bitfield<31> m;
+ Bitfield<30, 25> mmuSize;
+ Bitfield<24, 22> is;
+ Bitfield<21, 19> il;
+ Bitfield<18, 16> ia;
+ Bitfield<15, 13> ds;
+ Bitfield<12, 10> dl;
+ Bitfield<9, 7> da;
+ Bitfield<6> c2;
+ Bitfield<5> md;
+ Bitfield<4> pc;
+ Bitfield<3> wr;
+ Bitfield<2> ca;
+ Bitfield<1> ep;
+ Bitfield<0> fp;
+EndBitUnion(Config1Reg)
+
+BitUnion32(Config2Reg)
+ Bitfield<31> m;
+ Bitfield<30, 28> tu;
+ Bitfield<27, 24> ts;
+ Bitfield<23, 20> tl;
+ Bitfield<19, 16> ta;
+ Bitfield<15, 12> su;
+ Bitfield<11, 8> ss;
+ Bitfield<7, 4> sl;
+ Bitfield<3, 0> sa;
+EndBitUnion(Config2Reg)
+
+BitUnion32(Config3Reg)
+ Bitfield<31> m;
+ // Bits 30-11 are zeros
+ Bitfield<10> dspp;
+ // Bits 9-8 are zeros
+ Bitfield<7> lpa;
+ Bitfield<6> veic;
+ Bitfield<5> vint;
+ Bitfield<4> sp;
+ // Bit 3 is zero
+ Bitfield<2> mt;
+ Bitfield<1> sm;
+ Bitfield<0> tl;
+EndBitUnion(Config3Reg)
+
+BitUnion64(WatchLoReg)
+ Bitfield<63, 3> vaddr;
+ Bitfield<2> i;
+ Bitfield<1> r;
+ Bitfield<0> w;
+EndBitUnion(WatchLoReg)
+
+BitUnion32(WatchHiReg)
+ Bitfield<31> m;
+ Bitfield<30> g;
+ // Bits 29-24 are zeros
+ Bitfield<23, 16> asid;
+ // Bits 15-12 are zeros
+ Bitfield<11, 3> mask;
+ Bitfield<2> i;
+ Bitfield<1> r;
+ Bitfield<0> w;
+EndBitUnion(WatchHiReg)
+
+BitUnion32(PerfCntCtlReg)
+ Bitfield<31> m;
+ Bitfield<30> w;
+ // Bits 29-11 are zeros
+ Bitfield<10, 5> event;
+ Bitfield<4> ie;
+ Bitfield<3> u;
+ Bitfield<2> s;
+ Bitfield<1> k;
+ Bitfield<0> exl;
+EndBitUnion(PerfCntCtlReg)
+
+BitUnion32(CacheErrReg)
+ Bitfield<31> er;
+ Bitfield<30> ec;
+ Bitfield<29> ed;
+ Bitfield<28> et;
+ Bitfield<27> es;
+ Bitfield<26> ee;
+ Bitfield<25> eb;
+ Bitfield<24, 22> impl;
+ Bitfield<22, 0> index;
+EndBitUnion(CacheErrReg)
+
+BitUnion32(TagLoReg)
+ Bitfield<31, 8> pTagLo;
+ Bitfield<7, 6> pState;
+ Bitfield<5> l;
+ Bitfield<4, 3> impl;
+ // Bits 2-1 are zeros
+ Bitfield<0> p;
+EndBitUnion(TagLoReg)
+
+} // namespace RiscvISA
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2016 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ * Ali Saidi
+ * Korey Sewell
+ * Alec Roelke
+ */
+#include "arch/riscv/process.hh"
+
+#include <vector>
+
+#include "arch/riscv/isa_traits.hh"
+#include "base/loader/elf_object.hh"
+#include "base/loader/object_file.hh"
+#include "base/misc.hh"
+#include "cpu/thread_context.hh"
+#include "debug/Loader.hh"
+#include "mem/page_table.hh"
+#include "sim/process.hh"
+#include "sim/process_impl.hh"
+#include "sim/system.hh"
+
+using namespace std;
+using namespace RiscvISA;
+
+RiscvLiveProcess::RiscvLiveProcess(LiveProcessParams * params,
+ ObjectFile *objFile) : LiveProcess(params, objFile)
+{
+ // Set up stack. On RISC-V, stack starts at the top of kuseg
+ // user address space. RISC-V stack grows down from here
+ stack_base = 0x7FFFFFFF;
+
+ // Set pointer for next thread stack. Reserve 8M for main stack.
+ next_thread_stack_base = stack_base - (8 * 1024 * 1024);
+
+ // Set up break point (Top of Heap)
+ brk_point = objFile->bssBase() + objFile->bssSize();
+
+ // Set up region for mmaps. Start it 1GB above the top of the heap.
+ mmap_end = brk_point + 0x40000000L;
+}
+
+void
+RiscvLiveProcess::initState()
+{
+ LiveProcess::initState();
+
+ argsInit<uint64_t>(PageBytes);
+}
+
+template<class IntType> void
+RiscvLiveProcess::argsInit(int pageSize)
+{
+ updateBias();
+
+ // load object file into target memory
+ objFile->loadSections(initVirtMem);
+
+ typedef AuxVector<IntType> auxv_t;
+ vector<auxv_t> auxv;
+ ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
+ if (elfObject) {
+ // Set the system page size
+ auxv.push_back(auxv_t(M5_AT_PAGESZ, RiscvISA::PageBytes));
+ // Set the frequency at which time() increments
+ auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
+ // For statically linked executables, this is the virtual
+ // address of the program header tables if they appear in the
+ // executable image.
+ auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
+ DPRINTF(Loader, "auxv at PHDR %08p\n",
+ elfObject->programHeaderTable());
+ // This is the size of a program header entry from the elf file.
+ auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
+ // This is the number of program headers from the original elf file.
+ auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
+ auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
+ //The entry point to the program
+ auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
+ //Different user and group IDs
+ auxv.push_back(auxv_t(M5_AT_UID, uid()));
+ auxv.push_back(auxv_t(M5_AT_EUID, euid()));
+ auxv.push_back(auxv_t(M5_AT_GID, gid()));
+ auxv.push_back(auxv_t(M5_AT_EGID, egid()));
+ }
+
+ const IntType zero = 0;
+ IntType argc = htog((IntType)argv.size());
+ int argv_array_size = sizeof(Addr) * argv.size();
+ int arg_data_size = 0;
+ for (string arg: argv)
+ arg_data_size += arg.size() + 1;
+ int envp_array_size = sizeof(Addr) * envp.size();
+ int env_data_size = 0;
+ for (string env: envp)
+ env_data_size += env.size() + 1;
+ int auxv_array_size = 2 * sizeof(IntType)*auxv.size();
+
+ stack_size = sizeof(IntType) + argv_array_size + 2 * sizeof(Addr) +
+ arg_data_size + 2 * sizeof(Addr);
+ if (!envp.empty()) {
+ stack_size += 2 * sizeof(Addr) + envp_array_size + 2 * sizeof(Addr) +
+ env_data_size;
+ }
+ if (!auxv.empty())
+ stack_size += 2 * sizeof(Addr) + auxv_array_size;
+ stack_min = roundDown(stack_base - stack_size, pageSize);
+ allocateMem(stack_min, roundUp(stack_size, pageSize));
+
+ Addr argv_array_base = stack_min + sizeof(IntType);
+ Addr arg_data_base = argv_array_base + argv_array_size + 2 * sizeof(Addr);
+ Addr envp_array_base = arg_data_base + arg_data_size;
+ if (!envp.empty())
+ envp_array_base += 2 * sizeof(Addr);
+ Addr env_data_base = envp_array_base + envp_array_size;
+ if (!envp.empty())
+ env_data_base += 2 * sizeof(Addr);
+
+ vector<Addr> arg_pointers;
+ if (!argv.empty()) {
+ arg_pointers.push_back(arg_data_base);
+ for (int i = 0; i < argv.size() - 1; i++) {
+ arg_pointers.push_back(arg_pointers[i] + argv[i].size() + 1);
+ }
+ }
+
+ vector<Addr> env_pointers;
+ if (!envp.empty()) {
+ env_pointers.push_back(env_data_base);
+ for (int i = 0; i < envp.size() - 1; i++) {
+ env_pointers.push_back(env_pointers[i] + envp[i].size() + 1);
+ }
+ }
+
+ Addr sp = stack_min;
+ initVirtMem.writeBlob(sp, (uint8_t *)&argc, sizeof(IntType));
+ sp += sizeof(IntType);
+ for (Addr arg_pointer: arg_pointers) {
+ initVirtMem.writeBlob(sp, (uint8_t *)&arg_pointer, sizeof(Addr));
+ sp += sizeof(Addr);
+ }
+ for (int i = 0; i < 2; i++) {
+ initVirtMem.writeBlob(sp, (uint8_t *)&zero, sizeof(Addr));
+ sp += sizeof(Addr);
+ }
+ for (int i = 0; i < argv.size(); i++) {
+ initVirtMem.writeString(sp, argv[i].c_str());
+ sp += argv[i].size() + 1;
+ }
+ if (!envp.empty()) {
+ for (int i = 0; i < 2; i++) {
+ initVirtMem.writeBlob(sp, (uint8_t *)&zero, sizeof(Addr));
+ sp += sizeof(Addr);
+ }
+ }
+ for (Addr env_pointer: env_pointers)
+ initVirtMem.writeBlob(sp, (uint8_t *)&env_pointer, sizeof(Addr));
+ if (!envp.empty()) {
+ for (int i = 0; i < 2; i++) {
+ initVirtMem.writeBlob(sp, (uint8_t *)&zero, sizeof(Addr));
+ sp += sizeof(Addr);
+ }
+ }
+ for (int i = 0; i < envp.size(); i++) {
+ initVirtMem.writeString(sp, envp[i].c_str());
+ sp += envp[i].size() + 1;
+ }
+ if (!auxv.empty()) {
+ for (int i = 0; i < 2; i++) {
+ initVirtMem.writeBlob(sp, (uint8_t *)&zero, sizeof(Addr));
+ sp += sizeof(Addr);
+ }
+ }
+ for (auxv_t aux: auxv) {
+ initVirtMem.writeBlob(sp, (uint8_t *)&aux.a_type, sizeof(IntType));
+ initVirtMem.writeBlob(sp + sizeof(IntType), (uint8_t *)&aux.a_val,
+ sizeof(IntType));
+ sp += 2 * sizeof(IntType);
+ }
+ for (int i = 0; i < 2; i++) {
+ initVirtMem.writeBlob(sp, (uint8_t *)&zero, sizeof(Addr));
+ sp += sizeof(Addr);
+ }
+
+ ThreadContext *tc = system->getThreadContext(contextIds[0]);
+ tc->setIntReg(StackPointerReg, stack_min);
+ tc->pcState(getStartPC());
+}
+
+RiscvISA::IntReg
+RiscvLiveProcess::getSyscallArg(ThreadContext *tc, int &i)
+{
+ return tc->readIntReg(SyscallArgumentRegs[i++]);
+}
+
+void
+RiscvLiveProcess::setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val)
+{
+ tc->setIntReg(SyscallArgumentRegs[i], val);
+}
+
+void
+RiscvLiveProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
+{
+ if (sysret.successful()) {
+ // no error
+ tc->setIntReg(SyscallPseudoReturnReg, sysret.returnValue());
+ } else {
+ // got an error, return details
+ tc->setIntReg(SyscallPseudoReturnReg, sysret.errnoValue());
+ }
+}
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ * Ali Saidi
+ */
+
+#ifndef __RISCV_PROCESS_HH__
+#define __RISCV_PROCESS_HH__
+
+#include <string>
+#include <vector>
+
+#include "sim/process.hh"
+
+class LiveProcess;
+class ObjectFile;
+class System;
+
+class RiscvLiveProcess : public LiveProcess
+{
+ protected:
+ RiscvLiveProcess(LiveProcessParams * params, ObjectFile *objFile);
+
+ void initState();
+
+ template<class IntType>
+ void argsInit(int pageSize);
+
+ public:
+ RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
+ /// Explicitly import the otherwise hidden getSyscallArg
+ using LiveProcess::getSyscallArg;
+ void setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val);
+ void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
+};
+
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
+
+#endif // __RISCV_PROCESS_HH__
--- /dev/null
+/*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alexandru Dutu
+ */
+
+#ifndef __ARCH_RISCV_PSEUDO_INST_HH__
+#define __ARCH_RISCV_PSEUDO_INST_HH__
+
+#include "arch/generic/pseudo_inst.hh"
+#include "base/misc.hh"
+
+class ThreadContext;
+
+namespace RiscvISA {
+ using GenericISA::m5Syscall;
+ using GenericISA::m5PageFault;
+}
+
+#endif // __ARCH_RISCV_PSEUDO_INST_HH__
+
--- /dev/null
+/*
+ * Copyright (c) 2013 ARM Limited
+ * Copyright (c) 2014-2015 Sven Karlsson
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2016 RISC-V Foundation
+ * Copyright (c) 2016 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Hansson
+ * Sven Karlsson
+ * Alec Roelke
+ */
+
+#ifndef __ARCH_RISCV_REGISTERS_HH__
+#define __ARCH_RISCV_REGISTERS_HH__
+
+#include <map>
+#include <string>
+
+#include "arch/riscv/generated/max_inst_regs.hh"
+#include "base/types.hh"
+#include "sim/system.hh"
+
+namespace RiscvISA {
+
+using RiscvISAInst::MaxInstSrcRegs;
+using RiscvISAInst::MaxInstDestRegs;
+const int MaxMiscDestRegs = 1;
+
+typedef uint_fast16_t RegIndex;
+typedef uint64_t IntReg;
+typedef uint64_t FloatRegBits;
+typedef double FloatReg;
+typedef uint8_t CCReg; // Not applicable to Riscv
+typedef uint64_t MiscReg;
+
+const int NumIntArchRegs = 32;
+const int NumIntRegs = NumIntArchRegs;
+const int NumFloatRegs = 0;
+const int NumCCRegs = 0;
+const int NumMiscRegs = 4096;
+
+// These help enumerate all the registers for dependence tracking.
+const int FP_Reg_Base = NumIntRegs;
+const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
+const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs;
+const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
+
+
+// Semantically meaningful register indices
+const int ZeroReg = 0;
+const int ReturnAddrReg = 1;
+const int StackPointerReg = 2;
+const int GlobalPointerReg = 3;
+const int ThreadPointerReg = 4;
+const int FramePointerReg = 8;
+const int ReturnValueRegs[] = {10, 11};
+const int ReturnValueReg = ReturnValueRegs[0];
+const int ArgumentRegs[] = {10, 11, 12, 13, 14, 15, 16, 17};
+
+const char* const RegisterNames[] = {"zero", "ra", "sp", "gp",
+ "tp", "t0", "t1", "t2",
+ "s0", "s1", "a0", "a1",
+ "a2", "a3", "a4", "a5",
+ "a6", "a7", "s2", "s3",
+ "s4", "s5", "s6", "s7",
+ "s8", "s9", "s10", "s11",
+ "t3", "t4", "t5", "t6"};
+
+const int SyscallNumReg = ArgumentRegs[7];
+const int SyscallArgumentRegs[] = {ArgumentRegs[0], ArgumentRegs[1],
+ ArgumentRegs[2], ArgumentRegs[3]};
+const int SyscallPseudoReturnReg = ReturnValueRegs[0];
+
+enum MiscRegIndex {
+ MISCREG_FFLAGS = 0x001,
+ MISCREG_FRM = 0x002,
+ MISCREG_FCSR = 0x003,
+ MISCREG_CYCLE = 0xC00,
+ MISCREG_TIME = 0xC01,
+ MISCREG_INSTRET = 0xC02,
+ MISCREG_CYCLEH = 0xC80,
+ MISCREG_TIMEH = 0xC81,
+ MISCREG_INSTRETH = 0xC82,
+
+ MISCREG_SSTATUS = 0x100,
+ MISCREG_STVEC = 0x101,
+ MISCREG_SIE = 0x104,
+ MISCREG_STIMECMP = 0x121,
+ MISCREG_STIME = 0xD01,
+ MISCREG_STIMEH = 0xD81,
+ MISCREG_SSCRATCH = 0x140,
+ MISCREG_SEPC = 0x141,
+ MISCREG_SCAUSE = 0xD42,
+ MISCREG_SBADADDR = 0xD43,
+ MISCREG_SIP = 0x144,
+ MISCREG_SPTBR = 0x180,
+ MISCREG_SASID = 0x181,
+ MISCREG_CYCLEW = 0x900,
+ MISCREG_TIMEW = 0x901,
+ MISCREG_INSTRETW = 0x902,
+ MISCREG_CYCLEHW = 0x980,
+ MISCREG_TIMEHW = 0x981,
+ MISCREG_INSTRETHW = 0x982,
+
+ MISCREG_HSTATUS = 0x200,
+ MISCREG_HTVEC = 0x201,
+ MISCREG_HTDELEG = 0x202,
+ MISCREG_HTIMECMP = 0x221,
+ MISCREG_HTIME = 0xE01,
+ MISCREG_HTIMEH = 0xE81,
+ MISCREG_HSCRATCH = 0x240,
+ MISCREG_HEPC = 0x241,
+ MISCREG_HCAUSE = 0x242,
+ MISCREG_HBADADDR = 0x243,
+ MISCREG_STIMEW = 0xA01,
+ MISCREG_STIMEHW = 0xA81,
+
+ MISCREG_MCPUID = 0xF00,
+ MISCREG_MIMPID = 0xF01,
+ MISCREG_MHARTID = 0xF10,
+ MISCREG_MSTATUS = 0x300,
+ MISCREG_MTVEC = 0x301,
+ MISCREG_MTDELEG = 0x302,
+ MISCREG_MIE = 0x304,
+ MISCREG_MTIMECMP = 0x321,
+ MISCREG_MTIME = 0x701,
+ MISCREG_MTIMEH = 0x741,
+ MISCREG_MSCRATCH = 0x340,
+ MISCREG_MEPC = 0x341,
+ MISCREG_MCAUSE = 0x342,
+ MISCREG_MBADADDR = 0x343,
+ MISCREG_MIP = 0x344,
+ MISCREG_MBASE = 0x380,
+ MISCREG_MBOUND = 0x381,
+ MISCREG_MIBASE = 0x382,
+ MISCREG_MIBOUND = 0x383,
+ MISCREG_MDBASE = 0x384,
+ MISCREG_MDBOUND = 0x385,
+ MISCREG_HTIMEW = 0xB01,
+ MISCREG_HTIMEHW = 0xB81,
+ MISCREG_MTOHOST = 0x780,
+ MISCREG_MFROMHOST = 0x781
+};
+
+}
+
+#endif // __ARCH_RISCV_REGISTERS_HH__
--- /dev/null
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007-2008 The Florida State University
+ * Copyright (c) 2009 The University of Edinburgh
+ * Copyright (c) 2015 Sven Karlsson
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Stephen Hines
+ * Timothy M. Jones
+ * Sven Karlsson
+ */
+
+ #include "base/remote_gdb.hh"
+ #include "arch/riscv/remote_gdb.hh"
+ #include "sim/system.hh"
+
+using namespace std;
+using namespace RiscvISA;
+
+RemoteGDB::RemoteGDB(System *system, ThreadContext *context)
+ : BaseRemoteGDB(system, context)
+{
+}
+
+RemoteGDB::BaseGdbRegCache*
+RemoteGDB::gdbRegs()
+{
+ panic("gdbRegs not implemented for Riscv!");
+}
+
+bool
+RemoteGDB::acc(Addr, size_t)
+{
+ panic("acc not implemented for Riscv!");
+}
+
+void
+RemoteGDB::getregs()
+{
+ panic("getregs not implemented for Riscv!");
+}
+
+void
+RemoteGDB::setregs()
+{
+ panic("setregs not implemented for Riscv!");
+}
--- /dev/null
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007-2008 The Florida State University
+ * Copyright (c) 2009 The University of Edinburgh
+ * Copyright (c) 2015 Sven Karlsson
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Stephen Hines
+ * Timothy M. Jones
+ * Sven Karlsson
+ */
+
+#ifndef __ARCH_RISCV_REMOTE_GDB_HH__
+#define __ARCH_RISCV_REMOTE_GDB_HH__
+
+#include "base/remote_gdb.hh"
+
+class System;
+class ThreadContext;
+
+namespace RiscvISA
+{
+
+class RemoteGDB : public BaseRemoteGDB
+{
+ public:
+ RemoteGDB(System *system, ThreadContext *context);
+
+ BaseGdbRegCache *
+ gdbRegs();
+
+ bool
+ acc(Addr, size_t);
+
+ void
+ getregs();
+
+ void
+ setregs();
+};
+
+} // namespace RiscvISA
+
+#endif /* __ARCH_RISCV_REMOTE_GDB_H__ */
--- /dev/null
+/*
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+#include "arch/riscv/stacktrace.hh"
+
+#include <string>
+
+#include "base/trace.hh"
+
+using namespace std;
+
+namespace RiscvISA {
+
+ProcessInfo::ProcessInfo(ThreadContext *_tc)
+{
+ panic("ProcessInfo constructor not implemented.\n");
+}
+
+Addr
+ProcessInfo::task(Addr ksp) const
+{
+ panic("ProcessInfo::task not implemented.\n");
+ return 0;
+}
+
+int
+ProcessInfo::pid(Addr ksp) const
+{
+ panic("ProcessInfo::pid not implemented.\n");
+ return 0;
+}
+
+string
+ProcessInfo::name(Addr ksp) const
+{
+ panic("ProcessInfo::name not implemented.\n");
+ return "";
+}
+
+StackTrace::StackTrace()
+ : tc(0), stack(64)
+{
+ panic("StackTrace constructor not implemented.\n");
+}
+
+StackTrace::StackTrace(ThreadContext *_tc, const StaticInstPtr &inst)
+ : tc(0), stack(64)
+{
+ panic("StackTrace constructor not implemented.\n");
+}
+
+StackTrace::~StackTrace()
+{
+ panic("StackTrace destructor not implemented.\n");
+}
+
+void
+StackTrace::trace(ThreadContext *_tc, bool is_call)
+{
+ panic("StackTrace::trace not implemented.\n");
+}
+
+bool
+StackTrace::isEntry(Addr addr)
+{
+ panic("StackTrace::isEntry not implemented.\n");
+ return false;
+}
+
+bool
+StackTrace::decodeStack(MachInst inst, int &disp)
+{
+ panic("StackTrace::decodeStack not implemented.\n");
+ return false;
+}
+
+bool
+StackTrace::decodeSave(MachInst inst, int ®, int &disp)
+{
+ panic("StackTrace::decodeSave not implemented.\n");
+ return true;
+}
+
+/*
+ * Decode the function prologue for the function we're in, and note
+ * which registers are stored where, and how large the stack frame is.
+ */
+bool
+StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func, int &size,
+ Addr &ra)
+{
+ panic("StackTrace::decodePrologue not implemented.\n");
+ return true;
+}
+
+#if TRACING_ON
+void
+StackTrace::dump()
+{
+ panic("StackTrace::dump not implemented.\n");
+}
+#endif
+
+} // namespace RiscvISA
--- /dev/null
+/*
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * Copyright (c) 2007-2008 The Florida State University
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ * Stephen Hines
+ * Timothy M. Jones
+ */
+
+#ifndef __ARCH_RISCV_STACKTRACE_HH__
+#define __ARCH_RISCV_STACKTRACE_HH__
+
+#include "base/trace.hh"
+#include "cpu/static_inst.hh"
+#include "debug/Stack.hh"
+
+class ThreadContext;
+class StackTrace;
+
+namespace RiscvISA
+{
+
+class ProcessInfo
+{
+ public:
+ ProcessInfo(ThreadContext *_tc);
+
+ Addr task(Addr ksp) const;
+ int pid(Addr ksp) const;
+ std::string name(Addr ksp) const;
+};
+
+class StackTrace
+{
+ protected:
+ typedef TheISA::MachInst MachInst;
+ private:
+ ThreadContext *tc;
+ std::vector<Addr> stack;
+
+ private:
+ bool isEntry(Addr addr);
+ bool decodePrologue(Addr sp, Addr callpc, Addr func, int &size, Addr &ra);
+ bool decodeSave(MachInst inst, int ®, int &disp);
+ bool decodeStack(MachInst inst, int &disp);
+
+ void trace(ThreadContext *tc, bool is_call);
+
+ public:
+ StackTrace();
+ StackTrace(ThreadContext *tc, const StaticInstPtr &inst);
+ ~StackTrace();
+
+ void
+ clear()
+ {
+ tc = 0;
+ stack.clear();
+ }
+
+ bool
+ valid() const
+ {
+ return tc != nullptr;
+ }
+
+ bool trace(ThreadContext *tc, const StaticInstPtr &inst);
+
+ public:
+ const std::vector<Addr> &
+ getstack() const
+ {
+ return stack;
+ }
+
+ static const int user = 1;
+ static const int console = 2;
+ static const int unknown = 3;
+
+#if TRACING_ON
+ private:
+ void dump();
+
+ public:
+ void
+ dprintf()
+ {
+ if (DTRACE(Stack))
+ dump();
+ }
+#else
+ public:
+ void
+ dprintf()
+ {
+ }
+#endif
+};
+
+inline bool
+StackTrace::trace(ThreadContext *tc, const StaticInstPtr &inst)
+{
+ if (!inst->isCall() && !inst->isReturn())
+ return false;
+
+ if (valid())
+ clear();
+
+ trace(tc, !inst->isReturn());
+ return true;
+}
+
+} // namespace RiscvISA
+
+#endif // __ARCH_RISCV_STACKTRACE_HH__
--- /dev/null
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ * Nathan Binkert
+ * Jaidev Patwardhan
+ */
+
+#include "arch/riscv/system.hh"
+
+#include "arch/vtophys.hh"
+#include "base/loader/hex_file.hh"
+#include "base/loader/object_file.hh"
+#include "base/loader/symtab.hh"
+#include "base/trace.hh"
+#include "mem/physical.hh"
+#include "params/RiscvSystem.hh"
+#include "sim/byteswap.hh"
+
+using namespace LittleEndianGuest;
+
+RiscvSystem::RiscvSystem(Params *p) : System(p)
+{
+}
+
+RiscvSystem::~RiscvSystem()
+{
+}
+
+Addr
+RiscvSystem::fixFuncEventAddr(Addr addr)
+{
+ return addr;
+}
+
+void
+RiscvSystem::setRiscvAccess(Addr access)
+{}
+
+bool
+RiscvSystem::breakpoint()
+{
+ return 0;
+}
+
+RiscvSystem *
+RiscvSystemParams::create()
+{
+ return new RiscvSystem(this);
+}
+
--- /dev/null
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ * Nathan Binkert
+ * Jaidev Patwardhan
+ */
+
+#ifndef __ARCH_RISCV_SYSTEM_HH__
+#define __ARCH_RISCV_SYSTEM_HH__
+
+#include <string>
+#include <vector>
+
+#include "base/loader/hex_file.hh"
+#include "base/loader/symtab.hh"
+#include "cpu/pc_event.hh"
+#include "kern/system_events.hh"
+#include "params/RiscvSystem.hh"
+#include "sim/sim_object.hh"
+#include "sim/system.hh"
+
+class RiscvSystem : public System
+{
+ public:
+ typedef RiscvSystemParams Params;
+ RiscvSystem(Params *p);
+ ~RiscvSystem();
+
+ virtual bool breakpoint();
+
+ public:
+
+ /**
+ * Set the m5RiscvAccess pointer in the console
+ */
+ void setRiscvAccess(Addr access);
+
+ /** console symbol table */
+ SymbolTable *consoleSymtab;
+
+ /** Object pointer for the console code */
+ ObjectFile *console;
+
+ /** Used by some Bare Iron Configurations */
+ HexFile *hexFile;
+
+#ifndef NDEBUG
+ /** Event to halt the simulator if the console calls panic() */
+ BreakPCEvent *consolePanicEvent;
+#endif
+
+ protected:
+ const Params *params() const { return (const Params *)_params; }
+
+ /** Add a function-based event to the console code. */
+ template <class T>
+ T *
+ addConsoleFuncEvent(const char *lbl)
+ {
+ return addFuncEvent<T>(consoleSymtab, lbl);
+ }
+
+ virtual Addr fixFuncEventAddr(Addr addr);
+
+};
+
+#endif
+
--- /dev/null
+/*
+ * Copyright (c) 2001-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Steve Reinhardt
+ * Jaidev Patwardhan
+ * Zhengxing Li
+ * Deyuan Guo
+ */
+
+#include "arch/riscv/tlb.hh"
+
+#include <string>
+#include <vector>
+
+#include "arch/riscv/faults.hh"
+#include "arch/riscv/pagetable.hh"
+#include "arch/riscv/pra_constants.hh"
+#include "arch/riscv/utility.hh"
+#include "base/inifile.hh"
+#include "base/str.hh"
+#include "base/trace.hh"
+#include "cpu/thread_context.hh"
+#include "debug/RiscvTLB.hh"
+#include "debug/TLB.hh"
+#include "mem/page_table.hh"
+#include "params/RiscvTLB.hh"
+#include "sim/full_system.hh"
+#include "sim/process.hh"
+
+using namespace std;
+using namespace RiscvISA;
+
+///////////////////////////////////////////////////////////////////////
+//
+// RISC-V TLB
+//
+
+TLB::TLB(const Params *p)
+ : BaseTLB(p), size(p->size), nlu(0)
+{
+ table = new PTE[size];
+ memset(table, 0, sizeof(PTE[size]));
+ smallPages = 0;
+}
+
+TLB::~TLB()
+{
+ if (table)
+ delete [] table;
+}
+
+// look up an entry in the TLB
+RiscvISA::PTE *
+TLB::lookup(Addr vpn, uint8_t asn) const
+{
+ // assume not found...
+ PTE *retval = nullptr;
+ PageTable::const_iterator i = lookupTable.find(vpn);
+ if (i != lookupTable.end()) {
+ while (i->first == vpn) {
+ int index = i->second;
+ PTE *pte = &table[index];
+
+ /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
+ Addr Mask = pte->Mask;
+ Addr InvMask = ~Mask;
+ Addr VPN = pte->VPN;
+ if (((vpn & InvMask) == (VPN & InvMask)) &&
+ (pte->G || (asn == pte->asid))) {
+ // We have a VPN + ASID Match
+ retval = pte;
+ break;
+ }
+ ++i;
+ }
+ }
+
+ DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
+ retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
+ return retval;
+}
+
+RiscvISA::PTE*
+TLB::getEntry(unsigned Index) const
+{
+ // Make sure that Index is valid
+ assert(Index<size);
+ return &table[Index];
+}
+
+int
+TLB::probeEntry(Addr vpn, uint8_t asn) const
+{
+ // assume not found...
+ int Ind = -1;
+ PageTable::const_iterator i = lookupTable.find(vpn);
+ if (i != lookupTable.end()) {
+ while (i->first == vpn) {
+ int index = i->second;
+ PTE *pte = &table[index];
+
+ /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
+ Addr Mask = pte->Mask;
+ Addr InvMask = ~Mask;
+ Addr VPN = pte->VPN;
+ if (((vpn & InvMask) == (VPN & InvMask)) &&
+ (pte->G || (asn == pte->asid))) {
+ // We have a VPN + ASID Match
+ Ind = index;
+ break;
+ }
+ ++i;
+ }
+ }
+ DPRINTF(RiscvTLB,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind);
+ return Ind;
+}
+
+inline Fault
+TLB::checkCacheability(RequestPtr &req)
+{
+ Addr VAddrUncacheable = 0xA0000000;
+ // In MIPS, cacheability is controlled by certain bits of the virtual
+ // address or by the TLB entry
+ if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
+ // mark request as uncacheable
+ req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
+ }
+ return NoFault;
+}
+
+void
+TLB::insertAt(PTE &pte, unsigned Index, int _smallPages)
+{
+ smallPages = _smallPages;
+ if (Index > size) {
+ warn("Attempted to write at index (%d) beyond TLB size (%d)",
+ Index, size);
+ } else {
+ // Update TLB
+ DPRINTF(TLB, "TLB[%d]: %x %x %x %x\n",
+ Index, pte.Mask << 11,
+ ((pte.VPN << 11) | pte.asid),
+ ((pte.PFN0 << 6) | (pte.C0 << 3) |
+ (pte.D0 << 2) | (pte.V0 <<1) | pte.G),
+ ((pte.PFN1 <<6) | (pte.C1 << 3) |
+ (pte.D1 << 2) | (pte.V1 <<1) | pte.G));
+ if (table[Index].V0 || table[Index].V1) {
+ // Previous entry is valid
+ PageTable::iterator i = lookupTable.find(table[Index].VPN);
+ lookupTable.erase(i);
+ }
+ table[Index]=pte;
+ // Update fast lookup table
+ lookupTable.insert(make_pair(table[Index].VPN, Index));
+ }
+}
+
+// insert a new TLB entry
+void
+TLB::insert(Addr addr, PTE &pte)
+{
+ fatal("TLB Insert not yet implemented\n");
+}
+
+void
+TLB::flushAll()
+{
+ DPRINTF(TLB, "flushAll\n");
+ memset(table, 0, sizeof(PTE[size]));
+ lookupTable.clear();
+ nlu = 0;
+}
+
+void
+TLB::serialize(CheckpointOut &cp) const
+{
+ SERIALIZE_SCALAR(size);
+ SERIALIZE_SCALAR(nlu);
+
+ for (int i = 0; i < size; i++) {
+ ScopedCheckpointSection sec(cp, csprintf("PTE%d", i));
+ table[i].serialize(cp);
+ }
+}
+
+void
+TLB::unserialize(CheckpointIn &cp)
+{
+ UNSERIALIZE_SCALAR(size);
+ UNSERIALIZE_SCALAR(nlu);
+
+ for (int i = 0; i < size; i++) {
+ ScopedCheckpointSection sec(cp, csprintf("PTE%d", i));
+ table[i].unserialize(cp);
+ if (table[i].V0 || table[i].V1) {
+ lookupTable.insert(make_pair(table[i].VPN, i));
+ }
+ }
+}
+
+void
+TLB::regStats()
+{
+ BaseTLB::regStats();
+
+ read_hits
+ .name(name() + ".read_hits")
+ .desc("DTB read hits")
+ ;
+
+ read_misses
+ .name(name() + ".read_misses")
+ .desc("DTB read misses")
+ ;
+
+
+ read_accesses
+ .name(name() + ".read_accesses")
+ .desc("DTB read accesses")
+ ;
+
+ write_hits
+ .name(name() + ".write_hits")
+ .desc("DTB write hits")
+ ;
+
+ write_misses
+ .name(name() + ".write_misses")
+ .desc("DTB write misses")
+ ;
+
+
+ write_accesses
+ .name(name() + ".write_accesses")
+ .desc("DTB write accesses")
+ ;
+
+ hits
+ .name(name() + ".hits")
+ .desc("DTB hits")
+ ;
+
+ misses
+ .name(name() + ".misses")
+ .desc("DTB misses")
+ ;
+
+ accesses
+ .name(name() + ".accesses")
+ .desc("DTB accesses")
+ ;
+
+ hits = read_hits + write_hits;
+ misses = read_misses + write_misses;
+ accesses = read_accesses + write_accesses;
+}
+
+Fault
+TLB::translateInst(RequestPtr req, ThreadContext *tc)
+{
+ if (FullSystem)
+ panic("translateInst not implemented in RISC-V.\n");
+
+ Process * p = tc->getProcessPtr();
+
+ Fault fault = p->pTable->translate(req);
+ if (fault != NoFault)
+ return fault;
+
+ return NoFault;
+}
+
+Fault
+TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
+{
+ if (FullSystem)
+ panic("translateData not implemented in RISC-V.\n");
+
+ Process * p = tc->getProcessPtr();
+
+ Fault fault = p->pTable->translate(req);
+ if (fault != NoFault)
+ return fault;
+
+ return NoFault;
+}
+
+Fault
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
+{
+ if (mode == Execute)
+ return translateInst(req, tc);
+ else
+ return translateData(req, tc, mode == Write);
+}
+
+void
+TLB::translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation, Mode mode)
+{
+ assert(translation);
+ translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
+}
+
+Fault
+TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
+{
+ panic("Not implemented\n");
+ return NoFault;
+}
+
+Fault
+TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+{
+ return NoFault;
+}
+
+
+RiscvISA::PTE &
+TLB::index(bool advance)
+{
+ PTE *pte = &table[nlu];
+
+ if (advance)
+ nextnlu();
+
+ return *pte;
+}
+
+RiscvISA::TLB *
+RiscvTLBParams::create()
+{
+ return new TLB(this);
+}
--- /dev/null
+/*
+ * Copyright (c) 2001-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Steve Reinhardt
+ * Jaidev Patwardhan
+ * Korey Sewell
+ */
+
+#ifndef __ARCH_RISCV_TLB_HH__
+#define __ARCH_RISCV_TLB_HH__
+
+#include <map>
+
+#include "arch/generic/tlb.hh"
+#include "arch/riscv/isa_traits.hh"
+#include "arch/riscv/pagetable.hh"
+#include "arch/riscv/utility.hh"
+#include "arch/riscv/vtophys.hh"
+#include "base/statistics.hh"
+#include "mem/request.hh"
+#include "params/RiscvTLB.hh"
+#include "sim/sim_object.hh"
+
+class ThreadContext;
+
+/* To maintain compatibility with other architectures, we'll
+ simply create an ITLB and DTLB that will point to the real TLB */
+namespace RiscvISA {
+
+class TLB : public BaseTLB
+{
+ protected:
+ typedef std::multimap<Addr, int> PageTable;
+ PageTable lookupTable; // Quick lookup into page table
+
+ RiscvISA::PTE *table; // the Page Table
+ int size; // TLB Size
+ int nlu; // not last used entry (for replacement)
+
+ void nextnlu() { if (++nlu >= size) nlu = 0; }
+ RiscvISA::PTE *lookup(Addr vpn, uint8_t asn) const;
+
+ mutable Stats::Scalar read_hits;
+ mutable Stats::Scalar read_misses;
+ mutable Stats::Scalar read_acv;
+ mutable Stats::Scalar read_accesses;
+ mutable Stats::Scalar write_hits;
+ mutable Stats::Scalar write_misses;
+ mutable Stats::Scalar write_acv;
+ mutable Stats::Scalar write_accesses;
+ Stats::Formula hits;
+ Stats::Formula misses;
+ Stats::Formula accesses;
+
+ public:
+ typedef RiscvTLBParams Params;
+ TLB(const Params *p);
+
+ int probeEntry(Addr vpn,uint8_t) const;
+ RiscvISA::PTE *getEntry(unsigned) const;
+ virtual ~TLB();
+
+ void takeOverFrom(BaseTLB *otlb) override {}
+
+ int smallPages;
+ int getsize() const { return size; }
+
+ RiscvISA::PTE &index(bool advance = true);
+ void insert(Addr vaddr, RiscvISA::PTE &pte);
+ void insertAt(RiscvISA::PTE &pte, unsigned Index, int _smallPages);
+ void flushAll() override;
+ void demapPage(Addr vaddr, uint64_t asn) override
+ {
+ panic("demapPage unimplemented.\n");
+ }
+
+ // static helper functions... really
+ static bool validVirtualAddress(Addr vaddr);
+
+ static Fault checkCacheability(RequestPtr &req);
+
+ // Checkpointing
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
+
+ void regStats() override;
+
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
+ void translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation, Mode mode);
+
+ /** Function stub for CheckerCPU compilation issues. RISC-V does not
+ * support the Checker model at the moment.
+ */
+ Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
+ Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
+
+ private:
+ Fault translateInst(RequestPtr req, ThreadContext *tc);
+ Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
+};
+
+}
+
+
+
+#endif // __RISCV_MEMORY_HH__
--- /dev/null
+/*
+ * Copyright (c) 2013 ARM Limited
+ * Copyright (c) 2014 Sven Karlsson
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Hansson
+ * Sven Karlsson
+ */
+
+#ifndef __ARCH_RISCV_TYPES_HH__
+#define __ARCH_RISCV_TYPES_HH__
+
+#include "arch/generic/types.hh"
+
+namespace RiscvISA
+{
+typedef uint32_t MachInst;
+typedef uint64_t ExtMachInst;
+
+typedef GenericISA::SimplePCState<MachInst> PCState;
+}
+
+
+#endif // __ARCH_RISCV_TYPES_HH__
--- /dev/null
+/*
+ * Copyright (c) 2013 ARM Limited
+ * Copyright (c) 2014-2015 Sven Karlsson
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2016 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Hansson
+ * Sven Karlsson
+ * Alec Roelke
+ */
+
+#ifndef __ARCH_RISCV_UTILITY_HH__
+#define __ARCH_RISCV_UTILITY_HH__
+
+#include <cmath>
+#include <cstdint>
+
+#include "base/types.hh"
+#include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
+
+namespace RiscvISA
+{
+
+inline PCState
+buildRetPC(const PCState &curPC, const PCState &callPC)
+{
+ PCState retPC = callPC;
+ retPC.advance();
+ retPC.pc(curPC.npc());
+ return retPC;
+}
+
+inline uint64_t
+getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
+{
+ return 0;
+}
+
+inline void startupCPU(ThreadContext *tc, int cpuId)
+{
+}
+
+inline void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+ // First loop through the integer registers.
+ for (int i = 0; i < NumIntRegs; ++i)
+ dest->setIntReg(i, src->readIntReg(i));
+
+ // Lastly copy PC/NPC
+ dest->pcState(src->pcState());
+}
+
+inline void
+skipFunction(ThreadContext *tc)
+{
+ panic("Not Implemented for Riscv");
+}
+
+inline void
+advancePC(PCState &pc, const StaticInstPtr &inst)
+{
+ inst->advancePC(pc);
+}
+
+static inline bool
+inUserMode(ThreadContext *tc)
+{
+ return true;
+}
+
+inline uint64_t
+getExecutingAsid(ThreadContext *tc)
+{
+ return 0;
+}
+
+inline void
+initCPU(ThreadContext *, int cpuId)
+{
+ panic("initCPU not implemented for Riscv.\n");
+}
+
+} // namespace RiscvISA
+
+#endif // __ARCH_RISCV_UTILITY_HH__
--- /dev/null
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007-2008 The Florida State University
+ * Copyright (c) 2009 The University of Edinburgh
+ * Copyright (c) 2014-2015 Sven Karlsson
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ * Nathan Binkert
+ * Stephen Hines
+ * Timothy M. Jones
+ * Sven Karlsson
+ */
+
+#ifndef __ARCH_RISCV_VTOPHYS_HH__
+#define __ARCH_RISCV_VTOPHYS_HH__
+
+#include "arch/riscv/isa_traits.hh"
+#include "arch/riscv/utility.hh"
+
+class ThreadContext;
+
+namespace RiscvISA {
+
+inline Addr
+vtophys(Addr vaddr)
+{
+ fatal("VTOPHYS: Unimplemented on RISC-V\n");
+ return vaddr;
+}
+
+inline Addr
+vtophys(ThreadContext *tc, Addr vaddr)
+{
+ fatal("VTOPHYS: Unimplemented on RISC-V\n");
+ return vtophys(vaddr);
+}
+
+} // namespace RiscvISA
+
+#endif // __ARCH_RISCV_VTOPHYS_HH__
+
} else if (ehdr.e_machine == EM_AARCH64 &&
ehdr.e_ident[EI_CLASS] == ELFCLASS64) {
arch = Arm64;
+ } else if (ehdr.e_machine == EM_RISCV) {
+ arch = Riscv;
} else if (ehdr.e_machine == EM_PPC &&
ehdr.e_ident[EI_CLASS] == ELFCLASS32) {
arch = Power;
Arm64,
Arm,
Thumb,
- Power
+ Power,
+ Riscv
};
enum OpSys {
from PowerInterrupts import PowerInterrupts
from PowerISA import PowerISA
isa_class = PowerISA
+elif buildEnv['TARGET_ISA'] == 'riscv':
+ from RiscvTLB import RiscvTLB
+ from RiscvInterrupts import RiscvInterrupts
+ from RiscvISA import RiscvISA
+ isa_class = RiscvISA
class BaseCPU(MemObject):
type = 'BaseCPU'
interrupts = VectorParam.PowerInterrupts(
[], "Interrupt Controller")
isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
+ elif buildEnv['TARGET_ISA'] == 'riscv':
+ dtb = Param.RiscvTLB(RiscvTLB(), "Data TLB")
+ itb = Param.RiscvTLB(RiscvTLB(), "Instruction TLB")
+ interrupts = VectorParam.RiscvInterrupts(
+ [], "Interrupt Controller")
+ isa = VectorParam.RiscvISA([ isa_class() ], "ISA instance")
else:
print "Don't know what TLB to use for ISA %s" % \
buildEnv['TARGET_ISA']
self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)]
elif buildEnv['TARGET_ISA'] == 'power':
self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)]
+ elif buildEnv['TARGET_ISA'] == 'riscv':
+ self.interrupts = \
+ [RiscvInterrupts() for i in xrange(self.numThreads)]
else:
print "Don't know what Interrupt Controller to use for ISA %s" % \
buildEnv['TARGET_ISA']
#include "arch/x86/linux/process.hh"
#elif THE_ISA == POWER_ISA
#include "arch/power/linux/process.hh"
+#elif THE_ISA == RISCV_ISA
+#include "arch/riscv/linux/process.hh"
#else
#error "THE_ISA not set"
#endif
default:
fatal("Unknown/unsupported operating system.");
}
+#elif THE_ISA == RISCV_ISA
+ if (objFile->getArch() != ObjectFile::Riscv)
+ fatal("Object file architecture does not match compiled ISA (RISCV).");
+ switch (objFile->getOpSys()) {
+ case ObjectFile::UnknownOpSys:
+ warn("Unknown operating system; assuming Linux.");
+ // fall through
+ case ObjectFile::Linux:
+ process = new RiscvLinuxProcess(params, objFile);
+ break;
+ default:
+ fatal("Unknown/unsupported operating system.");
+ }
#else
#error "THE_ISA not set"
#endif
projects / gem5.git / commitdiff