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author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 7 Dec 2021 00:03:10 +0000
(
00:03
+0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 7 Dec 2021 00:03:10 +0000
(
00:03
+0000)
src/soc/experiment/dcache.py
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diff --git
a/src/soc/experiment/dcache.py
b/src/soc/experiment/dcache.py
index 3460e9768a886269596d919cce05e904916adb60..25ccac59cdc369615e1529b9897161d356335fa8 100644
(file)
--- a/
src/soc/experiment/dcache.py
+++ b/
src/soc/experiment/dcache.py
@@
-160,6
+160,7
@@
TAG_RAM_WIDTH = TAG_WIDTH * NUM_WAYS
print ("TAG_RAM_WIDTH", TAG_RAM_WIDTH)
print (" TAG_WIDTH", TAG_WIDTH)
print (" NUM_WAYS", NUM_WAYS)
+print (" NUM_LINES", NUM_LINES)
def CacheTagArray():
tag_layout = [('valid', NUM_WAYS),