attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57"
wire width 2 output 43 \ldst_mode
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
- wire width 5 output 44 \reg1
+ wire width 5 output 44 \reg2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
- wire width 5 output 45 \reg2
+ wire width 5 output 45 \reg3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
- wire width 5 output 46 \reg3
+ wire width 5 output 46 \reg1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire width 3 output 47 \cr_in1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 4 input 23 \cu_rd__go_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 24 \src1_i
+ wire width 64 input 24 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 25 \src2_i
+ wire width 64 input 25 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
wire width 1 input 26 \src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 6 input 10 \cu_rd__go_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 11 \src1_i
+ wire width 64 input 11 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 12 \src2_i
+ wire width 64 input 12 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
wire width 32 input 13 \src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 4 input 13 \cu_rd__go_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 14 \src1_i
+ wire width 64 input 14 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 15 \src2_i
+ wire width 64 input 15 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
wire width 64 input 16 \src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 2 input 23 \cu_rd__go_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 24 \src1_i
+ wire width 64 input 24 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 25 \src2_i
+ wire width 64 input 25 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire width 1 output 26 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 input 23 \cu_rd__go_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 24 \src1_i
+ wire width 64 input 24 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 25 \src2_i
+ wire width 64 input 25 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
wire width 1 input 26 \src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 input 20 \cu_rd__go_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 21 \src1_i
+ wire width 64 input 21 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 22 \src2_i
+ wire width 64 input 22 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
wire width 1 input 23 \src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 4 input 21 \cu_rd__go_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 22 \src1_i
+ wire width 64 input 22 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 23 \src2_i
+ wire width 64 input 23 \src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 24 \src3_i
+ wire width 64 input 24 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
wire width 2 input 25 \src4_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 input 23 \cu_rd__go_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 24 \src1_i
+ wire width 64 input 24 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 25 \src2_i
+ wire width 64 input 25 \src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 26 \src3_i
+ wire width 64 input 26 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 2 output 27 \cu_wr__rel_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 4 input 160 \cu_rd__go_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 161 \src1_i
+ wire width 64 input 161 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 6 output 162 \cu_rd__rel_o$28
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 6 input 163 \cu_rd__go_i$29
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 164 \src1_i$30
+ wire width 64 input 164 \src2_i$30
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 4 output 165 \cu_rd__rel_o$31
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 4 input 166 \cu_rd__go_i$32
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 167 \src1_i$33
+ wire width 64 input 167 \src2_i$33
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 2 output 168 \cu_rd__rel_o$34
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 2 input 169 \cu_rd__go_i$35
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 170 \src1_i$36
+ wire width 64 input 170 \src2_i$36
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 171 \cu_rd__rel_o$37
+ wire width 3 output 171 \cu_rd__rel_o$37
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 input 172 \cu_rd__go_i$38
+ wire width 3 input 172 \cu_rd__go_i$38
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 173 \src1_i$39
+ wire width 64 input 173 \src2_i$39
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 output 174 \cu_rd__rel_o$40
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 input 175 \cu_rd__go_i$41
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 176 \src1_i$42
+ wire width 64 input 176 \src2_i$42
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 177 \cu_rd__rel_o$43
+ wire width 4 output 177 \cu_rd__rel_o$43
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 input 178 \cu_rd__go_i$44
+ wire width 4 input 178 \cu_rd__go_i$44
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 179 \src1_i$45
+ wire width 64 input 179 \src2_i$45
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 180 \cu_rd__rel_o$46
+ wire width 3 output 180 \cu_rd__rel_o$46
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 input 181 \cu_rd__go_i$47
+ wire width 3 input 181 \cu_rd__go_i$47
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 182 \src1_i$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 183 \cu_rd__rel_o$49
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 input 184 \cu_rd__go_i$50
+ wire width 64 input 182 \src2_i$48
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 185 \src1_i$51
+ wire width 64 input 183 \src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 186 \src2_i
+ wire width 64 input 184 \src3_i$49
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 187 \src2_i$52
+ wire width 64 input 185 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 188 \src2_i$53
+ wire width 64 input 186 \src1_i$50
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 189 \src2_i$54
+ wire width 64 input 187 \src1_i$51
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 190 \src2_i$55
+ wire width 64 input 188 \src1_i$52
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 6 output 189 \cu_rd__rel_o$53
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 6 input 190 \cu_rd__go_i$54
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 191 \src2_i$56
+ wire width 64 input 191 \src1_i$55
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 192 \src2_i$57
+ wire width 64 input 192 \src1_i$56
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 193 \src2_i$58
+ wire width 64 input 193 \src1_i$57
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 194 \src3_i
+ wire width 64 input 194 \src1_i$58
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 input 195 \src3_i$59
+ wire width 64 input 195 \src1_i$59
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
wire width 1 input 196 \src3_i$60
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
connect \cu_rdmaskn_i \cu_rdmaskn_i
connect \cu_rd__rel_o \cu_rd__rel_o
connect \cu_rd__go_i \cu_rd__go_i
- connect \src1_i \src1_i
connect \src2_i \src2_i
+ connect \src1_i \src1_i
connect \src3_i \src3_i$60
connect \src4_i \src4_i$63
connect \o_ok \o_ok
connect \cu_rdmaskn_i \cu_rdmaskn_i$3
connect \cu_rd__rel_o \cu_rd__rel_o$28
connect \cu_rd__go_i \cu_rd__go_i$29
- connect \src1_i \src1_i$30
- connect \src2_i \src2_i$52
+ connect \src2_i \src2_i$30
+ connect \src1_i \src1_i$50
connect \src3_i \src3_i$65
connect \src4_i \src4_i$66
connect \src5_i \src5_i$70
connect \cu_rdmaskn_i \cu_rdmaskn_i$9
connect \cu_rd__rel_o \cu_rd__rel_o$31
connect \cu_rd__go_i \cu_rd__go_i$32
- connect \src1_i \src1_i$33
- connect \src2_i \src2_i$53
+ connect \src2_i \src2_i$33
+ connect \src1_i \src1_i$51
connect \src3_i \src3_i$73
connect \src4_i \src4_i$76
connect \o_ok \o_ok$81
connect \cu_rdmaskn_i \cu_rdmaskn_i$12
connect \cu_rd__rel_o \cu_rd__rel_o$34
connect \cu_rd__go_i \cu_rd__go_i$35
- connect \src1_i \src1_i$36
- connect \src2_i \src2_i$54
+ connect \src2_i \src2_i$36
+ connect \src1_i \src1_i$52
connect \o_ok \o_ok$84
connect \cu_wr__rel_o \cu_wr__rel_o$85
connect \cu_wr__go_i \cu_wr__go_i$86
connect \cu_issue_i \cu_issue_i$13
connect \cu_busy_o \cu_busy_o$14
connect \cu_rdmaskn_i \cu_rdmaskn_i$15
- connect \cu_rd__rel_o \cu_rd__rel_o$37
- connect \cu_rd__go_i \cu_rd__go_i$38
- connect \src1_i \src1_i$39
+ connect \cu_rd__rel_o \cu_rd__rel_o$53
+ connect \cu_rd__go_i \cu_rd__go_i$54
+ connect \src1_i \src1_i$55
connect \src4_i \src4_i
connect \src6_i \src6_i
connect \src5_i \src5_i
connect \cu_issue_i \cu_issue_i$16
connect \cu_busy_o \cu_busy_o$17
connect \cu_rdmaskn_i \cu_rdmaskn_i$18
- connect \cu_rd__rel_o \cu_rd__rel_o$40
- connect \cu_rd__go_i \cu_rd__go_i$41
- connect \src1_i \src1_i$42
- connect \src2_i \src2_i$55
+ connect \cu_rd__rel_o \cu_rd__rel_o$37
+ connect \cu_rd__go_i \cu_rd__go_i$38
+ connect \src2_i \src2_i$39
+ connect \src1_i \src1_i$56
connect \src3_i \src3_i$61
connect \o_ok \o_ok$90
connect \cu_wr__rel_o \cu_wr__rel_o$91
connect \cu_issue_i \cu_issue_i$19
connect \cu_busy_o \cu_busy_o$20
connect \cu_rdmaskn_i \cu_rdmaskn_i$21
- connect \cu_rd__rel_o \cu_rd__rel_o$43
- connect \cu_rd__go_i \cu_rd__go_i$44
- connect \src1_i \src1_i$45
- connect \src2_i \src2_i$56
+ connect \cu_rd__rel_o \cu_rd__rel_o$40
+ connect \cu_rd__go_i \cu_rd__go_i$41
+ connect \src2_i \src2_i$42
+ connect \src1_i \src1_i$57
connect \src3_i \src3_i$62
connect \o_ok \o_ok$93
connect \cu_wr__rel_o \cu_wr__rel_o$94
connect \cu_issue_i \cu_issue_i$22
connect \cu_busy_o \cu_busy_o$23
connect \cu_rdmaskn_i \cu_rdmaskn_i$24
- connect \cu_rd__rel_o \cu_rd__rel_o$46
- connect \cu_rd__go_i \cu_rd__go_i$47
- connect \src1_i \src1_i$48
- connect \src2_i \src2_i$57
+ connect \cu_rd__rel_o \cu_rd__rel_o$43
+ connect \cu_rd__go_i \cu_rd__go_i$44
+ connect \src2_i \src2_i$45
connect \src3_i \src3_i
+ connect \src1_i \src1_i$58
connect \src4_i \src4_i$64
connect \o_ok \o_ok$96
connect \cu_wr__rel_o \cu_wr__rel_o$97
connect \cu_issue_i \cu_issue_i$25
connect \cu_busy_o \cu_busy_o$26
connect \cu_rdmaskn_i \cu_rdmaskn_i$27
- connect \cu_rd__rel_o \cu_rd__rel_o$49
- connect \cu_rd__go_i \cu_rd__go_i$50
- connect \src1_i \src1_i$51
- connect \src2_i \src2_i$58
- connect \src3_i \src3_i$59
+ connect \cu_rd__rel_o \cu_rd__rel_o$46
+ connect \cu_rd__go_i \cu_rd__go_i$47
+ connect \src2_i \src2_i$48
+ connect \src3_i \src3_i$49
+ connect \src1_i \src1_i$59
connect \cu_wr__rel_o \cu_wr__rel_o$99
connect \cu_wr__go_i \cu_wr__go_i$100
connect \o \o
connect \pimem_ldst_port0_addr_exc_o 1'0
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_0"
+attribute \nmigen.hierarchy "test_issuer.core.int"
+module \int
+ attribute \src "simple/issuer.py:89"
+ wire width 1 input 0 \coresync_clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 1 \dmi__ren
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 output 2 \dmi__data_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 output 3 \src1__data_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 5 input 4 \src1__addr
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 5 \src1__ren
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 input 6 \dest1__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 5 input 7 \dest1__addr
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 8 \dest1__wen
+ memory width 64 size 32 \memory
+ cell $meminit $1
+ parameter \MEMID "\\memory"
+ parameter \ABITS 6
+ parameter \WIDTH 64
+ parameter \WORDS 32
+ parameter \PRIORITY 0
+ connect \ADDR 6'000000
+ connect \DATA 2048'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:185"
+ wire width 5 \memory_r_addr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:185"
+ wire width 64 \memory_r_data
+ cell $memrd \rp_src1
+ parameter \MEMID "\\memory"
+ parameter \ABITS 5
+ parameter \WIDTH 64
+ parameter \CLK_ENABLE 0
+ parameter \CLK_POLARITY 1
+ parameter \TRANSPARENT 1
+ connect \CLK 1'0
+ connect \EN 1'1
+ connect \ADDR \memory_r_addr
+ connect \DATA \memory_r_data
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:185"
+ wire width 5 \memory_r_addr$2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:185"
+ wire width 64 \memory_r_data$3
+ cell $memrd \rp_dmi
+ parameter \MEMID "\\memory"
+ parameter \ABITS 5
+ parameter \WIDTH 64
+ parameter \CLK_ENABLE 0
+ parameter \CLK_POLARITY 1
+ parameter \TRANSPARENT 1
+ connect \CLK 1'0
+ connect \EN 1'1
+ connect \ADDR \memory_r_addr$2
+ connect \DATA \memory_r_data$3
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+ wire width 1 \memory_w_en
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+ wire width 5 \memory_w_addr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+ wire width 64 \memory_w_data
+ cell $memwr \wp_dest1
+ parameter \MEMID "\\memory"
+ parameter \ABITS 5
+ parameter \WIDTH 64
+ parameter \CLK_ENABLE 1
+ parameter \CLK_POLARITY 1
+ parameter \PRIORITY 0
+ connect \CLK \coresync_clk
+ connect \EN { { \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en } }
+ connect \ADDR \memory_w_addr
+ connect \DATA \memory_w_data
+ end
+ process $group_0
+ assign \memory_r_addr 5'00000
+ assign \memory_r_addr \src1__addr
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
+ wire width 1 \wr_detect
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:208"
+ wire width 1 \addrmatch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ wire width 1 $4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ cell $and $5
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \dest1__wen
+ connect \B \addrmatch
+ connect \Y $4
+ end
+ process $group_1
+ assign \wr_detect 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
+ switch { \src1__ren }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
+ case 1'1
+ assign \wr_detect 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ switch { $4 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ case 1'1
+ assign \wr_detect 1'1
+ end
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209"
+ wire width 1 $6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209"
+ cell $eq $7
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 1
+ connect \A \dest1__addr
+ connect \B \src1__addr
+ connect \Y $6
+ end
+ process $group_2
+ assign \addrmatch 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
+ switch { \src1__ren }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
+ case 1'1
+ assign \addrmatch $6
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ wire width 1 $8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ cell $and $9
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \dest1__wen
+ connect \B \addrmatch
+ connect \Y $8
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213"
+ wire width 1 $10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213"
+ cell $not $11
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_detect
+ connect \Y $10
+ end
+ process $group_3
+ assign \src1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
+ switch { \src1__ren }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ switch { $8 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ case 1'1
+ assign \src1__data_o \dest1__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213"
+ switch { $10 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213"
+ case 1'1
+ assign \src1__data_o \memory_r_data
+ end
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 5 \dmi__addr
+ process $group_4
+ assign \memory_r_addr$2 5'00000
+ assign \memory_r_addr$2 \dmi__addr
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
+ wire width 1 \wr_detect$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:208"
+ wire width 1 \addrmatch$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ wire width 1 $14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ cell $and $15
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \dest1__wen
+ connect \B \addrmatch$13
+ connect \Y $14
+ end
+ process $group_5
+ assign \wr_detect$12 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
+ switch { \dmi__ren }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
+ case 1'1
+ assign \wr_detect$12 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ switch { $14 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ case 1'1
+ assign \wr_detect$12 1'1
+ end
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209"
+ wire width 1 $16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209"
+ cell $eq $17
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 1
+ connect \A \dest1__addr
+ connect \B \dmi__addr
+ connect \Y $16
+ end
+ process $group_6
+ assign \addrmatch$13 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
+ switch { \dmi__ren }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
+ case 1'1
+ assign \addrmatch$13 $16
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ wire width 1 $18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ cell $and $19
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \dest1__wen
+ connect \B \addrmatch$13
+ connect \Y $18
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213"
+ wire width 1 $20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213"
+ cell $not $21
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_detect$12
+ connect \Y $20
+ end
+ process $group_7
+ assign \dmi__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
+ switch { \dmi__ren }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ switch { $18 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ case 1'1
+ assign \dmi__data_o \dest1__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213"
+ switch { $20 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213"
+ case 1'1
+ assign \dmi__data_o \memory_r_data$3
+ end
+ end
+ sync init
+ end
+ process $group_8
+ assign \memory_w_addr 5'00000
+ assign \memory_w_addr \dest1__addr
+ sync init
+ end
+ process $group_9
+ assign \memory_w_en 1'0
+ assign \memory_w_en \dest1__wen
+ sync init
+ end
+ process $group_10
+ assign \memory_w_data 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \memory_w_data \dest1__data_i
+ sync init
+ end
+ connect \dmi__addr 5'00000
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.cr.reg_0"
module \reg_0
attribute \src "simple/issuer.py:89"
wire width 1 input 0 \coresync_clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src10__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src10__data_o
+ wire width 4 output 3 \src10__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src30__ren
+ wire width 1 input 4 \src20__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src30__data_o
+ wire width 4 output 5 \src20__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi0__ren
+ wire width 1 input 6 \src30__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi0__data_o
+ wire width 4 output 7 \src30__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest10__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest10__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ wire width 4 input 9 \dest10__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 10 \dest20__wen
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 input 11 \dest20__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 output 12 \r0__data_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 13 \r0__ren
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 input 14 \w0__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 15 \w0__wen
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest20__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w0__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
+ wire width 4 \reg
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
+ wire width 4 \reg$next
process $group_1
- assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src10__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src10__data_o \dest10__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest20__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src10__data_o \dest20__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w0__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src10__data_o \w0__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src10__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src10__data_o 4'0000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src30__ren
+ connect \A \src20__ren
connect \B 1'1
connect \Y $8
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$7 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest20__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$7 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w0__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src30__ren
+ connect \A \src20__ren
connect \B 1'1
connect \Y $10
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \Y $12
end
process $group_3
- assign \src30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src20__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
- assign \src30__data_o \dest10__data_i
+ assign \src20__data_o \dest10__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest20__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src20__data_o \dest20__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w0__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src20__data_o \w0__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
- assign \src30__data_o \reg
+ assign \src20__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \src30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src20__data_o 4'0000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi0__ren
+ connect \A \src30__ren
connect \B 1'1
connect \Y $15
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$14 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest20__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$14 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w0__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi0__ren
+ connect \A \src30__ren
connect \B 1'1
connect \Y $17
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \Y $19
end
process $group_5
- assign \dmi0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src30__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src30__data_o \dest10__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest20__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src30__data_o \dest20__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w0__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
- assign \dmi0__data_o \dest10__data_i
+ assign \src30__data_o \w0__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
- assign \dmi0__data_o \reg
+ assign \src30__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \dmi0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src30__data_o 4'0000
end
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
+ wire width 1 \wr_detect$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ wire width 1 $22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ cell $eq $23
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r0__ren
+ connect \B 1'1
+ connect \Y $22
+ end
process $group_6
+ assign \wr_detect$21 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ switch { $22 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ case 1'1
+ assign \wr_detect$21 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest10__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$21 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest20__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$21 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w0__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$21 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
+ case
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ wire width 1 $24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ cell $eq $25
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r0__ren
+ connect \B 1'1
+ connect \Y $24
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ wire width 1 $26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ cell $not $27
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_detect$21
+ connect \Y $26
+ end
+ process $group_7
+ assign \r0__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ switch { $24 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest10__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \r0__data_o \dest10__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest20__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \r0__data_o \dest20__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w0__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \r0__data_o \w0__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ switch { $26 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ case 1'1
+ assign \r0__data_o \reg
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
+ case
+ assign \r0__data_o 4'0000
+ end
+ sync init
+ end
+ process $group_8
assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest10__data_i
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ switch { \dest20__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ case 1'1
+ assign \reg$next \dest20__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ switch { \w0__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ case 1'1
+ assign \reg$next \w0__data_i
+ end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \reg$next 4'0000
end
sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \reg 4'0000
sync posedge \coresync_clk
update \reg \reg$next
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_1"
+attribute \nmigen.hierarchy "test_issuer.core.cr.reg_1"
module \reg_1
attribute \src "simple/issuer.py:89"
wire width 1 input 0 \coresync_clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src11__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src11__data_o
+ wire width 4 output 3 \src11__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src31__ren
+ wire width 1 input 4 \src21__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src31__data_o
+ wire width 4 output 5 \src21__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi1__ren
+ wire width 1 input 6 \src31__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi1__data_o
+ wire width 4 output 7 \src31__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest11__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest11__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ wire width 4 input 9 \dest11__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 10 \dest21__wen
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 input 11 \dest21__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 output 12 \r1__data_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 13 \r1__ren
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 input 14 \w1__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 15 \w1__wen
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest21__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w1__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
+ wire width 4 \reg
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
+ wire width 4 \reg$next
process $group_1
- assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src11__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src11__data_o \dest11__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest21__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src11__data_o \dest21__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w1__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src11__data_o \w1__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src11__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src11__data_o 4'0000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src31__ren
+ connect \A \src21__ren
connect \B 1'1
connect \Y $8
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$7 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest21__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$7 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w1__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src31__ren
+ connect \A \src21__ren
connect \B 1'1
connect \Y $10
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \Y $12
end
process $group_3
- assign \src31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src21__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
- assign \src31__data_o \dest11__data_i
+ assign \src21__data_o \dest11__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest21__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src21__data_o \dest21__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w1__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src21__data_o \w1__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
- assign \src31__data_o \reg
+ assign \src21__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \src31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src21__data_o 4'0000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi1__ren
+ connect \A \src31__ren
connect \B 1'1
connect \Y $15
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$14 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest21__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$14 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w1__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi1__ren
+ connect \A \src31__ren
connect \B 1'1
connect \Y $17
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \Y $19
end
process $group_5
- assign \dmi1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src31__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src31__data_o \dest11__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest21__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src31__data_o \dest21__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w1__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
- assign \dmi1__data_o \dest11__data_i
+ assign \src31__data_o \w1__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
- assign \dmi1__data_o \reg
+ assign \src31__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \dmi1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src31__data_o 4'0000
end
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
+ wire width 1 \wr_detect$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ wire width 1 $22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ cell $eq $23
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r1__ren
+ connect \B 1'1
+ connect \Y $22
+ end
process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ assign \wr_detect$21 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ switch { $22 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ case 1'1
+ assign \wr_detect$21 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest11__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$21 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest21__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$21 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w1__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$21 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
+ case
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ wire width 1 $24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ cell $eq $25
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r1__ren
+ connect \B 1'1
+ connect \Y $24
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ wire width 1 $26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ cell $not $27
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_detect$21
+ connect \Y $26
+ end
+ process $group_7
+ assign \r1__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ switch { $24 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest11__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \r1__data_o \dest11__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest21__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \r1__data_o \dest21__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w1__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \r1__data_o \w1__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ switch { $26 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ case 1'1
+ assign \r1__data_o \reg
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
+ case
+ assign \r1__data_o 4'0000
+ end
+ sync init
+ end
+ process $group_8
+ assign \reg$next \reg
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ switch { \dest11__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest11__data_i
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ switch { \dest21__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ case 1'1
+ assign \reg$next \dest21__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ switch { \w1__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ case 1'1
+ assign \reg$next \w1__data_i
+ end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \reg$next 4'0000
end
sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \reg 4'0000
sync posedge \coresync_clk
update \reg \reg$next
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_2"
+attribute \nmigen.hierarchy "test_issuer.core.cr.reg_2"
module \reg_2
attribute \src "simple/issuer.py:89"
wire width 1 input 0 \coresync_clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src12__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src12__data_o
+ wire width 4 output 3 \src12__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src32__ren
+ wire width 1 input 4 \src22__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src32__data_o
+ wire width 4 output 5 \src22__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi2__ren
+ wire width 1 input 6 \src32__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi2__data_o
+ wire width 4 output 7 \src32__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest12__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest12__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ wire width 4 input 9 \dest12__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 10 \dest22__wen
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 input 11 \dest22__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 output 12 \r2__data_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 13 \r2__ren
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 input 14 \w2__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 15 \w2__wen
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest22__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w2__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
+ wire width 4 \reg
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
+ wire width 4 \reg$next
process $group_1
- assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src12__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src12__data_o \dest12__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest22__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src12__data_o \dest22__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w2__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src12__data_o \w2__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src12__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src12__data_o 4'0000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src32__ren
+ connect \A \src22__ren
connect \B 1'1
connect \Y $8
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$7 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest22__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$7 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w2__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src32__ren
+ connect \A \src22__ren
connect \B 1'1
connect \Y $10
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \Y $12
end
process $group_3
- assign \src32__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src22__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
- assign \src32__data_o \dest12__data_i
+ assign \src22__data_o \dest12__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest22__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src22__data_o \dest22__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w2__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src22__data_o \w2__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
- assign \src32__data_o \reg
+ assign \src22__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \src32__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src22__data_o 4'0000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi2__ren
+ connect \A \src32__ren
connect \B 1'1
connect \Y $15
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$14 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest22__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$14 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w2__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi2__ren
+ connect \A \src32__ren
connect \B 1'1
connect \Y $17
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \Y $19
end
process $group_5
- assign \dmi2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src32__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src32__data_o \dest12__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest22__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src32__data_o \dest22__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w2__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
- assign \dmi2__data_o \dest12__data_i
+ assign \src32__data_o \w2__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
- assign \dmi2__data_o \reg
+ assign \src32__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \dmi2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src32__data_o 4'0000
end
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
+ wire width 1 \wr_detect$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ wire width 1 $22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ cell $eq $23
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r2__ren
+ connect \B 1'1
+ connect \Y $22
+ end
process $group_6
+ assign \wr_detect$21 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ switch { $22 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ case 1'1
+ assign \wr_detect$21 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest12__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$21 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest22__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$21 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w2__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$21 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
+ case
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ wire width 1 $24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ cell $eq $25
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r2__ren
+ connect \B 1'1
+ connect \Y $24
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ wire width 1 $26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ cell $not $27
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_detect$21
+ connect \Y $26
+ end
+ process $group_7
+ assign \r2__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ switch { $24 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest12__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \r2__data_o \dest12__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest22__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \r2__data_o \dest22__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w2__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \r2__data_o \w2__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ switch { $26 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ case 1'1
+ assign \r2__data_o \reg
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
+ case
+ assign \r2__data_o 4'0000
+ end
+ sync init
+ end
+ process $group_8
assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest12__data_i
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ switch { \dest22__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ case 1'1
+ assign \reg$next \dest22__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ switch { \w2__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ case 1'1
+ assign \reg$next \w2__data_i
+ end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \reg$next 4'0000
end
sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \reg 4'0000
sync posedge \coresync_clk
update \reg \reg$next
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_3"
+attribute \nmigen.hierarchy "test_issuer.core.cr.reg_3"
module \reg_3
attribute \src "simple/issuer.py:89"
wire width 1 input 0 \coresync_clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src13__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src13__data_o
+ wire width 4 output 3 \src13__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src33__ren
+ wire width 1 input 4 \src23__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src33__data_o
+ wire width 4 output 5 \src23__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi3__ren
+ wire width 1 input 6 \src33__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi3__data_o
+ wire width 4 output 7 \src33__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest13__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest13__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ wire width 4 input 9 \dest13__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 10 \dest23__wen
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 input 11 \dest23__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 output 12 \r3__data_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 13 \r3__ren
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 input 14 \w3__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 15 \w3__wen
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest13__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest23__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w3__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
+ wire width 4 \reg
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
+ wire width 4 \reg$next
process $group_1
- assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src13__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest13__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src13__data_o \dest13__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest23__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src13__data_o \dest23__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w3__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src13__data_o \w3__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src13__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src13__data_o 4'0000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src33__ren
+ connect \A \src23__ren
connect \B 1'1
connect \Y $8
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest13__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$7 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest23__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$7 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w3__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src33__ren
+ connect \A \src23__ren
connect \B 1'1
connect \Y $10
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \Y $12
end
process $group_3
- assign \src33__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src23__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest13__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
- assign \src33__data_o \dest13__data_i
+ assign \src23__data_o \dest13__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest23__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src23__data_o \dest23__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w3__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src23__data_o \w3__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
- assign \src33__data_o \reg
+ assign \src23__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \src33__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src23__data_o 4'0000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi3__ren
+ connect \A \src33__ren
connect \B 1'1
connect \Y $15
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest13__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$14 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest23__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$14 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w3__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi3__ren
+ connect \A \src33__ren
connect \B 1'1
connect \Y $17
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \Y $19
end
process $group_5
- assign \dmi3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src33__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest13__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src33__data_o \dest13__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest23__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src33__data_o \dest23__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w3__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
- assign \dmi3__data_o \dest13__data_i
+ assign \src33__data_o \w3__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
- assign \dmi3__data_o \reg
+ assign \src33__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \dmi3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src33__data_o 4'0000
end
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
+ wire width 1 \wr_detect$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ wire width 1 $22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ cell $eq $23
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r3__ren
+ connect \B 1'1
+ connect \Y $22
+ end
process $group_6
+ assign \wr_detect$21 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ switch { $22 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ case 1'1
+ assign \wr_detect$21 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest13__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$21 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest23__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$21 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w3__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$21 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
+ case
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ wire width 1 $24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ cell $eq $25
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r3__ren
+ connect \B 1'1
+ connect \Y $24
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ wire width 1 $26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ cell $not $27
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_detect$21
+ connect \Y $26
+ end
+ process $group_7
+ assign \r3__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ switch { $24 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest13__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \r3__data_o \dest13__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest23__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \r3__data_o \dest23__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w3__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \r3__data_o \w3__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ switch { $26 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ case 1'1
+ assign \r3__data_o \reg
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
+ case
+ assign \r3__data_o 4'0000
+ end
+ sync init
+ end
+ process $group_8
assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest13__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest13__data_i
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ switch { \dest23__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ case 1'1
+ assign \reg$next \dest23__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ switch { \w3__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ case 1'1
+ assign \reg$next \w3__data_i
+ end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \reg$next 4'0000
end
sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \reg 4'0000
sync posedge \coresync_clk
update \reg \reg$next
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_4"
+attribute \nmigen.hierarchy "test_issuer.core.cr.reg_4"
module \reg_4
attribute \src "simple/issuer.py:89"
wire width 1 input 0 \coresync_clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src14__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src14__data_o
+ wire width 4 output 3 \src14__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src34__ren
+ wire width 1 input 4 \src24__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src34__data_o
+ wire width 4 output 5 \src24__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi4__ren
+ wire width 1 input 6 \src34__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi4__data_o
+ wire width 4 output 7 \src34__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest14__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest14__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ wire width 4 input 9 \dest14__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 10 \dest24__wen
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 input 11 \dest24__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 output 12 \r4__data_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 13 \r4__ren
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 input 14 \w4__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 15 \w4__wen
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest14__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest24__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w4__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
+ wire width 4 \reg
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
+ wire width 4 \reg$next
process $group_1
- assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src14__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest14__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src14__data_o \dest14__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest24__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src14__data_o \dest24__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w4__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src14__data_o \w4__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src14__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src14__data_o 4'0000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src34__ren
+ connect \A \src24__ren
connect \B 1'1
connect \Y $8
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest14__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$7 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest24__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$7 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w4__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src34__ren
+ connect \A \src24__ren
connect \B 1'1
connect \Y $10
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \Y $12
end
process $group_3
- assign \src34__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src24__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest14__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
- assign \src34__data_o \dest14__data_i
+ assign \src24__data_o \dest14__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest24__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src24__data_o \dest24__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w4__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src24__data_o \w4__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
- assign \src34__data_o \reg
+ assign \src24__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \src34__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src24__data_o 4'0000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi4__ren
+ connect \A \src34__ren
connect \B 1'1
connect \Y $15
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest14__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$14 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest24__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$14 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w4__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi4__ren
+ connect \A \src34__ren
connect \B 1'1
connect \Y $17
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \Y $19
end
process $group_5
- assign \dmi4__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src34__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest14__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src34__data_o \dest14__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest24__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src34__data_o \dest24__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w4__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
- assign \dmi4__data_o \dest14__data_i
+ assign \src34__data_o \w4__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
- assign \dmi4__data_o \reg
+ assign \src34__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \dmi4__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src34__data_o 4'0000
end
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
+ wire width 1 \wr_detect$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ wire width 1 $22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ cell $eq $23
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r4__ren
+ connect \B 1'1
+ connect \Y $22
+ end
process $group_6
+ assign \wr_detect$21 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ switch { $22 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ case 1'1
+ assign \wr_detect$21 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest14__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$21 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest24__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$21 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w4__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$21 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
+ case
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ wire width 1 $24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ cell $eq $25
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r4__ren
+ connect \B 1'1
+ connect \Y $24
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ wire width 1 $26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ cell $not $27
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_detect$21
+ connect \Y $26
+ end
+ process $group_7
+ assign \r4__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ switch { $24 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest14__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \r4__data_o \dest14__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest24__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \r4__data_o \dest24__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w4__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \r4__data_o \w4__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ switch { $26 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ case 1'1
+ assign \r4__data_o \reg
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
+ case
+ assign \r4__data_o 4'0000
+ end
+ sync init
+ end
+ process $group_8
assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest14__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest14__data_i
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ switch { \dest24__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ case 1'1
+ assign \reg$next \dest24__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ switch { \w4__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ case 1'1
+ assign \reg$next \w4__data_i
+ end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \reg$next 4'0000
end
sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \reg 4'0000
sync posedge \coresync_clk
update \reg \reg$next
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_5"
+attribute \nmigen.hierarchy "test_issuer.core.cr.reg_5"
module \reg_5
attribute \src "simple/issuer.py:89"
wire width 1 input 0 \coresync_clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src15__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src15__data_o
+ wire width 4 output 3 \src15__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src35__ren
+ wire width 1 input 4 \src25__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src35__data_o
+ wire width 4 output 5 \src25__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi5__ren
+ wire width 1 input 6 \src35__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi5__data_o
+ wire width 4 output 7 \src35__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest15__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest15__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ wire width 4 input 9 \dest15__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 10 \dest25__wen
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 input 11 \dest25__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 output 12 \r5__data_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 13 \r5__ren
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 input 14 \w5__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 15 \w5__wen
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest15__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest25__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w5__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
+ wire width 4 \reg
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
+ wire width 4 \reg$next
process $group_1
- assign \src15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src15__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest15__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src15__data_o \dest15__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest25__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src15__data_o \dest25__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w5__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src15__data_o \w5__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src15__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \src15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src15__data_o 4'0000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src35__ren
+ connect \A \src25__ren
connect \B 1'1
connect \Y $8
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest15__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$7 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest25__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$7 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w5__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src35__ren
+ connect \A \src25__ren
connect \B 1'1
connect \Y $10
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \Y $12
end
process $group_3
- assign \src35__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src25__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest15__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
- assign \src35__data_o \dest15__data_i
+ assign \src25__data_o \dest15__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest25__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src25__data_o \dest25__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w5__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src25__data_o \w5__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
- assign \src35__data_o \reg
+ assign \src25__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \src35__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src25__data_o 4'0000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi5__ren
+ connect \A \src35__ren
connect \B 1'1
connect \Y $15
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest15__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$14 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest25__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$14 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w5__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi5__ren
+ connect \A \src35__ren
connect \B 1'1
connect \Y $17
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \Y $19
end
process $group_5
- assign \dmi5__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src35__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest15__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src35__data_o \dest15__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest25__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
- assign \dmi5__data_o \dest15__data_i
+ assign \src35__data_o \dest25__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w5__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src35__data_o \w5__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
- assign \dmi5__data_o \reg
+ assign \src35__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \dmi5__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src35__data_o 4'0000
end
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
+ wire width 1 \wr_detect$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ wire width 1 $22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ cell $eq $23
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r5__ren
+ connect \B 1'1
+ connect \Y $22
+ end
process $group_6
+ assign \wr_detect$21 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ switch { $22 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ case 1'1
+ assign \wr_detect$21 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest15__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$21 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest25__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$21 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w5__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$21 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
+ case
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ wire width 1 $24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ cell $eq $25
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r5__ren
+ connect \B 1'1
+ connect \Y $24
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ wire width 1 $26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ cell $not $27
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_detect$21
+ connect \Y $26
+ end
+ process $group_7
+ assign \r5__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ switch { $24 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest15__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \r5__data_o \dest15__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest25__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \r5__data_o \dest25__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w5__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \r5__data_o \w5__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ switch { $26 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
+ case 1'1
+ assign \r5__data_o \reg
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
+ case
+ assign \r5__data_o 4'0000
+ end
+ sync init
+ end
+ process $group_8
assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest15__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest15__data_i
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ switch { \dest25__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ case 1'1
+ assign \reg$next \dest25__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ switch { \w5__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
+ case 1'1
+ assign \reg$next \w5__data_i
+ end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \reg$next 4'0000
end
sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \reg 4'0000
sync posedge \coresync_clk
update \reg \reg$next
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_6"
+attribute \nmigen.hierarchy "test_issuer.core.cr.reg_6"
module \reg_6
attribute \src "simple/issuer.py:89"
wire width 1 input 0 \coresync_clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src16__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src16__data_o
+ wire width 4 output 3 \src16__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src36__ren
+ wire width 1 input 4 \src26__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src36__data_o
+ wire width 4 output 5 \src26__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi6__ren
+ wire width 1 input 6 \src36__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi6__data_o
+ wire width 4 output 7 \src36__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest16__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest16__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ wire width 4 input 9 \dest16__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 10 \dest26__wen
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 input 11 \dest26__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 output 12 \r6__data_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 13 \r6__ren
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 4 input 14 \w6__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 15 \w6__wen
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest16__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest26__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w6__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
+ wire width 4 \reg
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
+ wire width 4 \reg$next
process $group_1
- assign \src16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src16__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest16__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src16__data_o \dest16__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest26__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src16__data_o \dest26__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w6__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src16__data_o \w6__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src16__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \src16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src16__data_o 4'0000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src36__ren
+ connect \A \src26__ren
connect \B 1'1
connect \Y $8
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest16__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$7 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest26__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$7 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w6__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src36__ren
+ connect \A \src26__ren
connect \B 1'1
connect \Y $10
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \Y $12
end
process $group_3
- assign \src36__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src26__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest16__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
- assign \src36__data_o \dest16__data_i
+ assign \src26__data_o \dest16__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest26__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src26__data_o \dest26__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w6__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src26__data_o \w6__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
- assign \src36__data_o \reg
+ assign \src26__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \src36__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src26__data_o 4'0000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi6__ren
+ connect \A \src36__ren
connect \B 1'1
connect \Y $15
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest16__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$14 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest26__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \wr_detect$14 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w6__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi6__ren
+ connect \A \src36__ren
connect \B 1'1
connect \Y $17
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \Y $19
end
process $group_5
- assign \dmi6__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ assign \src36__data_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest16__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src36__data_o \dest16__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \dest26__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ case 1'1
+ assign \src36__data_o \dest26__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
+ switch { \w6__wen }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
- assign \dmi6__data_o \dest16__data_i
+ assign \src36__data_o \w6__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
- assign \dmi6__data_o \reg
+ assign \src36__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
- assign \dmi6__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest16__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest16__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src36__data_o 4'0000
end
sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_7"
-module \reg_7
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src17__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src17__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src37__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src37__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi7__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi7__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest17__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest17__data_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
+ wire width 1 \wr_detect$21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
+ wire width 1 $22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src17__ren
+ connect \A \r6__ren
connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest17__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src17__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest17__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src17__data_o \dest17__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src17__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src37__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest17__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src37__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src37__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest17__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src37__data_o \dest17__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src37__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src37__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi7__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest17__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi7__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi7__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest17__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi7__data_o \dest17__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi7__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi7__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest17__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest17__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_8"
-module \reg_8
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src18__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src18__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src38__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src38__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi8__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi8__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest18__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest18__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src18__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest18__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src18__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src18__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest18__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src18__data_o \dest18__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src18__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src18__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src38__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest18__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src38__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src38__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest18__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src38__data_o \dest18__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src38__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src38__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi8__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest18__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi8__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi8__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest18__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi8__data_o \dest18__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi8__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi8__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest18__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest18__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_9"
-module \reg_9
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src19__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src19__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src39__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src39__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi9__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi9__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest19__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest19__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src19__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest19__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src19__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src19__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest19__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src19__data_o \dest19__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src19__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src19__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src39__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest19__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src39__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src39__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest19__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src39__data_o \dest19__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src39__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src39__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi9__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest19__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi9__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi9__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest19__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi9__data_o \dest19__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi9__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi9__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest19__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest19__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_10"
-module \reg_10
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src110__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src110__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src310__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src310__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi10__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi10__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest110__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest110__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src110__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest110__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src110__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src110__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest110__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src110__data_o \dest110__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src110__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src110__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src310__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest110__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src310__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src310__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest110__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src310__data_o \dest110__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src310__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src310__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi10__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest110__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi10__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest110__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi10__data_o \dest110__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi10__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest110__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest110__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_11"
-module \reg_11
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src111__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src111__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src311__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src311__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi11__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi11__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest111__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest111__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src111__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest111__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src111__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src111__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest111__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src111__data_o \dest111__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src111__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src111__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src311__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest111__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src311__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src311__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest111__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src311__data_o \dest111__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src311__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src311__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi11__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest111__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi11__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest111__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi11__data_o \dest111__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi11__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest111__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest111__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_12"
-module \reg_12
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src112__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src112__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src312__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src312__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi12__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi12__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest112__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest112__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src112__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest112__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src112__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src112__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest112__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src112__data_o \dest112__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src112__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src112__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src312__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest112__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src312__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src312__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest112__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src312__data_o \dest112__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src312__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src312__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi12__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest112__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi12__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest112__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi12__data_o \dest112__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi12__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest112__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest112__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_13"
-module \reg_13
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src113__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src113__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src313__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src313__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi13__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi13__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest113__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest113__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src113__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest113__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src113__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src113__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest113__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src113__data_o \dest113__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src113__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src113__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src313__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest113__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src313__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src313__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest113__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src313__data_o \dest113__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src313__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src313__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi13__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest113__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi13__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest113__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi13__data_o \dest113__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi13__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest113__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest113__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_14"
-module \reg_14
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src114__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src114__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src314__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src314__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi14__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi14__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest114__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest114__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src114__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest114__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src114__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src114__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest114__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src114__data_o \dest114__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src114__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src114__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src314__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest114__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src314__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src314__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest114__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src314__data_o \dest114__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src314__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src314__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi14__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest114__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi14__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest114__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi14__data_o \dest114__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi14__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest114__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest114__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_15"
-module \reg_15
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src115__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src115__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src315__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src315__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi15__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi15__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest115__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest115__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src115__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest115__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src115__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src115__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest115__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src115__data_o \dest115__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src115__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src115__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src315__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest115__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src315__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src315__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest115__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src315__data_o \dest115__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src315__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src315__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi15__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest115__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi15__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest115__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi15__data_o \dest115__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi15__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest115__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest115__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_16"
-module \reg_16
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src116__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src116__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src316__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src316__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi16__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi16__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest116__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest116__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src116__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest116__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src116__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src116__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest116__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src116__data_o \dest116__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src116__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src116__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src316__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest116__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src316__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src316__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest116__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src316__data_o \dest116__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src316__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src316__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi16__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest116__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi16__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest116__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi16__data_o \dest116__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi16__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest116__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest116__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_17"
-module \reg_17
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src117__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src117__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src317__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src317__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi17__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi17__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest117__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest117__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src117__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest117__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src117__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src117__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest117__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src117__data_o \dest117__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src117__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src117__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src317__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest117__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src317__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src317__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest117__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src317__data_o \dest117__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src317__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src317__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi17__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest117__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi17__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest117__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi17__data_o \dest117__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi17__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest117__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest117__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_18"
-module \reg_18
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src118__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src118__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src318__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src318__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi18__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi18__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest118__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest118__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src118__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest118__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src118__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src118__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest118__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src118__data_o \dest118__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src118__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src118__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src318__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest118__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src318__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src318__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest118__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src318__data_o \dest118__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src318__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src318__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi18__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest118__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi18__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi18__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest118__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi18__data_o \dest118__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi18__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi18__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest118__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest118__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_19"
-module \reg_19
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src119__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src119__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src319__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src319__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi19__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi19__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest119__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest119__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src119__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest119__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src119__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src119__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest119__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src119__data_o \dest119__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src119__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src119__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src319__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest119__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src319__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src319__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest119__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src319__data_o \dest119__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src319__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src319__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi19__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest119__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi19__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi19__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest119__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi19__data_o \dest119__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi19__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi19__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest119__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest119__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_20"
-module \reg_20
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src120__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src120__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src320__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src320__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi20__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi20__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest120__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest120__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src120__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest120__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src120__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src120__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest120__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src120__data_o \dest120__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src120__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src120__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src320__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest120__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src320__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src320__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest120__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src320__data_o \dest120__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src320__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src320__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi20__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest120__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi20__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest120__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi20__data_o \dest120__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi20__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest120__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest120__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_21"
-module \reg_21
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src121__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src121__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src321__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src321__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi21__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi21__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest121__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest121__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src121__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest121__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src121__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src121__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest121__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src121__data_o \dest121__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src121__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src121__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src321__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest121__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src321__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src321__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest121__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src321__data_o \dest121__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src321__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src321__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi21__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest121__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi21__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest121__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi21__data_o \dest121__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi21__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest121__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest121__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_22"
-module \reg_22
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src122__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src122__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src322__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src322__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi22__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi22__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest122__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest122__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src122__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest122__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src122__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src122__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest122__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src122__data_o \dest122__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src122__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src122__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src322__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest122__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src322__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src322__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest122__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src322__data_o \dest122__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src322__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src322__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi22__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest122__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi22__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest122__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi22__data_o \dest122__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi22__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest122__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest122__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_23"
-module \reg_23
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src123__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src123__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src323__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src323__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi23__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi23__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest123__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest123__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src123__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest123__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src123__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src123__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest123__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src123__data_o \dest123__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src123__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src123__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src323__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest123__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src323__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src323__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest123__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src323__data_o \dest123__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src323__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src323__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi23__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest123__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi23__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest123__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi23__data_o \dest123__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi23__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest123__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest123__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_24"
-module \reg_24
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src124__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src124__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src324__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src324__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi24__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi24__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest124__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest124__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src124__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest124__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src124__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src124__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest124__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src124__data_o \dest124__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src124__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src124__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src324__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest124__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src324__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src324__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest124__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src324__data_o \dest124__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src324__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src324__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi24__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest124__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi24__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest124__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi24__data_o \dest124__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi24__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest124__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest124__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_25"
-module \reg_25
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src125__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src125__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src325__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src325__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi25__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi25__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest125__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest125__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src125__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest125__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src125__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src125__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest125__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src125__data_o \dest125__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src125__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src125__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src325__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest125__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src325__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src325__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest125__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src325__data_o \dest125__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src325__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src325__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi25__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest125__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi25__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest125__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi25__data_o \dest125__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi25__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest125__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest125__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_26"
-module \reg_26
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src126__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src126__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src326__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src326__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi26__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi26__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest126__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest126__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src126__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest126__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src126__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src126__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest126__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src126__data_o \dest126__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src126__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src126__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src326__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest126__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src326__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src326__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest126__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src326__data_o \dest126__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src326__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src326__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi26__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest126__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi26__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest126__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi26__data_o \dest126__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi26__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest126__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest126__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_27"
-module \reg_27
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src127__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src127__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src327__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src327__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi27__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi27__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest127__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest127__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src127__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest127__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src127__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src127__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest127__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src127__data_o \dest127__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src127__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src127__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src327__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest127__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src327__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src327__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest127__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src327__data_o \dest127__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src327__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src327__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi27__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest127__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi27__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest127__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi27__data_o \dest127__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi27__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest127__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest127__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_28"
-module \reg_28
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src128__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src128__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src328__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src328__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi28__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi28__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest128__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest128__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src128__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest128__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src128__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src128__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest128__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src128__data_o \dest128__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src128__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src128__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src328__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest128__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src328__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src328__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest128__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src328__data_o \dest128__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src328__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src328__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi28__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest128__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi28__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi28__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest128__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi28__data_o \dest128__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi28__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi28__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest128__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest128__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_29"
-module \reg_29
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src129__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src129__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src329__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src329__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi29__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi29__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest129__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest129__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src129__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest129__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src129__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src129__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest129__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src129__data_o \dest129__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src129__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src129__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src329__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest129__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src329__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src329__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest129__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src329__data_o \dest129__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src329__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src329__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi29__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest129__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi29__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi29__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest129__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi29__data_o \dest129__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi29__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi29__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest129__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest129__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_30"
-module \reg_30
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src130__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src130__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src330__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src330__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi30__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi30__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest130__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest130__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src130__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest130__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src130__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src130__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest130__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src130__data_o \dest130__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src130__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src130__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src330__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest130__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src330__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src330__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest130__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src330__data_o \dest130__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src330__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src330__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi30__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest130__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi30__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest130__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi30__data_o \dest130__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi30__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest130__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest130__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_31"
-module \reg_31
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src131__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src131__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src331__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src331__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \dmi31__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \dmi31__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest131__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 9 \dest131__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src131__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest131__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src131__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 64 \reg$next
- process $group_1
- assign \src131__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest131__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src131__data_o \dest131__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src131__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src131__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src331__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest131__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src331__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src331__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest131__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src331__data_o \dest131__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src331__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src331__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi31__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest131__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi31__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \dmi31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest131__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \dmi31__data_o \dest131__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \dmi31__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \dmi31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_6
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest131__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest131__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int"
-module \int
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 32 input 1 \dmi__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 2 \dmi__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src1__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 32 input 4 \src1__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src3__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 32 input 6 \src3__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 7 \data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 32 input 8 \wen
- attribute \src "simple/issuer.py:89"
- wire width 1 input 9 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_0_src10__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_0_src10__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_0_src30__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_0_src30__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_0_dmi0__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_0_dmi0__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_0_dest10__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_0_dest10__data_i
- cell \reg_0 \reg_0
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src10__ren \reg_0_src10__ren
- connect \src10__data_o \reg_0_src10__data_o
- connect \src30__ren \reg_0_src30__ren
- connect \src30__data_o \reg_0_src30__data_o
- connect \dmi0__ren \reg_0_dmi0__ren
- connect \dmi0__data_o \reg_0_dmi0__data_o
- connect \dest10__wen \reg_0_dest10__wen
- connect \dest10__data_i \reg_0_dest10__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_1_src11__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_1_src11__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_1_src31__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_1_src31__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_1_dmi1__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_1_dmi1__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_1_dest11__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_1_dest11__data_i
- cell \reg_1 \reg_1
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src11__ren \reg_1_src11__ren
- connect \src11__data_o \reg_1_src11__data_o
- connect \src31__ren \reg_1_src31__ren
- connect \src31__data_o \reg_1_src31__data_o
- connect \dmi1__ren \reg_1_dmi1__ren
- connect \dmi1__data_o \reg_1_dmi1__data_o
- connect \dest11__wen \reg_1_dest11__wen
- connect \dest11__data_i \reg_1_dest11__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_2_src12__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_2_src12__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_2_src32__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_2_src32__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_2_dmi2__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_2_dmi2__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_2_dest12__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_2_dest12__data_i
- cell \reg_2 \reg_2
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src12__ren \reg_2_src12__ren
- connect \src12__data_o \reg_2_src12__data_o
- connect \src32__ren \reg_2_src32__ren
- connect \src32__data_o \reg_2_src32__data_o
- connect \dmi2__ren \reg_2_dmi2__ren
- connect \dmi2__data_o \reg_2_dmi2__data_o
- connect \dest12__wen \reg_2_dest12__wen
- connect \dest12__data_i \reg_2_dest12__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_3_src13__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_3_src13__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_3_src33__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_3_src33__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_3_dmi3__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_3_dmi3__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_3_dest13__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_3_dest13__data_i
- cell \reg_3 \reg_3
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src13__ren \reg_3_src13__ren
- connect \src13__data_o \reg_3_src13__data_o
- connect \src33__ren \reg_3_src33__ren
- connect \src33__data_o \reg_3_src33__data_o
- connect \dmi3__ren \reg_3_dmi3__ren
- connect \dmi3__data_o \reg_3_dmi3__data_o
- connect \dest13__wen \reg_3_dest13__wen
- connect \dest13__data_i \reg_3_dest13__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_4_src14__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_4_src14__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_4_src34__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_4_src34__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_4_dmi4__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_4_dmi4__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_4_dest14__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_4_dest14__data_i
- cell \reg_4 \reg_4
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src14__ren \reg_4_src14__ren
- connect \src14__data_o \reg_4_src14__data_o
- connect \src34__ren \reg_4_src34__ren
- connect \src34__data_o \reg_4_src34__data_o
- connect \dmi4__ren \reg_4_dmi4__ren
- connect \dmi4__data_o \reg_4_dmi4__data_o
- connect \dest14__wen \reg_4_dest14__wen
- connect \dest14__data_i \reg_4_dest14__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_5_src15__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_5_src15__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_5_src35__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_5_src35__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_5_dmi5__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_5_dmi5__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_5_dest15__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_5_dest15__data_i
- cell \reg_5 \reg_5
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src15__ren \reg_5_src15__ren
- connect \src15__data_o \reg_5_src15__data_o
- connect \src35__ren \reg_5_src35__ren
- connect \src35__data_o \reg_5_src35__data_o
- connect \dmi5__ren \reg_5_dmi5__ren
- connect \dmi5__data_o \reg_5_dmi5__data_o
- connect \dest15__wen \reg_5_dest15__wen
- connect \dest15__data_i \reg_5_dest15__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_6_src16__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_6_src16__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_6_src36__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_6_src36__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_6_dmi6__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_6_dmi6__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_6_dest16__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_6_dest16__data_i
- cell \reg_6 \reg_6
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src16__ren \reg_6_src16__ren
- connect \src16__data_o \reg_6_src16__data_o
- connect \src36__ren \reg_6_src36__ren
- connect \src36__data_o \reg_6_src36__data_o
- connect \dmi6__ren \reg_6_dmi6__ren
- connect \dmi6__data_o \reg_6_dmi6__data_o
- connect \dest16__wen \reg_6_dest16__wen
- connect \dest16__data_i \reg_6_dest16__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_7_src17__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_7_src17__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_7_src37__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_7_src37__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_7_dmi7__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_7_dmi7__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_7_dest17__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_7_dest17__data_i
- cell \reg_7 \reg_7
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src17__ren \reg_7_src17__ren
- connect \src17__data_o \reg_7_src17__data_o
- connect \src37__ren \reg_7_src37__ren
- connect \src37__data_o \reg_7_src37__data_o
- connect \dmi7__ren \reg_7_dmi7__ren
- connect \dmi7__data_o \reg_7_dmi7__data_o
- connect \dest17__wen \reg_7_dest17__wen
- connect \dest17__data_i \reg_7_dest17__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_8_src18__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_8_src18__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_8_src38__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_8_src38__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_8_dmi8__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_8_dmi8__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_8_dest18__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_8_dest18__data_i
- cell \reg_8 \reg_8
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src18__ren \reg_8_src18__ren
- connect \src18__data_o \reg_8_src18__data_o
- connect \src38__ren \reg_8_src38__ren
- connect \src38__data_o \reg_8_src38__data_o
- connect \dmi8__ren \reg_8_dmi8__ren
- connect \dmi8__data_o \reg_8_dmi8__data_o
- connect \dest18__wen \reg_8_dest18__wen
- connect \dest18__data_i \reg_8_dest18__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_9_src19__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_9_src19__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_9_src39__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_9_src39__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_9_dmi9__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_9_dmi9__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_9_dest19__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_9_dest19__data_i
- cell \reg_9 \reg_9
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src19__ren \reg_9_src19__ren
- connect \src19__data_o \reg_9_src19__data_o
- connect \src39__ren \reg_9_src39__ren
- connect \src39__data_o \reg_9_src39__data_o
- connect \dmi9__ren \reg_9_dmi9__ren
- connect \dmi9__data_o \reg_9_dmi9__data_o
- connect \dest19__wen \reg_9_dest19__wen
- connect \dest19__data_i \reg_9_dest19__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_10_src110__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_10_src110__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_10_src310__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_10_src310__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_10_dmi10__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_10_dmi10__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_10_dest110__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_10_dest110__data_i
- cell \reg_10 \reg_10
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src110__ren \reg_10_src110__ren
- connect \src110__data_o \reg_10_src110__data_o
- connect \src310__ren \reg_10_src310__ren
- connect \src310__data_o \reg_10_src310__data_o
- connect \dmi10__ren \reg_10_dmi10__ren
- connect \dmi10__data_o \reg_10_dmi10__data_o
- connect \dest110__wen \reg_10_dest110__wen
- connect \dest110__data_i \reg_10_dest110__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_11_src111__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_11_src111__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_11_src311__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_11_src311__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_11_dmi11__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_11_dmi11__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_11_dest111__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_11_dest111__data_i
- cell \reg_11 \reg_11
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src111__ren \reg_11_src111__ren
- connect \src111__data_o \reg_11_src111__data_o
- connect \src311__ren \reg_11_src311__ren
- connect \src311__data_o \reg_11_src311__data_o
- connect \dmi11__ren \reg_11_dmi11__ren
- connect \dmi11__data_o \reg_11_dmi11__data_o
- connect \dest111__wen \reg_11_dest111__wen
- connect \dest111__data_i \reg_11_dest111__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_12_src112__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_12_src112__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_12_src312__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_12_src312__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_12_dmi12__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_12_dmi12__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_12_dest112__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_12_dest112__data_i
- cell \reg_12 \reg_12
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src112__ren \reg_12_src112__ren
- connect \src112__data_o \reg_12_src112__data_o
- connect \src312__ren \reg_12_src312__ren
- connect \src312__data_o \reg_12_src312__data_o
- connect \dmi12__ren \reg_12_dmi12__ren
- connect \dmi12__data_o \reg_12_dmi12__data_o
- connect \dest112__wen \reg_12_dest112__wen
- connect \dest112__data_i \reg_12_dest112__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_13_src113__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_13_src113__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_13_src313__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_13_src313__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_13_dmi13__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_13_dmi13__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_13_dest113__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_13_dest113__data_i
- cell \reg_13 \reg_13
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src113__ren \reg_13_src113__ren
- connect \src113__data_o \reg_13_src113__data_o
- connect \src313__ren \reg_13_src313__ren
- connect \src313__data_o \reg_13_src313__data_o
- connect \dmi13__ren \reg_13_dmi13__ren
- connect \dmi13__data_o \reg_13_dmi13__data_o
- connect \dest113__wen \reg_13_dest113__wen
- connect \dest113__data_i \reg_13_dest113__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_14_src114__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_14_src114__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_14_src314__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_14_src314__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_14_dmi14__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_14_dmi14__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_14_dest114__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_14_dest114__data_i
- cell \reg_14 \reg_14
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src114__ren \reg_14_src114__ren
- connect \src114__data_o \reg_14_src114__data_o
- connect \src314__ren \reg_14_src314__ren
- connect \src314__data_o \reg_14_src314__data_o
- connect \dmi14__ren \reg_14_dmi14__ren
- connect \dmi14__data_o \reg_14_dmi14__data_o
- connect \dest114__wen \reg_14_dest114__wen
- connect \dest114__data_i \reg_14_dest114__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_15_src115__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_15_src115__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_15_src315__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_15_src315__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_15_dmi15__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_15_dmi15__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_15_dest115__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_15_dest115__data_i
- cell \reg_15 \reg_15
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src115__ren \reg_15_src115__ren
- connect \src115__data_o \reg_15_src115__data_o
- connect \src315__ren \reg_15_src315__ren
- connect \src315__data_o \reg_15_src315__data_o
- connect \dmi15__ren \reg_15_dmi15__ren
- connect \dmi15__data_o \reg_15_dmi15__data_o
- connect \dest115__wen \reg_15_dest115__wen
- connect \dest115__data_i \reg_15_dest115__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_16_src116__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_16_src116__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_16_src316__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_16_src316__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_16_dmi16__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_16_dmi16__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_16_dest116__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_16_dest116__data_i
- cell \reg_16 \reg_16
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src116__ren \reg_16_src116__ren
- connect \src116__data_o \reg_16_src116__data_o
- connect \src316__ren \reg_16_src316__ren
- connect \src316__data_o \reg_16_src316__data_o
- connect \dmi16__ren \reg_16_dmi16__ren
- connect \dmi16__data_o \reg_16_dmi16__data_o
- connect \dest116__wen \reg_16_dest116__wen
- connect \dest116__data_i \reg_16_dest116__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_17_src117__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_17_src117__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_17_src317__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_17_src317__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_17_dmi17__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_17_dmi17__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_17_dest117__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_17_dest117__data_i
- cell \reg_17 \reg_17
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src117__ren \reg_17_src117__ren
- connect \src117__data_o \reg_17_src117__data_o
- connect \src317__ren \reg_17_src317__ren
- connect \src317__data_o \reg_17_src317__data_o
- connect \dmi17__ren \reg_17_dmi17__ren
- connect \dmi17__data_o \reg_17_dmi17__data_o
- connect \dest117__wen \reg_17_dest117__wen
- connect \dest117__data_i \reg_17_dest117__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_18_src118__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_18_src118__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_18_src318__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_18_src318__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_18_dmi18__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_18_dmi18__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_18_dest118__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_18_dest118__data_i
- cell \reg_18 \reg_18
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src118__ren \reg_18_src118__ren
- connect \src118__data_o \reg_18_src118__data_o
- connect \src318__ren \reg_18_src318__ren
- connect \src318__data_o \reg_18_src318__data_o
- connect \dmi18__ren \reg_18_dmi18__ren
- connect \dmi18__data_o \reg_18_dmi18__data_o
- connect \dest118__wen \reg_18_dest118__wen
- connect \dest118__data_i \reg_18_dest118__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_19_src119__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_19_src119__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_19_src319__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_19_src319__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_19_dmi19__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_19_dmi19__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_19_dest119__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_19_dest119__data_i
- cell \reg_19 \reg_19
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src119__ren \reg_19_src119__ren
- connect \src119__data_o \reg_19_src119__data_o
- connect \src319__ren \reg_19_src319__ren
- connect \src319__data_o \reg_19_src319__data_o
- connect \dmi19__ren \reg_19_dmi19__ren
- connect \dmi19__data_o \reg_19_dmi19__data_o
- connect \dest119__wen \reg_19_dest119__wen
- connect \dest119__data_i \reg_19_dest119__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_20_src120__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_20_src120__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_20_src320__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_20_src320__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_20_dmi20__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_20_dmi20__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_20_dest120__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_20_dest120__data_i
- cell \reg_20 \reg_20
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src120__ren \reg_20_src120__ren
- connect \src120__data_o \reg_20_src120__data_o
- connect \src320__ren \reg_20_src320__ren
- connect \src320__data_o \reg_20_src320__data_o
- connect \dmi20__ren \reg_20_dmi20__ren
- connect \dmi20__data_o \reg_20_dmi20__data_o
- connect \dest120__wen \reg_20_dest120__wen
- connect \dest120__data_i \reg_20_dest120__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_21_src121__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_21_src121__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_21_src321__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_21_src321__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_21_dmi21__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_21_dmi21__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_21_dest121__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_21_dest121__data_i
- cell \reg_21 \reg_21
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src121__ren \reg_21_src121__ren
- connect \src121__data_o \reg_21_src121__data_o
- connect \src321__ren \reg_21_src321__ren
- connect \src321__data_o \reg_21_src321__data_o
- connect \dmi21__ren \reg_21_dmi21__ren
- connect \dmi21__data_o \reg_21_dmi21__data_o
- connect \dest121__wen \reg_21_dest121__wen
- connect \dest121__data_i \reg_21_dest121__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_22_src122__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_22_src122__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_22_src322__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_22_src322__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_22_dmi22__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_22_dmi22__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_22_dest122__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_22_dest122__data_i
- cell \reg_22 \reg_22
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src122__ren \reg_22_src122__ren
- connect \src122__data_o \reg_22_src122__data_o
- connect \src322__ren \reg_22_src322__ren
- connect \src322__data_o \reg_22_src322__data_o
- connect \dmi22__ren \reg_22_dmi22__ren
- connect \dmi22__data_o \reg_22_dmi22__data_o
- connect \dest122__wen \reg_22_dest122__wen
- connect \dest122__data_i \reg_22_dest122__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_23_src123__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_23_src123__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_23_src323__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_23_src323__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_23_dmi23__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_23_dmi23__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_23_dest123__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_23_dest123__data_i
- cell \reg_23 \reg_23
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src123__ren \reg_23_src123__ren
- connect \src123__data_o \reg_23_src123__data_o
- connect \src323__ren \reg_23_src323__ren
- connect \src323__data_o \reg_23_src323__data_o
- connect \dmi23__ren \reg_23_dmi23__ren
- connect \dmi23__data_o \reg_23_dmi23__data_o
- connect \dest123__wen \reg_23_dest123__wen
- connect \dest123__data_i \reg_23_dest123__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_24_src124__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_24_src124__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_24_src324__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_24_src324__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_24_dmi24__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_24_dmi24__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_24_dest124__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_24_dest124__data_i
- cell \reg_24 \reg_24
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src124__ren \reg_24_src124__ren
- connect \src124__data_o \reg_24_src124__data_o
- connect \src324__ren \reg_24_src324__ren
- connect \src324__data_o \reg_24_src324__data_o
- connect \dmi24__ren \reg_24_dmi24__ren
- connect \dmi24__data_o \reg_24_dmi24__data_o
- connect \dest124__wen \reg_24_dest124__wen
- connect \dest124__data_i \reg_24_dest124__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_25_src125__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_25_src125__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_25_src325__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_25_src325__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_25_dmi25__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_25_dmi25__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_25_dest125__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_25_dest125__data_i
- cell \reg_25 \reg_25
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src125__ren \reg_25_src125__ren
- connect \src125__data_o \reg_25_src125__data_o
- connect \src325__ren \reg_25_src325__ren
- connect \src325__data_o \reg_25_src325__data_o
- connect \dmi25__ren \reg_25_dmi25__ren
- connect \dmi25__data_o \reg_25_dmi25__data_o
- connect \dest125__wen \reg_25_dest125__wen
- connect \dest125__data_i \reg_25_dest125__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_26_src126__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_26_src126__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_26_src326__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_26_src326__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_26_dmi26__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_26_dmi26__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_26_dest126__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_26_dest126__data_i
- cell \reg_26 \reg_26
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src126__ren \reg_26_src126__ren
- connect \src126__data_o \reg_26_src126__data_o
- connect \src326__ren \reg_26_src326__ren
- connect \src326__data_o \reg_26_src326__data_o
- connect \dmi26__ren \reg_26_dmi26__ren
- connect \dmi26__data_o \reg_26_dmi26__data_o
- connect \dest126__wen \reg_26_dest126__wen
- connect \dest126__data_i \reg_26_dest126__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_27_src127__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_27_src127__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_27_src327__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_27_src327__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_27_dmi27__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_27_dmi27__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_27_dest127__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_27_dest127__data_i
- cell \reg_27 \reg_27
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src127__ren \reg_27_src127__ren
- connect \src127__data_o \reg_27_src127__data_o
- connect \src327__ren \reg_27_src327__ren
- connect \src327__data_o \reg_27_src327__data_o
- connect \dmi27__ren \reg_27_dmi27__ren
- connect \dmi27__data_o \reg_27_dmi27__data_o
- connect \dest127__wen \reg_27_dest127__wen
- connect \dest127__data_i \reg_27_dest127__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_28_src128__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_28_src128__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_28_src328__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_28_src328__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_28_dmi28__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_28_dmi28__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_28_dest128__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_28_dest128__data_i
- cell \reg_28 \reg_28
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src128__ren \reg_28_src128__ren
- connect \src128__data_o \reg_28_src128__data_o
- connect \src328__ren \reg_28_src328__ren
- connect \src328__data_o \reg_28_src328__data_o
- connect \dmi28__ren \reg_28_dmi28__ren
- connect \dmi28__data_o \reg_28_dmi28__data_o
- connect \dest128__wen \reg_28_dest128__wen
- connect \dest128__data_i \reg_28_dest128__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_29_src129__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_29_src129__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_29_src329__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_29_src329__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_29_dmi29__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_29_dmi29__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_29_dest129__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_29_dest129__data_i
- cell \reg_29 \reg_29
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src129__ren \reg_29_src129__ren
- connect \src129__data_o \reg_29_src129__data_o
- connect \src329__ren \reg_29_src329__ren
- connect \src329__data_o \reg_29_src329__data_o
- connect \dmi29__ren \reg_29_dmi29__ren
- connect \dmi29__data_o \reg_29_dmi29__data_o
- connect \dest129__wen \reg_29_dest129__wen
- connect \dest129__data_i \reg_29_dest129__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_30_src130__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_30_src130__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_30_src330__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_30_src330__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_30_dmi30__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_30_dmi30__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_30_dest130__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_30_dest130__data_i
- cell \reg_30 \reg_30
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src130__ren \reg_30_src130__ren
- connect \src130__data_o \reg_30_src130__data_o
- connect \src330__ren \reg_30_src330__ren
- connect \src330__data_o \reg_30_src330__data_o
- connect \dmi30__ren \reg_30_dmi30__ren
- connect \dmi30__data_o \reg_30_dmi30__data_o
- connect \dest130__wen \reg_30_dest130__wen
- connect \dest130__data_i \reg_30_dest130__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_31_src131__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_31_src131__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_31_src331__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_31_src331__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_31_dmi31__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_31_dmi31__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_31_dest131__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_31_dest131__data_i
- cell \reg_31 \reg_31
- connect \coresync_clk \coresync_clk
- connect \coresync_rst \coresync_rst
- connect \src131__ren \reg_31_src131__ren
- connect \src131__data_o \reg_31_src131__data_o
- connect \src331__ren \reg_31_src331__ren
- connect \src331__data_o \reg_31_src331__data_o
- connect \dmi31__ren \reg_31_dmi31__ren
- connect \dmi31__data_o \reg_31_dmi31__data_o
- connect \dest131__wen \reg_31_dest131__wen
- connect \dest131__data_i \reg_31_dest131__data_i
- end
- process $group_0
- assign \reg_0_src10__ren 1'0
- assign \reg_1_src11__ren 1'0
- assign \reg_2_src12__ren 1'0
- assign \reg_3_src13__ren 1'0
- assign \reg_4_src14__ren 1'0
- assign \reg_5_src15__ren 1'0
- assign \reg_6_src16__ren 1'0
- assign \reg_7_src17__ren 1'0
- assign \reg_8_src18__ren 1'0
- assign \reg_9_src19__ren 1'0
- assign \reg_10_src110__ren 1'0
- assign \reg_11_src111__ren 1'0
- assign \reg_12_src112__ren 1'0
- assign \reg_13_src113__ren 1'0
- assign \reg_14_src114__ren 1'0
- assign \reg_15_src115__ren 1'0
- assign \reg_16_src116__ren 1'0
- assign \reg_17_src117__ren 1'0
- assign \reg_18_src118__ren 1'0
- assign \reg_19_src119__ren 1'0
- assign \reg_20_src120__ren 1'0
- assign \reg_21_src121__ren 1'0
- assign \reg_22_src122__ren 1'0
- assign \reg_23_src123__ren 1'0
- assign \reg_24_src124__ren 1'0
- assign \reg_25_src125__ren 1'0
- assign \reg_26_src126__ren 1'0
- assign \reg_27_src127__ren 1'0
- assign \reg_28_src128__ren 1'0
- assign \reg_29_src129__ren 1'0
- assign \reg_30_src130__ren 1'0
- assign \reg_31_src131__ren 1'0
- assign { \reg_31_src131__ren \reg_30_src130__ren \reg_29_src129__ren \reg_28_src128__ren \reg_27_src127__ren \reg_26_src126__ren \reg_25_src125__ren \reg_24_src124__ren \reg_23_src123__ren \reg_22_src122__ren \reg_21_src121__ren \reg_20_src120__ren \reg_19_src119__ren \reg_18_src118__ren \reg_17_src117__ren \reg_16_src116__ren \reg_15_src115__ren \reg_14_src114__ren \reg_13_src113__ren \reg_12_src112__ren \reg_11_src111__ren \reg_10_src110__ren \reg_9_src19__ren \reg_8_src18__ren \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_0_src10__data_o
- connect \B \reg_1_src11__data_o
- connect \Y $1
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $3
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_2_src12__data_o
- connect \B \reg_3_src13__data_o
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $5
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $1
- connect \B $3
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $7
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $8
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_4_src14__data_o
- connect \B \reg_5_src15__data_o
- connect \Y $7
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $9
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $10
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_6_src16__data_o
- connect \B \reg_7_src17__data_o
- connect \Y $9
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $11
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $12
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $7
- connect \B $9
- connect \Y $11
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $13
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $14
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $5
- connect \B $11
- connect \Y $13
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $15
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_8_src18__data_o
- connect \B \reg_9_src19__data_o
- connect \Y $15
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $17
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_10_src110__data_o
- connect \B \reg_11_src111__data_o
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $19
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $15
- connect \B $17
- connect \Y $19
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $21
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $22
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_12_src112__data_o
- connect \B \reg_13_src113__data_o
- connect \Y $21
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $23
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $24
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_14_src114__data_o
- connect \B \reg_15_src115__data_o
- connect \Y $23
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $25
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $26
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $21
- connect \B $23
- connect \Y $25
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $27
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $28
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $19
- connect \B $25
- connect \Y $27
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $29
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $30
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $13
- connect \B $27
- connect \Y $29
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $31
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $32
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_16_src116__data_o
- connect \B \reg_17_src117__data_o
- connect \Y $31
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $33
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $34
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_18_src118__data_o
- connect \B \reg_19_src119__data_o
- connect \Y $33
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $35
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $36
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $31
- connect \B $33
- connect \Y $35
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $37
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $38
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_20_src120__data_o
- connect \B \reg_21_src121__data_o
- connect \Y $37
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $39
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $40
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_22_src122__data_o
- connect \B \reg_23_src123__data_o
- connect \Y $39
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $41
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $42
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $37
- connect \B $39
- connect \Y $41
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $43
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $44
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $35
- connect \B $41
- connect \Y $43
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $45
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $46
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_24_src124__data_o
- connect \B \reg_25_src125__data_o
- connect \Y $45
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $47
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $48
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_26_src126__data_o
- connect \B \reg_27_src127__data_o
- connect \Y $47
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $49
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $50
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $45
- connect \B $47
- connect \Y $49
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $51
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $52
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_28_src128__data_o
- connect \B \reg_29_src129__data_o
- connect \Y $51
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $53
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $54
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_30_src130__data_o
- connect \B \reg_31_src131__data_o
- connect \Y $53
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $55
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $56
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $51
- connect \B $53
- connect \Y $55
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $57
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $58
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $49
- connect \B $55
- connect \Y $57
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $59
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $60
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $43
- connect \B $57
- connect \Y $59
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $61
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $62
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $29
- connect \B $59
- connect \Y $61
- end
- process $group_32
- assign \src1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src1__data_o $61
- sync init
- end
- process $group_33
- assign \reg_0_src30__ren 1'0
- assign \reg_1_src31__ren 1'0
- assign \reg_2_src32__ren 1'0
- assign \reg_3_src33__ren 1'0
- assign \reg_4_src34__ren 1'0
- assign \reg_5_src35__ren 1'0
- assign \reg_6_src36__ren 1'0
- assign \reg_7_src37__ren 1'0
- assign \reg_8_src38__ren 1'0
- assign \reg_9_src39__ren 1'0
- assign \reg_10_src310__ren 1'0
- assign \reg_11_src311__ren 1'0
- assign \reg_12_src312__ren 1'0
- assign \reg_13_src313__ren 1'0
- assign \reg_14_src314__ren 1'0
- assign \reg_15_src315__ren 1'0
- assign \reg_16_src316__ren 1'0
- assign \reg_17_src317__ren 1'0
- assign \reg_18_src318__ren 1'0
- assign \reg_19_src319__ren 1'0
- assign \reg_20_src320__ren 1'0
- assign \reg_21_src321__ren 1'0
- assign \reg_22_src322__ren 1'0
- assign \reg_23_src323__ren 1'0
- assign \reg_24_src324__ren 1'0
- assign \reg_25_src325__ren 1'0
- assign \reg_26_src326__ren 1'0
- assign \reg_27_src327__ren 1'0
- assign \reg_28_src328__ren 1'0
- assign \reg_29_src329__ren 1'0
- assign \reg_30_src330__ren 1'0
- assign \reg_31_src331__ren 1'0
- assign { \reg_31_src331__ren \reg_30_src330__ren \reg_29_src329__ren \reg_28_src328__ren \reg_27_src327__ren \reg_26_src326__ren \reg_25_src325__ren \reg_24_src324__ren \reg_23_src323__ren \reg_22_src322__ren \reg_21_src321__ren \reg_20_src320__ren \reg_19_src319__ren \reg_18_src318__ren \reg_17_src317__ren \reg_16_src316__ren \reg_15_src315__ren \reg_14_src314__ren \reg_13_src313__ren \reg_12_src312__ren \reg_11_src311__ren \reg_10_src310__ren \reg_9_src39__ren \reg_8_src38__ren \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $63
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $64
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_0_src30__data_o
- connect \B \reg_1_src31__data_o
- connect \Y $63
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $65
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $66
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_2_src32__data_o
- connect \B \reg_3_src33__data_o
- connect \Y $65
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $67
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $68
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $63
- connect \B $65
- connect \Y $67
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $69
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $70
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_4_src34__data_o
- connect \B \reg_5_src35__data_o
- connect \Y $69
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $71
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $72
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_6_src36__data_o
- connect \B \reg_7_src37__data_o
- connect \Y $71
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $73
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $74
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $69
- connect \B $71
- connect \Y $73
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $75
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $76
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $67
- connect \B $73
- connect \Y $75
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $77
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $78
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_8_src38__data_o
- connect \B \reg_9_src39__data_o
- connect \Y $77
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $79
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $80
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_10_src310__data_o
- connect \B \reg_11_src311__data_o
- connect \Y $79
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $81
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $82
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $77
- connect \B $79
- connect \Y $81
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $83
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $84
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_12_src312__data_o
- connect \B \reg_13_src313__data_o
- connect \Y $83
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $85
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $86
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_14_src314__data_o
- connect \B \reg_15_src315__data_o
- connect \Y $85
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $87
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $88
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $83
- connect \B $85
- connect \Y $87
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $89
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $90
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $81
- connect \B $87
- connect \Y $89
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $91
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $92
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $75
- connect \B $89
- connect \Y $91
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $93
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $94
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_16_src316__data_o
- connect \B \reg_17_src317__data_o
- connect \Y $93
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $95
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $96
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_18_src318__data_o
- connect \B \reg_19_src319__data_o
- connect \Y $95
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $97
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $98
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $93
- connect \B $95
- connect \Y $97
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $99
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $100
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_20_src320__data_o
- connect \B \reg_21_src321__data_o
- connect \Y $99
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $101
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $102
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_22_src322__data_o
- connect \B \reg_23_src323__data_o
- connect \Y $101
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $103
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $104
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $99
- connect \B $101
- connect \Y $103
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $105
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $106
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $97
- connect \B $103
- connect \Y $105
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $107
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $108
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_24_src324__data_o
- connect \B \reg_25_src325__data_o
- connect \Y $107
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $109
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $110
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_26_src326__data_o
- connect \B \reg_27_src327__data_o
- connect \Y $109
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $111
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $112
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $107
- connect \B $109
- connect \Y $111
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $113
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $114
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_28_src328__data_o
- connect \B \reg_29_src329__data_o
- connect \Y $113
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $115
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $116
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_30_src330__data_o
- connect \B \reg_31_src331__data_o
- connect \Y $115
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $117
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $118
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $113
- connect \B $115
- connect \Y $117
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $119
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $120
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $111
- connect \B $117
- connect \Y $119
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $121
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $122
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $105
- connect \B $119
- connect \Y $121
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $123
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $124
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $91
- connect \B $121
- connect \Y $123
- end
- process $group_65
- assign \src3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src3__data_o $123
- sync init
- end
- process $group_66
- assign \reg_0_dmi0__ren 1'0
- assign \reg_1_dmi1__ren 1'0
- assign \reg_2_dmi2__ren 1'0
- assign \reg_3_dmi3__ren 1'0
- assign \reg_4_dmi4__ren 1'0
- assign \reg_5_dmi5__ren 1'0
- assign \reg_6_dmi6__ren 1'0
- assign \reg_7_dmi7__ren 1'0
- assign \reg_8_dmi8__ren 1'0
- assign \reg_9_dmi9__ren 1'0
- assign \reg_10_dmi10__ren 1'0
- assign \reg_11_dmi11__ren 1'0
- assign \reg_12_dmi12__ren 1'0
- assign \reg_13_dmi13__ren 1'0
- assign \reg_14_dmi14__ren 1'0
- assign \reg_15_dmi15__ren 1'0
- assign \reg_16_dmi16__ren 1'0
- assign \reg_17_dmi17__ren 1'0
- assign \reg_18_dmi18__ren 1'0
- assign \reg_19_dmi19__ren 1'0
- assign \reg_20_dmi20__ren 1'0
- assign \reg_21_dmi21__ren 1'0
- assign \reg_22_dmi22__ren 1'0
- assign \reg_23_dmi23__ren 1'0
- assign \reg_24_dmi24__ren 1'0
- assign \reg_25_dmi25__ren 1'0
- assign \reg_26_dmi26__ren 1'0
- assign \reg_27_dmi27__ren 1'0
- assign \reg_28_dmi28__ren 1'0
- assign \reg_29_dmi29__ren 1'0
- assign \reg_30_dmi30__ren 1'0
- assign \reg_31_dmi31__ren 1'0
- assign { \reg_31_dmi31__ren \reg_30_dmi30__ren \reg_29_dmi29__ren \reg_28_dmi28__ren \reg_27_dmi27__ren \reg_26_dmi26__ren \reg_25_dmi25__ren \reg_24_dmi24__ren \reg_23_dmi23__ren \reg_22_dmi22__ren \reg_21_dmi21__ren \reg_20_dmi20__ren \reg_19_dmi19__ren \reg_18_dmi18__ren \reg_17_dmi17__ren \reg_16_dmi16__ren \reg_15_dmi15__ren \reg_14_dmi14__ren \reg_13_dmi13__ren \reg_12_dmi12__ren \reg_11_dmi11__ren \reg_10_dmi10__ren \reg_9_dmi9__ren \reg_8_dmi8__ren \reg_7_dmi7__ren \reg_6_dmi6__ren \reg_5_dmi5__ren \reg_4_dmi4__ren \reg_3_dmi3__ren \reg_2_dmi2__ren \reg_1_dmi1__ren \reg_0_dmi0__ren } \dmi__ren
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $125
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $126
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_0_dmi0__data_o
- connect \B \reg_1_dmi1__data_o
- connect \Y $125
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $127
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $128
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_2_dmi2__data_o
- connect \B \reg_3_dmi3__data_o
- connect \Y $127
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $129
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $130
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $125
- connect \B $127
- connect \Y $129
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $131
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $132
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_4_dmi4__data_o
- connect \B \reg_5_dmi5__data_o
- connect \Y $131
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $133
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $134
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_6_dmi6__data_o
- connect \B \reg_7_dmi7__data_o
- connect \Y $133
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $135
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $136
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $131
- connect \B $133
- connect \Y $135
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $137
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $138
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $129
- connect \B $135
- connect \Y $137
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $139
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $140
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_8_dmi8__data_o
- connect \B \reg_9_dmi9__data_o
- connect \Y $139
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $141
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $142
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_10_dmi10__data_o
- connect \B \reg_11_dmi11__data_o
- connect \Y $141
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $143
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $144
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $139
- connect \B $141
- connect \Y $143
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $145
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $146
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_12_dmi12__data_o
- connect \B \reg_13_dmi13__data_o
- connect \Y $145
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $147
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $148
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_14_dmi14__data_o
- connect \B \reg_15_dmi15__data_o
- connect \Y $147
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $149
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $150
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $145
- connect \B $147
- connect \Y $149
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $151
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $152
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $143
- connect \B $149
- connect \Y $151
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $153
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $154
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $137
- connect \B $151
- connect \Y $153
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $155
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $156
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_16_dmi16__data_o
- connect \B \reg_17_dmi17__data_o
- connect \Y $155
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $157
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $158
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_18_dmi18__data_o
- connect \B \reg_19_dmi19__data_o
- connect \Y $157
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $159
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $160
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $155
- connect \B $157
- connect \Y $159
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $161
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $162
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_20_dmi20__data_o
- connect \B \reg_21_dmi21__data_o
- connect \Y $161
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $163
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $164
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_22_dmi22__data_o
- connect \B \reg_23_dmi23__data_o
- connect \Y $163
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $165
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $166
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $161
- connect \B $163
- connect \Y $165
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $167
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $168
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $159
- connect \B $165
- connect \Y $167
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $169
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $170
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_24_dmi24__data_o
- connect \B \reg_25_dmi25__data_o
- connect \Y $169
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $171
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $172
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_26_dmi26__data_o
- connect \B \reg_27_dmi27__data_o
- connect \Y $171
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $173
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $174
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $169
- connect \B $171
- connect \Y $173
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $175
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $176
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_28_dmi28__data_o
- connect \B \reg_29_dmi29__data_o
- connect \Y $175
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $177
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $178
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_30_dmi30__data_o
- connect \B \reg_31_dmi31__data_o
- connect \Y $177
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $179
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $180
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $175
- connect \B $177
- connect \Y $179
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $181
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $182
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $173
- connect \B $179
- connect \Y $181
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $183
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $184
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $167
- connect \B $181
- connect \Y $183
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $185
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $186
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $153
- connect \B $183
- connect \Y $185
- end
- process $group_98
- assign \dmi__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \dmi__data_o $185
- sync init
- end
- process $group_99
- assign \reg_0_dest10__wen 1'0
- assign \reg_1_dest11__wen 1'0
- assign \reg_2_dest12__wen 1'0
- assign \reg_3_dest13__wen 1'0
- assign \reg_4_dest14__wen 1'0
- assign \reg_5_dest15__wen 1'0
- assign \reg_6_dest16__wen 1'0
- assign \reg_7_dest17__wen 1'0
- assign \reg_8_dest18__wen 1'0
- assign \reg_9_dest19__wen 1'0
- assign \reg_10_dest110__wen 1'0
- assign \reg_11_dest111__wen 1'0
- assign \reg_12_dest112__wen 1'0
- assign \reg_13_dest113__wen 1'0
- assign \reg_14_dest114__wen 1'0
- assign \reg_15_dest115__wen 1'0
- assign \reg_16_dest116__wen 1'0
- assign \reg_17_dest117__wen 1'0
- assign \reg_18_dest118__wen 1'0
- assign \reg_19_dest119__wen 1'0
- assign \reg_20_dest120__wen 1'0
- assign \reg_21_dest121__wen 1'0
- assign \reg_22_dest122__wen 1'0
- assign \reg_23_dest123__wen 1'0
- assign \reg_24_dest124__wen 1'0
- assign \reg_25_dest125__wen 1'0
- assign \reg_26_dest126__wen 1'0
- assign \reg_27_dest127__wen 1'0
- assign \reg_28_dest128__wen 1'0
- assign \reg_29_dest129__wen 1'0
- assign \reg_30_dest130__wen 1'0
- assign \reg_31_dest131__wen 1'0
- assign { \reg_31_dest131__wen \reg_30_dest130__wen \reg_29_dest129__wen \reg_28_dest128__wen \reg_27_dest127__wen \reg_26_dest126__wen \reg_25_dest125__wen \reg_24_dest124__wen \reg_23_dest123__wen \reg_22_dest122__wen \reg_21_dest121__wen \reg_20_dest120__wen \reg_19_dest119__wen \reg_18_dest118__wen \reg_17_dest117__wen \reg_16_dest116__wen \reg_15_dest115__wen \reg_14_dest114__wen \reg_13_dest113__wen \reg_12_dest112__wen \reg_11_dest111__wen \reg_10_dest110__wen \reg_9_dest19__wen \reg_8_dest18__wen \reg_7_dest17__wen \reg_6_dest16__wen \reg_5_dest15__wen \reg_4_dest14__wen \reg_3_dest13__wen \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen
- sync init
- end
- process $group_131
- assign \reg_0_dest10__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_0_dest10__data_i \data_i
- sync init
- end
- process $group_132
- assign \reg_1_dest11__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_1_dest11__data_i \data_i
- sync init
- end
- process $group_133
- assign \reg_2_dest12__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_2_dest12__data_i \data_i
- sync init
- end
- process $group_134
- assign \reg_3_dest13__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_3_dest13__data_i \data_i
- sync init
- end
- process $group_135
- assign \reg_4_dest14__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_4_dest14__data_i \data_i
- sync init
- end
- process $group_136
- assign \reg_5_dest15__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_5_dest15__data_i \data_i
- sync init
- end
- process $group_137
- assign \reg_6_dest16__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_6_dest16__data_i \data_i
- sync init
- end
- process $group_138
- assign \reg_7_dest17__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_7_dest17__data_i \data_i
- sync init
- end
- process $group_139
- assign \reg_8_dest18__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_8_dest18__data_i \data_i
- sync init
- end
- process $group_140
- assign \reg_9_dest19__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_9_dest19__data_i \data_i
- sync init
- end
- process $group_141
- assign \reg_10_dest110__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_10_dest110__data_i \data_i
- sync init
- end
- process $group_142
- assign \reg_11_dest111__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_11_dest111__data_i \data_i
- sync init
- end
- process $group_143
- assign \reg_12_dest112__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_12_dest112__data_i \data_i
- sync init
- end
- process $group_144
- assign \reg_13_dest113__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_13_dest113__data_i \data_i
- sync init
- end
- process $group_145
- assign \reg_14_dest114__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_14_dest114__data_i \data_i
- sync init
- end
- process $group_146
- assign \reg_15_dest115__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_15_dest115__data_i \data_i
- sync init
- end
- process $group_147
- assign \reg_16_dest116__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_16_dest116__data_i \data_i
- sync init
- end
- process $group_148
- assign \reg_17_dest117__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_17_dest117__data_i \data_i
- sync init
- end
- process $group_149
- assign \reg_18_dest118__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_18_dest118__data_i \data_i
- sync init
- end
- process $group_150
- assign \reg_19_dest119__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_19_dest119__data_i \data_i
- sync init
- end
- process $group_151
- assign \reg_20_dest120__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_20_dest120__data_i \data_i
- sync init
- end
- process $group_152
- assign \reg_21_dest121__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_21_dest121__data_i \data_i
- sync init
- end
- process $group_153
- assign \reg_22_dest122__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_22_dest122__data_i \data_i
- sync init
- end
- process $group_154
- assign \reg_23_dest123__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_23_dest123__data_i \data_i
- sync init
- end
- process $group_155
- assign \reg_24_dest124__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_24_dest124__data_i \data_i
- sync init
- end
- process $group_156
- assign \reg_25_dest125__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_25_dest125__data_i \data_i
- sync init
- end
- process $group_157
- assign \reg_26_dest126__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_26_dest126__data_i \data_i
- sync init
- end
- process $group_158
- assign \reg_27_dest127__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_27_dest127__data_i \data_i
- sync init
- end
- process $group_159
- assign \reg_28_dest128__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_28_dest128__data_i \data_i
- sync init
- end
- process $group_160
- assign \reg_29_dest129__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_29_dest129__data_i \data_i
- sync init
- end
- process $group_161
- assign \reg_30_dest130__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_30_dest130__data_i \data_i
- sync init
- end
- process $group_162
- assign \reg_31_dest131__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_31_dest131__data_i \data_i
- sync init
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.cr.reg_0"
-module \reg_0$125
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src10__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 3 \src10__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src20__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 5 \src20__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \src30__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 7 \src30__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest10__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 9 \dest10__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 10 \dest20__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 11 \dest20__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 12 \r0__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 13 \r0__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 14 \w0__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 15 \w0__wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src10__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest20__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src10__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 4 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 4 \reg$next
- process $group_1
- assign \src10__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src10__data_o \dest10__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest20__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src10__data_o \dest20__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src10__data_o \w0__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src10__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src10__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src20__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest20__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src20__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src20__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src20__data_o \dest10__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest20__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src20__data_o \dest20__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src20__data_o \w0__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src20__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src20__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src30__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest20__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src30__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \src30__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src30__data_o \dest10__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest20__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src30__data_o \dest20__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src30__data_o \w0__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src30__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src30__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $23
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \r0__ren
- connect \B 1'1
- connect \Y $22
- end
- process $group_6
- assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $22 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$21 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest20__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$21 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$21 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $25
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \r0__ren
- connect \B 1'1
- connect \Y $24
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $27
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$21
- connect \Y $26
- end
- process $group_7
- assign \r0__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $24 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \r0__data_o \dest10__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest20__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \r0__data_o \dest20__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \r0__data_o \w0__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $26 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \r0__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \r0__data_o 4'0000
- end
- sync init
- end
- process $group_8
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest10__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest20__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest20__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \w0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \w0__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 4'0000
- end
- sync init
- update \reg 4'0000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.cr.reg_1"
-module \reg_1$126
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src11__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 3 \src11__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src21__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 5 \src21__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \src31__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 7 \src31__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest11__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 9 \dest11__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 10 \dest21__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 11 \dest21__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 12 \r1__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 13 \r1__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 14 \w1__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 15 \w1__wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src11__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest21__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src11__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 4 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 4 \reg$next
- process $group_1
- assign \src11__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src11__data_o \dest11__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest21__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src11__data_o \dest21__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src11__data_o \w1__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src11__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src11__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src21__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest21__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src21__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src21__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src21__data_o \dest11__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest21__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src21__data_o \dest21__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src21__data_o \w1__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src21__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src21__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src31__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest21__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src31__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \src31__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src31__data_o \dest11__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest21__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src31__data_o \dest21__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src31__data_o \w1__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src31__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src31__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $23
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \r1__ren
- connect \B 1'1
- connect \Y $22
- end
- process $group_6
- assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $22 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$21 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest21__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$21 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$21 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $25
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \r1__ren
- connect \B 1'1
- connect \Y $24
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $27
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$21
- connect \Y $26
- end
- process $group_7
- assign \r1__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $24 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \r1__data_o \dest11__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest21__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \r1__data_o \dest21__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \r1__data_o \w1__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $26 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \r1__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \r1__data_o 4'0000
- end
- sync init
- end
- process $group_8
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest11__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest21__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest21__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \w1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \w1__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 4'0000
- end
- sync init
- update \reg 4'0000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.cr.reg_2"
-module \reg_2$127
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src12__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 3 \src12__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src22__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 5 \src22__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \src32__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 7 \src32__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest12__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 9 \dest12__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 10 \dest22__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 11 \dest22__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 12 \r2__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 13 \r2__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 14 \w2__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 15 \w2__wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src12__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest22__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w2__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src12__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 4 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 4 \reg$next
- process $group_1
- assign \src12__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src12__data_o \dest12__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest22__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src12__data_o \dest22__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w2__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src12__data_o \w2__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src12__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src12__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src22__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest22__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w2__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src22__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src22__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src22__data_o \dest12__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest22__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src22__data_o \dest22__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w2__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src22__data_o \w2__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src22__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src22__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src32__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest22__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w2__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src32__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \src32__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src32__data_o \dest12__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest22__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src32__data_o \dest22__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w2__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src32__data_o \w2__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src32__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src32__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $23
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \r2__ren
- connect \B 1'1
- connect \Y $22
- end
- process $group_6
- assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $22 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$21 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest22__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$21 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w2__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$21 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $25
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \r2__ren
- connect \B 1'1
- connect \Y $24
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $27
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$21
- connect \Y $26
- end
- process $group_7
- assign \r2__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $24 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \r2__data_o \dest12__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest22__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \r2__data_o \dest22__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w2__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \r2__data_o \w2__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $26 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \r2__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \r2__data_o 4'0000
- end
- sync init
- end
- process $group_8
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest12__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest22__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest22__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \w2__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \w2__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 4'0000
- end
- sync init
- update \reg 4'0000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.cr.reg_3"
-module \reg_3$128
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src13__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 3 \src13__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src23__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 5 \src23__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \src33__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 7 \src33__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest13__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 9 \dest13__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 10 \dest23__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 11 \dest23__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 12 \r3__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 13 \r3__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 14 \w3__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 15 \w3__wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src13__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest13__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest23__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w3__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src13__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 4 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 4 \reg$next
- process $group_1
- assign \src13__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest13__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src13__data_o \dest13__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest23__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src13__data_o \dest23__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w3__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src13__data_o \w3__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src13__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src13__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src23__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest13__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest23__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w3__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src23__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src23__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest13__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src23__data_o \dest13__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest23__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src23__data_o \dest23__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w3__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src23__data_o \w3__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src23__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src23__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src33__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest13__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest23__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w3__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src33__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \src33__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest13__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src33__data_o \dest13__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest23__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src33__data_o \dest23__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w3__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src33__data_o \w3__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src33__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src33__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $23
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \r3__ren
- connect \B 1'1
- connect \Y $22
- end
- process $group_6
- assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $22 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest13__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$21 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest23__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$21 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w3__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$21 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $25
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \r3__ren
- connect \B 1'1
- connect \Y $24
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $27
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$21
- connect \Y $26
- end
- process $group_7
- assign \r3__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $24 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest13__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \r3__data_o \dest13__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest23__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \r3__data_o \dest23__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w3__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \r3__data_o \w3__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $26 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \r3__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \r3__data_o 4'0000
- end
- sync init
- end
- process $group_8
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest13__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest13__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest23__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest23__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \w3__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \w3__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 4'0000
- end
- sync init
- update \reg 4'0000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.cr.reg_4"
-module \reg_4$129
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src14__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 3 \src14__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src24__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 5 \src24__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \src34__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 7 \src34__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest14__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 9 \dest14__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 10 \dest24__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 11 \dest24__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 12 \r4__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 13 \r4__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 14 \w4__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 15 \w4__wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src14__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest14__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest24__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w4__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src14__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 4 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 4 \reg$next
- process $group_1
- assign \src14__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest14__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src14__data_o \dest14__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest24__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src14__data_o \dest24__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w4__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src14__data_o \w4__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src14__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src14__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src24__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest14__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest24__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w4__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src24__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src24__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest14__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src24__data_o \dest14__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest24__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src24__data_o \dest24__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w4__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src24__data_o \w4__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src24__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src24__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src34__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest14__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest24__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w4__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src34__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \src34__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest14__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src34__data_o \dest14__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest24__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src34__data_o \dest24__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w4__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src34__data_o \w4__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src34__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src34__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $23
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \r4__ren
- connect \B 1'1
- connect \Y $22
- end
- process $group_6
- assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $22 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest14__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$21 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest24__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$21 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w4__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$21 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $25
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \r4__ren
- connect \B 1'1
- connect \Y $24
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $27
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$21
- connect \Y $26
- end
- process $group_7
- assign \r4__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $24 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest14__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \r4__data_o \dest14__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest24__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \r4__data_o \dest24__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w4__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \r4__data_o \w4__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $26 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \r4__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \r4__data_o 4'0000
- end
- sync init
- end
- process $group_8
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest14__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest14__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest24__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest24__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \w4__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \w4__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 4'0000
- end
- sync init
- update \reg 4'0000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.cr.reg_5"
-module \reg_5$130
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src15__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 3 \src15__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src25__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 5 \src25__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \src35__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 7 \src35__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest15__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 9 \dest15__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 10 \dest25__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 11 \dest25__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 12 \r5__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 13 \r5__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 14 \w5__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 15 \w5__wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src15__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest15__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest25__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w5__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src15__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 4 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 4 \reg$next
- process $group_1
- assign \src15__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest15__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src15__data_o \dest15__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest25__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src15__data_o \dest25__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w5__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src15__data_o \w5__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src15__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src15__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src25__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest15__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest25__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w5__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src25__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src25__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest15__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src25__data_o \dest15__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest25__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src25__data_o \dest25__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w5__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src25__data_o \w5__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src25__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src25__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src35__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest15__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest25__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w5__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src35__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \src35__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest15__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src35__data_o \dest15__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest25__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src35__data_o \dest25__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w5__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src35__data_o \w5__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src35__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src35__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $23
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \r5__ren
- connect \B 1'1
- connect \Y $22
- end
- process $group_6
- assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $22 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest15__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$21 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest25__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$21 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w5__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$21 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $25
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \r5__ren
- connect \B 1'1
- connect \Y $24
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $27
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$21
- connect \Y $26
- end
- process $group_7
- assign \r5__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $24 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest15__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \r5__data_o \dest15__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest25__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \r5__data_o \dest25__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w5__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \r5__data_o \w5__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $26 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \r5__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \r5__data_o 4'0000
- end
- sync init
- end
- process $group_8
- assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest15__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest15__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \dest25__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \dest25__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- switch { \w5__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
- case 1'1
- assign \reg$next \w5__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \coresync_rst
- case 1'1
- assign \reg$next 4'0000
- end
- sync init
- update \reg 4'0000
- sync posedge \coresync_clk
- update \reg \reg$next
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.cr.reg_6"
-module \reg_6$131
- attribute \src "simple/issuer.py:89"
- wire width 1 input 0 \coresync_clk
- attribute \src "simple/issuer.py:89"
- wire width 1 input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src16__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 3 \src16__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src26__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 5 \src26__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \src36__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 7 \src36__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \dest16__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 9 \dest16__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 10 \dest26__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 11 \dest26__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 output 12 \r6__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 13 \r6__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 input 14 \w6__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 15 \w6__wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src16__ren
- connect \B 1'1
- connect \Y $1
- end
- process $group_0
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest16__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest26__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w6__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src16__ren
- connect \B 1'1
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 4 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
- wire width 4 \reg$next
- process $group_1
- assign \src16__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest16__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src16__data_o \dest16__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest26__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src16__data_o \dest26__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w6__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src16__data_o \w6__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src16__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src16__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src26__ren
- connect \B 1'1
- connect \Y $8
- end
- process $group_2
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest16__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest26__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w6__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$7 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $11
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src26__ren
- connect \B 1'1
- connect \Y $10
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$7
- connect \Y $12
- end
- process $group_3
- assign \src26__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest16__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src26__data_o \dest16__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest26__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src26__data_o \dest26__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w6__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src26__data_o \w6__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src26__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src26__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src36__ren
- connect \B 1'1
- connect \Y $15
- end
- process $group_4
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest16__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest26__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w6__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$14 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \src36__ren
- connect \B 1'1
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$14
- connect \Y $19
- end
- process $group_5
- assign \src36__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest16__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src36__data_o \dest16__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest26__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src36__data_o \dest26__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \w6__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \src36__data_o \w6__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \src36__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \src36__data_o 4'0000
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $23
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \r6__ren
- connect \B 1'1
- connect \Y $22
+ connect \Y $22
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $22 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest16__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest26__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w6__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \r6__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $24 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest16__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \r6__data_o \dest16__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest26__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \r6__data_o \dest26__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w6__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \r6__data_o \w6__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $26 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \r6__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \r6__data_o 4'0000
end
end
process $group_8
assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest16__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest16__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest26__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest26__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \w6__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \w6__data_i
end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.cr.reg_7"
-module \reg_7$132
+module \reg_7
attribute \src "simple/issuer.py:89"
wire width 1 input 0 \coresync_clk
attribute \src "simple/issuer.py:89"
wire width 4 input 14 \w7__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 15 \w7__wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest17__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest27__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w7__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 4 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 4 \reg$next
process $group_1
assign \src17__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest17__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src17__data_o \dest17__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest27__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src17__data_o \dest27__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w7__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src17__data_o \w7__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src17__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \src17__data_o 4'0000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest17__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest27__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w7__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src27__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest17__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src27__data_o \dest17__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest27__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src27__data_o \dest27__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w7__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src27__data_o \w7__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src27__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \src27__data_o 4'0000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest17__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest27__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w7__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src37__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest17__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src37__data_o \dest17__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest27__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src37__data_o \dest27__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w7__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src37__data_o \w7__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src37__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \src37__data_o 4'0000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $22 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest17__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest27__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w7__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \r7__data_o 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $24 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest17__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \r7__data_o \dest17__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest27__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \r7__data_o \dest27__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w7__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \r7__data_o \w7__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $26 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \r7__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \r7__data_o 4'0000
end
end
process $group_8
assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest17__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest17__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest27__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest27__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \w7__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \w7__data_i
end
wire width 4 \reg_0_w0__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_w0__wen
- cell \reg_0$125 \reg_0
+ cell \reg_0 \reg_0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src10__ren \reg_0_src10__ren
wire width 4 \reg_1_w1__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_w1__wen
- cell \reg_1$126 \reg_1
+ cell \reg_1 \reg_1
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src11__ren \reg_1_src11__ren
wire width 4 \reg_2_w2__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_w2__wen
- cell \reg_2$127 \reg_2
+ cell \reg_2 \reg_2
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src12__ren \reg_2_src12__ren
wire width 4 \reg_3_w3__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_w3__wen
- cell \reg_3$128 \reg_3
+ cell \reg_3 \reg_3
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src13__ren \reg_3_src13__ren
wire width 4 \reg_4_w4__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_w4__wen
- cell \reg_4$129 \reg_4
+ cell \reg_4 \reg_4
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src14__ren \reg_4_src14__ren
wire width 4 \reg_5_w5__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_w5__wen
- cell \reg_5$130 \reg_5
+ cell \reg_5 \reg_5
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src15__ren \reg_5_src15__ren
wire width 4 \reg_6_w6__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_w6__wen
- cell \reg_6$131 \reg_6
+ cell \reg_6 \reg_6
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src16__ren \reg_6_src16__ren
wire width 4 \reg_7_w7__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_w7__wen
- cell \reg_7$132 \reg_7
+ cell \reg_7 \reg_7
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src17__ren \reg_7_src17__ren
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.xer.reg_0"
-module \reg_0$133
+module \reg_0$125
attribute \src "simple/issuer.py:89"
wire width 1 input 0 \coresync_clk
attribute \src "simple/issuer.py:89"
wire width 2 input 16 \w0__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 17 \w0__wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest20__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest30__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 2 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 2 \reg$next
process $group_1
assign \src10__data_o 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src10__data_o \dest10__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest20__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src10__data_o \dest20__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest30__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src10__data_o \dest30__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src10__data_o \w0__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src10__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \src10__data_o 2'00
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest20__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest30__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src20__data_o 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src20__data_o \dest10__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest20__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src20__data_o \dest20__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest30__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src20__data_o \dest30__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src20__data_o \w0__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src20__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \src20__data_o 2'00
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest20__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest30__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src30__data_o 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src30__data_o \dest10__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest20__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src30__data_o \dest20__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest30__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src30__data_o \dest30__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src30__data_o \w0__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src30__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \src30__data_o 2'00
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $22 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest20__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest30__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \r0__data_o 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $24 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \r0__data_o \dest10__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest20__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \r0__data_o \dest20__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest30__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \r0__data_o \dest30__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \r0__data_o \w0__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $26 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \r0__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \r0__data_o 2'00
end
end
process $group_8
assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest10__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest20__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest20__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest30__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest30__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \w0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \w0__data_i
end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.xer.reg_1"
-module \reg_1$134
+module \reg_1$126
attribute \src "simple/issuer.py:89"
wire width 1 input 0 \coresync_clk
attribute \src "simple/issuer.py:89"
wire width 2 input 16 \w1__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 17 \w1__wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest21__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest31__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 2 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 2 \reg$next
process $group_1
assign \src11__data_o 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src11__data_o \dest11__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest21__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src11__data_o \dest21__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest31__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src11__data_o \dest31__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src11__data_o \w1__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src11__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \src11__data_o 2'00
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest21__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest31__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src21__data_o 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src21__data_o \dest11__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest21__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src21__data_o \dest21__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest31__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src21__data_o \dest31__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src21__data_o \w1__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src21__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \src21__data_o 2'00
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest21__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest31__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src31__data_o 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src31__data_o \dest11__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest21__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src31__data_o \dest21__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest31__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src31__data_o \dest31__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src31__data_o \w1__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src31__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \src31__data_o 2'00
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $22 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest21__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest31__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \r1__data_o 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $24 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \r1__data_o \dest11__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest21__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \r1__data_o \dest21__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest31__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \r1__data_o \dest31__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \r1__data_o \w1__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $26 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \r1__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \r1__data_o 2'00
end
end
process $group_8
assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest11__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest21__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest21__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest31__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest31__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \w1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \w1__data_i
end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.xer.reg_2"
-module \reg_2$135
+module \reg_2$127
attribute \src "simple/issuer.py:89"
wire width 1 input 0 \coresync_clk
attribute \src "simple/issuer.py:89"
wire width 2 input 16 \w2__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 17 \w2__wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest22__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest32__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w2__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 2 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 2 \reg$next
process $group_1
assign \src12__data_o 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src12__data_o \dest12__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest22__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src12__data_o \dest22__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest32__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src12__data_o \dest32__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w2__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src12__data_o \w2__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src12__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \src12__data_o 2'00
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest22__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest32__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w2__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src22__data_o 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src22__data_o \dest12__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest22__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src22__data_o \dest22__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest32__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src22__data_o \dest32__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w2__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src22__data_o \w2__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src22__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \src22__data_o 2'00
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest22__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest32__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w2__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src32__data_o 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src32__data_o \dest12__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest22__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src32__data_o \dest22__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest32__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src32__data_o \dest32__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w2__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src32__data_o \w2__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src32__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \src32__data_o 2'00
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $22 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest22__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest32__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w2__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \r2__data_o 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $24 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \r2__data_o \dest12__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest22__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \r2__data_o \dest22__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest32__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \r2__data_o \dest32__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \w2__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \r2__data_o \w2__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $26 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \r2__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \r2__data_o 2'00
end
end
process $group_8
assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest12__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest22__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest22__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest32__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest32__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \w2__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \w2__data_i
end
wire width 2 \reg_0_w0__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_w0__wen
- cell \reg_0$133 \reg_0
+ cell \reg_0$125 \reg_0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src10__ren \reg_0_src10__ren
wire width 2 \reg_1_w1__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_w1__wen
- cell \reg_1$134 \reg_1
+ cell \reg_1$126 \reg_1
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src11__ren \reg_1_src11__ren
wire width 2 \reg_2_w2__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_w2__wen
- cell \reg_2$135 \reg_2
+ cell \reg_2$127 \reg_2
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src12__ren \reg_2_src12__ren
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fast.reg_0"
-module \reg_0$136
+module \reg_0$128
attribute \src "simple/issuer.py:89"
wire width 1 input 0 \coresync_clk
attribute \src "simple/issuer.py:89"
wire width 1 input 4 \dest30__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 5 \dest30__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest30__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 64 \reg$next
process $group_1
assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest30__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src10__data_o \dest30__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src10__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_2
assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest30__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest30__data_i
end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fast.reg_1"
-module \reg_1$137
+module \reg_1$129
attribute \src "simple/issuer.py:89"
wire width 1 input 0 \coresync_clk
attribute \src "simple/issuer.py:89"
wire width 1 input 4 \dest31__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 5 \dest31__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest31__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 64 \reg$next
process $group_1
assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest31__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src11__data_o \dest31__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src11__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_2
assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest31__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest31__data_i
end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fast.reg_2"
-module \reg_2$138
+module \reg_2$130
attribute \src "simple/issuer.py:89"
wire width 1 input 0 \coresync_clk
attribute \src "simple/issuer.py:89"
wire width 1 input 4 \dest32__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 5 \dest32__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest32__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 64 \reg$next
process $group_1
assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest32__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src12__data_o \dest32__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src12__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_2
assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest32__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest32__data_i
end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fast.reg_3"
-module \reg_3$139
+module \reg_3$131
attribute \src "simple/issuer.py:89"
wire width 1 input 0 \coresync_clk
attribute \src "simple/issuer.py:89"
wire width 1 input 4 \dest33__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 5 \dest33__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest33__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 64 \reg$next
process $group_1
assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest33__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src13__data_o \dest33__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src13__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_2
assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest33__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest33__data_i
end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fast.reg_4"
-module \reg_4$140
+module \reg_4$132
attribute \src "simple/issuer.py:89"
wire width 1 input 0 \coresync_clk
attribute \src "simple/issuer.py:89"
wire width 1 input 4 \dest34__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 5 \dest34__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest34__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 64 \reg$next
process $group_1
assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \dest34__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \src14__data_o \dest34__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \src14__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_2
assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \dest34__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \dest34__data_i
end
wire width 1 \reg_0_dest30__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_0_dest30__data_i
- cell \reg_0$136 \reg_0
+ cell \reg_0$128 \reg_0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src10__ren \reg_0_src10__ren
wire width 1 \reg_1_dest31__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_1_dest31__data_i
- cell \reg_1$137 \reg_1
+ cell \reg_1$129 \reg_1
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src11__ren \reg_1_src11__ren
wire width 1 \reg_2_dest32__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_2_dest32__data_i
- cell \reg_2$138 \reg_2
+ cell \reg_2$130 \reg_2
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src12__ren \reg_2_src12__ren
wire width 1 \reg_3_dest33__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_3_dest33__data_i
- cell \reg_3$139 \reg_3
+ cell \reg_3$131 \reg_3
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src13__ren \reg_3_src13__ren
wire width 1 \reg_4_dest34__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_4_dest34__data_i
- cell \reg_4$140 \reg_4
+ cell \reg_4$132 \reg_4
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src14__ren \reg_4_src14__ren
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.state.reg_0"
-module \reg_0$141
+module \reg_0$133
attribute \src "simple/issuer.py:89"
wire width 1 input 0 \coresync_clk
attribute \src "simple/issuer.py:89"
wire width 1 input 10 \d_wr10__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \d_wr10__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \nia0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \msr0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \d_wr10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 64 \reg$next
process $group_1
assign \cia0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \nia0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \cia0__data_o \nia0__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \msr0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \cia0__data_o \msr0__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \d_wr10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \cia0__data_o \d_wr10__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \cia0__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \cia0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \nia0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \msr0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \d_wr10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \msr0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \nia0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \msr0__data_o \nia0__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \msr0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \msr0__data_o \msr0__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \d_wr10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \msr0__data_o \d_wr10__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \msr0__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \msr0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_4
assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \nia0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \nia0__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \msr0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \msr0__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \d_wr10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \d_wr10__data_i
end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.state.reg_1"
-module \reg_1$142
+module \reg_1$134
attribute \src "simple/issuer.py:89"
wire width 1 input 0 \coresync_clk
attribute \src "simple/issuer.py:89"
wire width 1 input 10 \d_wr11__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \d_wr11__data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \nia1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \msr1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \d_wr11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 64 \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57"
wire width 64 \reg$next
process $group_1
assign \cia1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $3 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \nia1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \cia1__data_o \nia1__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \msr1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \cia1__data_o \msr1__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \d_wr11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \cia1__data_o \d_wr11__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $5 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \cia1__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \cia1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63"
wire width 1 \wr_detect$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $8 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \nia1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \msr1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \d_wr11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \msr1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \nia1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \msr1__data_o \nia1__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \msr1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \msr1__data_o \msr1__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
switch { \d_wr11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66"
case 1'1
assign \msr1__data_o \d_wr11__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69"
case 1'1
assign \msr1__data_o \reg
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73"
case
assign \msr1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_4
assign \reg$next \reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \nia1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \nia1__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \msr1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \msr1__data_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
switch { \d_wr11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78"
case 1'1
assign \reg$next \d_wr11__data_i
end
wire width 1 \reg_0_d_wr10__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_0_d_wr10__data_i
- cell \reg_0$141 \reg_0
+ cell \reg_0$133 \reg_0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \cia0__ren \reg_0_cia0__ren
wire width 1 \reg_1_d_wr11__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_1_d_wr11__data_i
- cell \reg_1$142 \reg_1
+ cell \reg_1$134 \reg_1
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \cia1__ren \reg_1_cia1__ren
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_ra"
-module \rdpick_INT_ra
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 9 input 0 \i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 9 output 1 \o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
- wire width 1 output 2 \en_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
- wire width 9 \ni
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
- wire width 9 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
- cell $not $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 9
- parameter \Y_WIDTH 9
- connect \A \i
- connect \Y $1
+attribute \nmigen.hierarchy "test_issuer.core.spr"
+module \spr
+ attribute \src "simple/issuer.py:89"
+ wire width 1 input 0 \coresync_clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 output 1 \spr1__data_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 7 input 2 \spr1__addr
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 3 \spr1__ren
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 input 4 \spr1__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 7 input 5 \spr1__addr$1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 input 6 \spr1__wen
+ memory width 64 size 110 \memory
+ cell $meminit $2
+ parameter \MEMID "\\memory"
+ parameter \ABITS 7
+ parameter \WIDTH 64
+ parameter \WORDS 110
+ parameter \PRIORITY 0
+ connect \ADDR 7'0000000
+ connect \DATA 7040'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:185"
+ wire width 7 \memory_r_addr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:185"
+ wire width 64 \memory_r_data
+ cell $memrd \rp_spr1
+ parameter \MEMID "\\memory"
+ parameter \ABITS 7
+ parameter \WIDTH 64
+ parameter \CLK_ENABLE 0
+ parameter \CLK_POLARITY 1
+ parameter \TRANSPARENT 1
+ connect \CLK 1'0
+ connect \EN 1'1
+ connect \ADDR \memory_r_addr
+ connect \DATA \memory_r_data
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+ wire width 1 \memory_w_en
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+ wire width 7 \memory_w_addr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+ wire width 64 \memory_w_data
+ cell $memwr \wp_spr1
+ parameter \MEMID "\\memory"
+ parameter \ABITS 7
+ parameter \WIDTH 64
+ parameter \CLK_ENABLE 1
+ parameter \CLK_POLARITY 1
+ parameter \PRIORITY 0
+ connect \CLK \coresync_clk
+ connect \EN { { \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en } }
+ connect \ADDR \memory_w_addr
+ connect \DATA \memory_w_data
end
process $group_0
- assign \ni 9'000000000
- assign \ni $1
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 1 \t0
- process $group_1
- assign \t0 1'0
- assign \t0 \i [0]
+ assign \memory_r_addr 7'0000000
+ assign \memory_r_addr \spr1__addr
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 1 \t1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
+ wire width 1 \wr_detect
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:208"
+ wire width 1 \addrmatch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $4
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- cell $reduce_bool $5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ cell $and $4
parameter \A_SIGNED 0
- parameter \A_WIDTH 2
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A { \i [0] \ni [1] }
- connect \Y $4
+ connect \A \spr1__wen
+ connect \B \addrmatch
+ connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- cell $not $6
+ process $group_1
+ assign \wr_detect 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
+ switch { \spr1__ren }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
+ case 1'1
+ assign \wr_detect 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ switch { $3 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ case 1'1
+ assign \wr_detect 1'1
+ end
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209"
+ cell $eq $6
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
+ parameter \A_WIDTH 7
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
parameter \Y_WIDTH 1
- connect \A $4
- connect \Y $3
+ connect \A \spr1__addr$1
+ connect \B \spr1__addr
+ connect \Y $5
end
process $group_2
- assign \t1 1'0
- assign \t1 $3
+ assign \addrmatch 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
+ switch { \spr1__ren }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
+ case 1'1
+ assign \addrmatch $5
+ end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 1 \t2
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
wire width 1 $7
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- cell $reduce_bool $9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ cell $and $8
parameter \A_SIGNED 0
- parameter \A_WIDTH 3
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
- connect \Y $8
+ connect \A \spr1__wen
+ connect \B \addrmatch
+ connect \Y $7
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213"
cell $not $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $8
- connect \Y $7
+ connect \A \wr_detect
+ connect \Y $9
end
process $group_3
- assign \t2 1'0
- assign \t2 $7
+ assign \spr1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
+ switch { \spr1__ren }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ switch { $7 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
+ case 1'1
+ assign \spr1__data_o \spr1__data_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213"
+ switch { $9 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213"
+ case 1'1
+ assign \spr1__data_o \memory_r_data
+ end
+ end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 1 \t3
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $11
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- cell $reduce_bool $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \Y_WIDTH 1
- connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
- connect \Y $12
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- cell $not $14
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $12
- connect \Y $11
- end
process $group_4
- assign \t3 1'0
- assign \t3 $11
+ assign \memory_w_addr 7'0000000
+ assign \memory_w_addr \spr1__addr$1
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 1 \t4
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $16
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- cell $reduce_bool $17
- parameter \A_SIGNED 0
- parameter \A_WIDTH 5
- parameter \Y_WIDTH 1
- connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] }
- connect \Y $16
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- cell $not $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $16
- connect \Y $15
- end
process $group_5
- assign \t4 1'0
- assign \t4 $15
+ assign \memory_w_en 1'0
+ assign \memory_w_en \spr1__wen
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 1 \t5
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $20
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- cell $reduce_bool $21
- parameter \A_SIGNED 0
- parameter \A_WIDTH 6
- parameter \Y_WIDTH 1
- connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] }
- connect \Y $20
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- cell $not $22
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $20
- connect \Y $19
- end
process $group_6
- assign \t5 1'0
- assign \t5 $19
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 1 \t6
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $23
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $24
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- cell $reduce_bool $25
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] }
- connect \Y $24
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- cell $not $26
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $24
- connect \Y $23
- end
- process $group_7
- assign \t6 1'0
- assign \t6 $23
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 1 \t7
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $27
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $28
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- cell $reduce_bool $29
- parameter \A_SIGNED 0
- parameter \A_WIDTH 8
- parameter \Y_WIDTH 1
- connect \A { \i [6:0] [6] \i [6:0] [5] \i [6:0] [4] \i [6:0] [3] \i [6:0] [2] \i [6:0] [1] \i [6:0] [0] \ni [7] }
- connect \Y $28
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- cell $not $30
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $28
- connect \Y $27
- end
- process $group_8
- assign \t7 1'0
- assign \t7 $27
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 1 \t8
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $31
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $32
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- cell $reduce_bool $33
- parameter \A_SIGNED 0
- parameter \A_WIDTH 9
- parameter \Y_WIDTH 1
- connect \A { \i [7:0] [7] \i [7:0] [6] \i [7:0] [5] \i [7:0] [4] \i [7:0] [3] \i [7:0] [2] \i [7:0] [1] \i [7:0] [0] \ni [8] }
- connect \Y $32
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- cell $not $34
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $32
- connect \Y $31
- end
- process $group_9
- assign \t8 1'0
- assign \t8 $31
- sync init
- end
- process $group_10
- assign \o 9'000000000
- assign \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- wire width 1 $35
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- cell $reduce_bool $36
- parameter \A_SIGNED 0
- parameter \A_WIDTH 9
- parameter \Y_WIDTH 1
- connect \A \o
- connect \Y $35
- end
- process $group_11
- assign \en_o 1'0
- assign \en_o $35
+ assign \memory_w_data 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \memory_w_data \spr1__data_i
sync init
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rbc"
-module \rdpick_INT_rbc
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rabc"
+module \rdpick_INT_rabc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 10 input 0 \i
+ wire width 19 input 0 \i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 10 output 1 \o
+ wire width 19 output 1 \o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 2 \en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
- wire width 10 \ni
+ wire width 19 \ni
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
- wire width 10 $1
+ wire width 19 $1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
- parameter \A_WIDTH 10
- parameter \Y_WIDTH 10
+ parameter \A_WIDTH 19
+ parameter \Y_WIDTH 19
connect \A \i
connect \Y $1
end
process $group_0
- assign \ni 10'0000000000
+ assign \ni 19'0000000000000000000
assign \ni $1
sync init
end
assign \t9 $35
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t10
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $39
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $40
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $41
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 11
+ parameter \Y_WIDTH 1
+ connect \A { \i [9:0] [9] \i [9:0] [8] \i [9:0] [7] \i [9:0] [6] \i [9:0] [5] \i [9:0] [4] \i [9:0] [3] \i [9:0] [2] \i [9:0] [1] \i [9:0] [0] \ni [10] }
+ connect \Y $40
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $42
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $40
+ connect \Y $39
+ end
process $group_11
- assign \o 10'0000000000
- assign \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
+ assign \t10 1'0
+ assign \t10 $39
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $43
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $44
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $45
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 12
+ parameter \Y_WIDTH 1
+ connect \A { \i [10:0] [10] \i [10:0] [9] \i [10:0] [8] \i [10:0] [7] \i [10:0] [6] \i [10:0] [5] \i [10:0] [4] \i [10:0] [3] \i [10:0] [2] \i [10:0] [1] \i [10:0] [0] \ni [11] }
+ connect \Y $44
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $46
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $44
+ connect \Y $43
+ end
+ process $group_12
+ assign \t11 1'0
+ assign \t11 $43
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t12
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $47
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $48
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $49
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 13
+ parameter \Y_WIDTH 1
+ connect \A { \i [11:0] [11] \i [11:0] [10] \i [11:0] [9] \i [11:0] [8] \i [11:0] [7] \i [11:0] [6] \i [11:0] [5] \i [11:0] [4] \i [11:0] [3] \i [11:0] [2] \i [11:0] [1] \i [11:0] [0] \ni [12] }
+ connect \Y $48
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $50
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $48
+ connect \Y $47
+ end
+ process $group_13
+ assign \t12 1'0
+ assign \t12 $47
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $51
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $52
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $53
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 14
+ parameter \Y_WIDTH 1
+ connect \A { \i [12:0] [12] \i [12:0] [11] \i [12:0] [10] \i [12:0] [9] \i [12:0] [8] \i [12:0] [7] \i [12:0] [6] \i [12:0] [5] \i [12:0] [4] \i [12:0] [3] \i [12:0] [2] \i [12:0] [1] \i [12:0] [0] \ni [13] }
+ connect \Y $52
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $54
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $52
+ connect \Y $51
+ end
+ process $group_14
+ assign \t13 1'0
+ assign \t13 $51
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t14
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $55
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $56
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $57
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 15
+ parameter \Y_WIDTH 1
+ connect \A { \i [13:0] [13] \i [13:0] [12] \i [13:0] [11] \i [13:0] [10] \i [13:0] [9] \i [13:0] [8] \i [13:0] [7] \i [13:0] [6] \i [13:0] [5] \i [13:0] [4] \i [13:0] [3] \i [13:0] [2] \i [13:0] [1] \i [13:0] [0] \ni [14] }
+ connect \Y $56
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $58
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $56
+ connect \Y $55
+ end
+ process $group_15
+ assign \t14 1'0
+ assign \t14 $55
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $59
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $60
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $61
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 16
+ parameter \Y_WIDTH 1
+ connect \A { \i [14:0] [14] \i [14:0] [13] \i [14:0] [12] \i [14:0] [11] \i [14:0] [10] \i [14:0] [9] \i [14:0] [8] \i [14:0] [7] \i [14:0] [6] \i [14:0] [5] \i [14:0] [4] \i [14:0] [3] \i [14:0] [2] \i [14:0] [1] \i [14:0] [0] \ni [15] }
+ connect \Y $60
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $62
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $60
+ connect \Y $59
+ end
+ process $group_16
+ assign \t15 1'0
+ assign \t15 $59
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t16
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $63
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $64
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $65
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 17
+ parameter \Y_WIDTH 1
+ connect \A { \i [15:0] [15] \i [15:0] [14] \i [15:0] [13] \i [15:0] [12] \i [15:0] [11] \i [15:0] [10] \i [15:0] [9] \i [15:0] [8] \i [15:0] [7] \i [15:0] [6] \i [15:0] [5] \i [15:0] [4] \i [15:0] [3] \i [15:0] [2] \i [15:0] [1] \i [15:0] [0] \ni [16] }
+ connect \Y $64
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $66
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $64
+ connect \Y $63
+ end
+ process $group_17
+ assign \t16 1'0
+ assign \t16 $63
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t17
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $67
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $68
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $69
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 18
+ parameter \Y_WIDTH 1
+ connect \A { \i [16:0] [16] \i [16:0] [15] \i [16:0] [14] \i [16:0] [13] \i [16:0] [12] \i [16:0] [11] \i [16:0] [10] \i [16:0] [9] \i [16:0] [8] \i [16:0] [7] \i [16:0] [6] \i [16:0] [5] \i [16:0] [4] \i [16:0] [3] \i [16:0] [2] \i [16:0] [1] \i [16:0] [0] \ni [17] }
+ connect \Y $68
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $70
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $68
+ connect \Y $67
+ end
+ process $group_18
+ assign \t17 1'0
+ assign \t17 $67
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t18
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $71
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $72
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $73
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 19
+ parameter \Y_WIDTH 1
+ connect \A { \i [17:0] [17] \i [17:0] [16] \i [17:0] [15] \i [17:0] [14] \i [17:0] [13] \i [17:0] [12] \i [17:0] [11] \i [17:0] [10] \i [17:0] [9] \i [17:0] [8] \i [17:0] [7] \i [17:0] [6] \i [17:0] [5] \i [17:0] [4] \i [17:0] [3] \i [17:0] [2] \i [17:0] [1] \i [17:0] [0] \ni [18] }
+ connect \Y $72
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $74
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $72
+ connect \Y $71
+ end
+ process $group_19
+ assign \t18 1'0
+ assign \t18 $71
+ sync init
+ end
+ process $group_20
+ assign \o 19'0000000000000000000
+ assign \o { \t18 \t17 \t16 \t15 \t14 \t13 \t12 \t11 \t10 \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- wire width 1 $39
+ wire width 1 $75
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- cell $reduce_bool $40
+ cell $reduce_bool $76
parameter \A_SIGNED 0
- parameter \A_WIDTH 10
+ parameter \A_WIDTH 19
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $39
+ connect \Y $75
end
- process $group_12
+ process $group_21
assign \en_o 1'0
- assign \en_o $39
+ assign \en_o $75
sync init
end
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 21 \data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 32 input 22 \dmi__ren
+ wire width 1 input 22 \dmi__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 23 \dmi__data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57"
wire width 2 \pdecode2_ldst_mode
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
- wire width 5 \pdecode2_reg1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire width 5 \pdecode2_reg2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire width 5 \pdecode2_reg3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+ wire width 5 \pdecode2_reg1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire width 3 \pdecode2_cr_in1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire width 3 \pdecode2_cr_in2
connect \byte_reverse \pdecode2_byte_reverse
connect \sign_extend \pdecode2_sign_extend
connect \ldst_mode \pdecode2_ldst_mode
- connect \reg1 \pdecode2_reg1
connect \reg2 \pdecode2_reg2
connect \reg3 \pdecode2_reg3
+ connect \reg1 \pdecode2_reg1
connect \cr_in1 \pdecode2_cr_in1
connect \cr_in2 \pdecode2_cr_in2
connect \cr_in2$2 \pdecode2_cr_in2$2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 4 \fus_cu_rd__go_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 \fus_src1_i
+ wire width 64 \fus_src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 6 \fus_cu_rd__rel_o$30
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 6 \fus_cu_rd__go_i$31
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 \fus_src1_i$32
+ wire width 64 \fus_src2_i$32
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 4 \fus_cu_rd__rel_o$33
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 4 \fus_cu_rd__go_i$34
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 \fus_src1_i$35
+ wire width 64 \fus_src2_i$35
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 2 \fus_cu_rd__rel_o$36
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 2 \fus_cu_rd__go_i$37
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 \fus_src1_i$38
+ wire width 64 \fus_src2_i$38
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 \fus_cu_rd__rel_o$39
+ wire width 3 \fus_cu_rd__rel_o$39
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 \fus_cu_rd__go_i$40
+ wire width 3 \fus_cu_rd__go_i$40
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 \fus_src1_i$41
+ wire width 64 \fus_src2_i$41
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 \fus_cu_rd__rel_o$42
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 \fus_cu_rd__go_i$43
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 \fus_src1_i$44
+ wire width 64 \fus_src2_i$44
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 \fus_cu_rd__rel_o$45
+ wire width 4 \fus_cu_rd__rel_o$45
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 \fus_cu_rd__go_i$46
+ wire width 4 \fus_cu_rd__go_i$46
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 \fus_src1_i$47
+ wire width 64 \fus_src2_i$47
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 \fus_cu_rd__rel_o$48
+ wire width 3 \fus_cu_rd__rel_o$48
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 \fus_cu_rd__go_i$49
+ wire width 3 \fus_cu_rd__go_i$49
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 \fus_src1_i$50
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 \fus_cu_rd__rel_o$51
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 \fus_cu_rd__go_i$52
+ wire width 64 \fus_src2_i$50
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 \fus_src1_i$53
+ wire width 64 \fus_src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 \fus_src2_i
+ wire width 64 \fus_src3_i$51
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 \fus_src2_i$54
+ wire width 64 \fus_src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 \fus_src2_i$55
+ wire width 64 \fus_src1_i$52
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 \fus_src2_i$56
+ wire width 64 \fus_src1_i$53
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 \fus_src2_i$57
+ wire width 64 \fus_src1_i$54
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 6 \fus_cu_rd__rel_o$55
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 6 \fus_cu_rd__go_i$56
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 \fus_src2_i$58
+ wire width 64 \fus_src1_i$57
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 \fus_src2_i$59
+ wire width 64 \fus_src1_i$58
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 \fus_src2_i$60
+ wire width 64 \fus_src1_i$59
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 \fus_src3_i
+ wire width 64 \fus_src1_i$60
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
- wire width 64 \fus_src3_i$61
+ wire width 64 \fus_src1_i$61
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
wire width 1 \fus_src3_i$62
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
connect \cu_rdmaskn_i$27 \fus_cu_rdmaskn_i$29
connect \cu_rd__rel_o \fus_cu_rd__rel_o
connect \cu_rd__go_i \fus_cu_rd__go_i
- connect \src1_i \fus_src1_i
+ connect \src2_i \fus_src2_i
connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$30
connect \cu_rd__go_i$29 \fus_cu_rd__go_i$31
- connect \src1_i$30 \fus_src1_i$32
+ connect \src2_i$30 \fus_src2_i$32
connect \cu_rd__rel_o$31 \fus_cu_rd__rel_o$33
connect \cu_rd__go_i$32 \fus_cu_rd__go_i$34
- connect \src1_i$33 \fus_src1_i$35
+ connect \src2_i$33 \fus_src2_i$35
connect \cu_rd__rel_o$34 \fus_cu_rd__rel_o$36
connect \cu_rd__go_i$35 \fus_cu_rd__go_i$37
- connect \src1_i$36 \fus_src1_i$38
+ connect \src2_i$36 \fus_src2_i$38
connect \cu_rd__rel_o$37 \fus_cu_rd__rel_o$39
connect \cu_rd__go_i$38 \fus_cu_rd__go_i$40
- connect \src1_i$39 \fus_src1_i$41
+ connect \src2_i$39 \fus_src2_i$41
connect \cu_rd__rel_o$40 \fus_cu_rd__rel_o$42
connect \cu_rd__go_i$41 \fus_cu_rd__go_i$43
- connect \src1_i$42 \fus_src1_i$44
+ connect \src2_i$42 \fus_src2_i$44
connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$45
connect \cu_rd__go_i$44 \fus_cu_rd__go_i$46
- connect \src1_i$45 \fus_src1_i$47
+ connect \src2_i$45 \fus_src2_i$47
connect \cu_rd__rel_o$46 \fus_cu_rd__rel_o$48
connect \cu_rd__go_i$47 \fus_cu_rd__go_i$49
- connect \src1_i$48 \fus_src1_i$50
- connect \cu_rd__rel_o$49 \fus_cu_rd__rel_o$51
- connect \cu_rd__go_i$50 \fus_cu_rd__go_i$52
- connect \src1_i$51 \fus_src1_i$53
- connect \src2_i \fus_src2_i
- connect \src2_i$52 \fus_src2_i$54
- connect \src2_i$53 \fus_src2_i$55
- connect \src2_i$54 \fus_src2_i$56
- connect \src2_i$55 \fus_src2_i$57
- connect \src2_i$56 \fus_src2_i$58
- connect \src2_i$57 \fus_src2_i$59
- connect \src2_i$58 \fus_src2_i$60
+ connect \src2_i$48 \fus_src2_i$50
connect \src3_i \fus_src3_i
- connect \src3_i$59 \fus_src3_i$61
+ connect \src3_i$49 \fus_src3_i$51
+ connect \src1_i \fus_src1_i
+ connect \src1_i$50 \fus_src1_i$52
+ connect \src1_i$51 \fus_src1_i$53
+ connect \src1_i$52 \fus_src1_i$54
+ connect \cu_rd__rel_o$53 \fus_cu_rd__rel_o$55
+ connect \cu_rd__go_i$54 \fus_cu_rd__go_i$56
+ connect \src1_i$55 \fus_src1_i$57
+ connect \src1_i$56 \fus_src1_i$58
+ connect \src1_i$57 \fus_src1_i$59
+ connect \src1_i$58 \fus_src1_i$60
+ connect \src1_i$59 \fus_src1_i$61
connect \src3_i$60 \fus_src3_i$62
connect \src4_i \fus_src4_i
connect \src3_i$61 \fus_src3_i$63
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \int_src1__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 32 \int_src1__ren
+ wire width 5 \int_src1__addr
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \int_src3__data_o
+ wire width 1 \int_src1__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 32 \int_src3__ren
+ wire width 64 \int_dest1__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \int_data_i
+ wire width 5 \int_dest1__addr
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 32 \int_wen
+ wire width 1 \int_dest1__wen
cell \int \int
connect \coresync_clk \coresync_clk
connect \dmi__ren \dmi__ren
connect \dmi__data_o \dmi__data_o
connect \src1__data_o \int_src1__data_o
+ connect \src1__addr \int_src1__addr
connect \src1__ren \int_src1__ren
- connect \src3__data_o \int_src3__data_o
- connect \src3__ren \int_src3__ren
- connect \data_i \int_data_i
- connect \wen \int_wen
- connect \coresync_rst \coresync_rst
+ connect \dest1__data_i \int_dest1__data_i
+ connect \dest1__addr \int_dest1__addr
+ connect \dest1__wen \int_dest1__wen
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 32 \cr_full_rd__data_o
connect \wen$3 \state_wen
connect \coresync_rst \coresync_rst
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 9 \rdpick_INT_ra_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 9 \rdpick_INT_ra_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
- wire width 1 \rdpick_INT_ra_en_o
- cell \rdpick_INT_ra \rdpick_INT_ra
- connect \i \rdpick_INT_ra_i
- connect \o \rdpick_INT_ra_o
- connect \en_o \rdpick_INT_ra_en_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 \spr_spr1__data_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 7 \spr_spr1__addr
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 \spr_spr1__ren
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 \spr_spr1__data_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 7 \spr_spr1__addr$158
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 1 \spr_spr1__wen
+ cell \spr \spr
+ connect \coresync_clk \coresync_clk
+ connect \spr1__data_o \spr_spr1__data_o
+ connect \spr1__addr \spr_spr1__addr
+ connect \spr1__ren \spr_spr1__ren
+ connect \spr1__data_i \spr_spr1__data_i
+ connect \spr1__addr$1 \spr_spr1__addr$158
+ connect \spr1__wen \spr_spr1__wen
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 10 \rdpick_INT_rbc_i
+ wire width 19 \rdpick_INT_rabc_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 10 \rdpick_INT_rbc_o
+ wire width 19 \rdpick_INT_rabc_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
- wire width 1 \rdpick_INT_rbc_en_o
- cell \rdpick_INT_rbc \rdpick_INT_rbc
- connect \i \rdpick_INT_rbc_i
- connect \o \rdpick_INT_rbc_o
- connect \en_o \rdpick_INT_rbc_en_o
+ wire width 1 \rdpick_INT_rabc_en_o
+ cell \rdpick_INT_rabc \rdpick_INT_rabc
+ connect \i \rdpick_INT_rabc_i
+ connect \o \rdpick_INT_rabc_o
+ connect \en_o \rdpick_INT_rabc_en_o
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 4 \rdpick_XER_xer_so_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
wire width 1 \en_alu0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- wire width 1 $158
+ wire width 1 $159
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- wire width 11 $159
+ wire width 11 $160
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- cell $and $160
+ cell $and $161
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \B_SIGNED 0
parameter \Y_WIDTH 11
connect \A \pdecode2_fn_unit
connect \B 2'10
- connect \Y $159
+ connect \Y $160
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- cell $reduce_bool $161
+ cell $reduce_bool $162
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \Y_WIDTH 1
- connect \A $159
- connect \Y $158
+ connect \A $160
+ connect \Y $159
end
process $group_0
assign \en_alu0 1'0
- assign \en_alu0 $158
+ assign \en_alu0 $159
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:130"
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- wire width 1 $162
+ wire width 1 $163
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- wire width 11 $163
+ wire width 11 $164
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- cell $and $164
+ cell $and $165
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \B_SIGNED 0
parameter \Y_WIDTH 11
connect \A \pdecode2_fn_unit
connect \B 7'1000000
- connect \Y $163
+ connect \Y $164
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- cell $reduce_bool $165
+ cell $reduce_bool $166
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \Y_WIDTH 1
- connect \A $163
- connect \Y $162
+ connect \A $164
+ connect \Y $163
end
process $group_2
assign \en_cr0 1'0
- assign \en_cr0 $162
+ assign \en_cr0 $163
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- wire width 1 $166
+ wire width 1 $167
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- wire width 11 $167
+ wire width 11 $168
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- cell $and $168
+ cell $and $169
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \B_SIGNED 0
parameter \Y_WIDTH 11
connect \A \pdecode2_fn_unit
connect \B 6'100000
- connect \Y $167
+ connect \Y $168
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- cell $reduce_bool $169
+ cell $reduce_bool $170
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \Y_WIDTH 1
- connect \A $167
- connect \Y $166
+ connect \A $168
+ connect \Y $167
end
process $group_3
assign \en_branch0 1'0
- assign \en_branch0 $166
+ assign \en_branch0 $167
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- wire width 1 $170
+ wire width 1 $171
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- wire width 11 $171
+ wire width 11 $172
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- cell $and $172
+ cell $and $173
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \B_SIGNED 0
parameter \Y_WIDTH 11
connect \A \pdecode2_fn_unit
connect \B 8'10000000
- connect \Y $171
+ connect \Y $172
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- cell $reduce_bool $173
+ cell $reduce_bool $174
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \Y_WIDTH 1
- connect \A $171
- connect \Y $170
+ connect \A $172
+ connect \Y $171
end
process $group_4
assign \en_trap0 1'0
- assign \en_trap0 $170
+ assign \en_trap0 $171
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- wire width 1 $174
+ wire width 1 $175
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- wire width 11 $175
+ wire width 11 $176
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- cell $and $176
+ cell $and $177
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \B_SIGNED 0
parameter \Y_WIDTH 11
connect \A \pdecode2_fn_unit
connect \B 5'10000
- connect \Y $175
+ connect \Y $176
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- cell $reduce_bool $177
+ cell $reduce_bool $178
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \Y_WIDTH 1
- connect \A $175
- connect \Y $174
+ connect \A $176
+ connect \Y $175
end
process $group_5
assign \en_logical0 1'0
- assign \en_logical0 $174
+ assign \en_logical0 $175
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- wire width 1 $178
+ wire width 1 $179
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- wire width 11 $179
+ wire width 11 $180
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- cell $and $180
+ cell $and $181
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \B_SIGNED 0
parameter \Y_WIDTH 11
connect \A \pdecode2_fn_unit
connect \B 11'10000000000
- connect \Y $179
+ connect \Y $180
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- cell $reduce_bool $181
+ cell $reduce_bool $182
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \Y_WIDTH 1
- connect \A $179
- connect \Y $178
+ connect \A $180
+ connect \Y $179
end
process $group_6
assign \en_spr0 1'0
- assign \en_spr0 $178
+ assign \en_spr0 $179
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- wire width 1 $182
+ wire width 1 $183
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- wire width 11 $183
+ wire width 11 $184
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- cell $and $184
+ cell $and $185
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \B_SIGNED 0
parameter \Y_WIDTH 11
connect \A \pdecode2_fn_unit
connect \B 10'1000000000
- connect \Y $183
+ connect \Y $184
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- cell $reduce_bool $185
+ cell $reduce_bool $186
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \Y_WIDTH 1
- connect \A $183
- connect \Y $182
+ connect \A $184
+ connect \Y $183
end
process $group_7
assign \en_div0 1'0
- assign \en_div0 $182
+ assign \en_div0 $183
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- wire width 1 $186
+ wire width 1 $187
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- wire width 11 $187
+ wire width 11 $188
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- cell $and $188
+ cell $and $189
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \B_SIGNED 0
parameter \Y_WIDTH 11
connect \A \pdecode2_fn_unit
connect \B 9'100000000
- connect \Y $187
+ connect \Y $188
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- cell $reduce_bool $189
+ cell $reduce_bool $190
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \Y_WIDTH 1
- connect \A $187
- connect \Y $186
+ connect \A $188
+ connect \Y $187
end
process $group_8
assign \en_mul0 1'0
- assign \en_mul0 $186
+ assign \en_mul0 $187
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- wire width 1 $190
+ wire width 1 $191
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- wire width 11 $191
+ wire width 11 $192
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- cell $and $192
+ cell $and $193
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \B_SIGNED 0
parameter \Y_WIDTH 11
connect \A \pdecode2_fn_unit
connect \B 4'1000
- connect \Y $191
+ connect \Y $192
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- cell $reduce_bool $193
+ cell $reduce_bool $194
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \Y_WIDTH 1
- connect \A $191
- connect \Y $190
+ connect \A $192
+ connect \Y $191
end
process $group_9
assign \en_shiftrot0 1'0
- assign \en_shiftrot0 $190
+ assign \en_shiftrot0 $191
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- wire width 1 $194
+ wire width 1 $195
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- wire width 11 $195
+ wire width 11 $196
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- cell $and $196
+ cell $and $197
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \B_SIGNED 0
parameter \Y_WIDTH 11
connect \A \pdecode2_fn_unit
connect \B 3'100
- connect \Y $195
+ connect \Y $196
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
- cell $reduce_bool $197
+ cell $reduce_bool $198
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \Y_WIDTH 1
- connect \A $195
- connect \Y $194
+ connect \A $196
+ connect \Y $195
end
process $group_10
assign \en_ldst0 1'0
- assign \en_ldst0 $194
+ assign \en_ldst0 $195
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:145"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:145"
wire width 2 \counter$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146"
- wire width 1 $198
+ wire width 1 $199
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146"
- cell $ne $199
+ cell $ne $200
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \counter
connect \B 1'0
- connect \Y $198
+ connect \Y $199
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
- wire width 3 $200
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
wire width 3 $201
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
- cell $sub $202
+ wire width 3 $202
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+ cell $sub $203
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \counter
connect \B 1'1
- connect \Y $201
+ connect \Y $202
end
- connect $200 $201
+ connect $201 $202
process $group_11
assign \counter$next \counter
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146"
- switch { $198 }
+ switch { $199 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146"
case 1'1
- assign \counter$next $200 [1:0]
+ assign \counter$next $201 [1:0]
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
switch { \valid }
update \counter \counter$next
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146"
- wire width 1 $203
+ wire width 1 $204
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146"
- cell $ne $204
+ cell $ne $205
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \counter
connect \B 1'0
- connect \Y $203
+ connect \Y $204
end
process $group_12
assign \corebusy_o 1'0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146"
- switch { $203 }
+ switch { $204 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146"
case 1'1
assign \corebusy_o 1'1
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
- wire width 4 $205
+ wire width 4 $206
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
- wire width 1 $206
+ wire width 1 $207
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
- cell $and $207
+ cell $and $208
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pdecode2_oe
connect \B \pdecode2_oe_ok
- connect \Y $206
+ connect \Y $207
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
- wire width 1 $208
+ wire width 1 $209
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
- cell $or $209
+ cell $or $210
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $206
+ connect \A $207
connect \B \pdecode2_xer_in
- connect \Y $208
+ connect \Y $209
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
- wire width 1 $210
+ wire width 1 $211
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
- cell $eq $211
+ cell $eq $212
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pdecode2_input_carry
connect \B 2'10
- connect \Y $210
+ connect \Y $211
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
- wire width 1 $212
+ wire width 1 $213
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
- cell $or $213
+ cell $or $214
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $210
+ connect \A $211
connect \B \pdecode2_xer_in
- connect \Y $212
+ connect \Y $213
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
- cell $not $214
+ cell $not $215
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
- connect \A { $212 $208 \pdecode2_reg2_ok \pdecode2_reg1_ok }
- connect \Y $205
+ connect \A { $213 $209 \pdecode2_reg2_ok \pdecode2_reg1_ok }
+ connect \Y $206
end
process $group_33
assign \fus_cu_rdmaskn_i 4'0000
switch { \fu_enable [0] }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
case 1'1
- assign \fus_cu_rdmaskn_i $205
+ assign \fus_cu_rdmaskn_i $206
end
end
end
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
- wire width 6 $215
+ wire width 6 $216
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
- cell $not $216
+ cell $not $217
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A { \pdecode2_cr_in2_ok$1 \pdecode2_cr_in2_ok \pdecode2_cr_in1_ok \pdecode2_read_cr_whole \pdecode2_reg2_ok \pdecode2_reg1_ok }
- connect \Y $215
+ connect \Y $216
end
process $group_40
assign \fus_cu_rdmaskn_i$5 6'000000
switch { \fu_enable [1] }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
case 1'1
- assign \fus_cu_rdmaskn_i$5 $215
+ assign \fus_cu_rdmaskn_i$5 $216
end
end
end
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
- wire width 3 $217
+ wire width 3 $218
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
- cell $not $218
+ cell $not $219
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A { \pdecode2_cr_in1_ok \pdecode2_fast2_ok \pdecode2_fast1_ok }
- connect \Y $217
+ connect \Y $218
end
process $group_50
assign \fus_cu_rdmaskn_i$8 3'000
switch { \fu_enable [2] }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
case 1'1
- assign \fus_cu_rdmaskn_i$8 $217
+ assign \fus_cu_rdmaskn_i$8 $218
end
end
end
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
- wire width 4 $219
+ wire width 4 $220
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
- cell $not $220
+ cell $not $221
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A { \pdecode2_fast2_ok \pdecode2_fast1_ok \pdecode2_reg2_ok \pdecode2_reg1_ok }
- connect \Y $219
+ connect \Y $220
end
process $group_60
assign \fus_cu_rdmaskn_i$11 4'0000
switch { \fu_enable [3] }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
case 1'1
- assign \fus_cu_rdmaskn_i$11 $219
+ assign \fus_cu_rdmaskn_i$11 $220
end
end
end
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
- wire width 2 $221
+ wire width 2 $222
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
- cell $not $222
+ cell $not $223
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A { \pdecode2_reg2_ok \pdecode2_reg1_ok }
- connect \Y $221
+ connect \Y $222
end
process $group_80
assign \fus_cu_rdmaskn_i$14 2'00
switch { \fu_enable [4] }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
case 1'1
- assign \fus_cu_rdmaskn_i$14 $221
+ assign \fus_cu_rdmaskn_i$14 $222
end
end
end
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
- wire width 6 $223
+ wire width 6 $224
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
- wire width 1 $224
+ wire width 1 $225
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
- cell $and $225
+ cell $and $226
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pdecode2_oe
connect \B \pdecode2_oe_ok
- connect \Y $224
+ connect \Y $225
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
- wire width 1 $226
+ wire width 1 $227
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
- cell $or $227
+ cell $or $228
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $224
+ connect \A $225
connect \B \pdecode2_xer_in
- connect \Y $226
+ connect \Y $227
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
- wire width 1 $228
+ wire width 1 $229
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
- cell $and $229
+ cell $and $230
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pdecode2_oe
connect \B \pdecode2_oe_ok
- connect \Y $228
+ connect \Y $229
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
- wire width 1 $230
+ wire width 1 $231
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
- cell $or $231
+ cell $or $232
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $228
+ connect \A $229
connect \B \pdecode2_xer_in
- connect \Y $230
+ connect \Y $231
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
- wire width 1 $232
+ wire width 1 $233
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
- cell $eq $233
+ cell $eq $234
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pdecode2_input_carry
connect \B 2'10
- connect \Y $232
+ connect \Y $233
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
- wire width 1 $234
+ wire width 1 $235
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
- cell $or $235
+ cell $or $236
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $232
+ connect \A $233
connect \B \pdecode2_xer_in
- connect \Y $234
+ connect \Y $235
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
- cell $not $236
+ cell $not $237
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
- connect \A { $234 $230 $226 \pdecode2_fast1_ok \pdecode2_spr1_ok \pdecode2_reg1_ok }
- connect \Y $223
+ connect \A { $235 $231 $227 \pdecode2_fast1_ok \pdecode2_spr1_ok \pdecode2_reg1_ok }
+ connect \Y $224
end
process $group_86
assign \fus_cu_rdmaskn_i$17 6'000000
switch { \fu_enable [5] }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
case 1'1
- assign \fus_cu_rdmaskn_i$17 $223
+ assign \fus_cu_rdmaskn_i$17 $224
end
end
end
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
- wire width 3 $237
+ wire width 3 $238
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
- wire width 1 $238
+ wire width 1 $239
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
- cell $and $239
+ cell $and $240
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pdecode2_oe
connect \B \pdecode2_oe_ok
- connect \Y $238
+ connect \Y $239
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
- wire width 1 $240
+ wire width 1 $241
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
- cell $or $241
+ cell $or $242
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $238
+ connect \A $239
connect \B \pdecode2_xer_in
- connect \Y $240
+ connect \Y $241
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
- cell $not $242
+ cell $not $243
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
- connect \A { $240 \pdecode2_reg2_ok \pdecode2_reg1_ok }
- connect \Y $237
+ connect \A { $241 \pdecode2_reg2_ok \pdecode2_reg1_ok }
+ connect \Y $238
end
process $group_106
assign \fus_cu_rdmaskn_i$20 3'000
switch { \fu_enable [6] }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
case 1'1
- assign \fus_cu_rdmaskn_i$20 $237
+ assign \fus_cu_rdmaskn_i$20 $238
end
end
end
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
- wire width 3 $243
+ wire width 3 $244
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
- wire width 1 $244
+ wire width 1 $245
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
- cell $and $245
+ cell $and $246
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pdecode2_oe
connect \B \pdecode2_oe_ok
- connect \Y $244
+ connect \Y $245
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
- wire width 1 $246
+ wire width 1 $247
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
- cell $or $247
+ cell $or $248
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $244
+ connect \A $245
connect \B \pdecode2_xer_in
- connect \Y $246
+ connect \Y $247
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
- cell $not $248
+ cell $not $249
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
- connect \A { $246 \pdecode2_reg2_ok \pdecode2_reg1_ok }
- connect \Y $243
+ connect \A { $247 \pdecode2_reg2_ok \pdecode2_reg1_ok }
+ connect \Y $244
end
process $group_123
assign \fus_cu_rdmaskn_i$23 3'000
switch { \fu_enable [7] }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
case 1'1
- assign \fus_cu_rdmaskn_i$23 $243
+ assign \fus_cu_rdmaskn_i$23 $244
end
end
end
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
- wire width 4 $249
+ wire width 4 $250
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
- wire width 1 $250
+ wire width 1 $251
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
- cell $eq $251
+ cell $eq $252
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pdecode2_input_carry
connect \B 2'10
- connect \Y $250
+ connect \Y $251
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
- wire width 1 $252
+ wire width 1 $253
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
- cell $or $253
+ cell $or $254
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $250
+ connect \A $251
connect \B \pdecode2_xer_in
- connect \Y $252
+ connect \Y $253
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
- cell $not $254
+ cell $not $255
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
- connect \A { $252 \pdecode2_reg3_ok \pdecode2_reg2_ok \pdecode2_reg1_ok }
- connect \Y $249
+ connect \A { $253 \pdecode2_reg3_ok \pdecode2_reg2_ok \pdecode2_reg1_ok }
+ connect \Y $250
end
process $group_141
assign \fus_cu_rdmaskn_i$26 4'0000
switch { \fu_enable [8] }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
case 1'1
- assign \fus_cu_rdmaskn_i$26 $249
+ assign \fus_cu_rdmaskn_i$26 $250
end
end
end
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
- wire width 3 $255
+ wire width 3 $256
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
- cell $not $256
+ cell $not $257
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A { \pdecode2_reg3_ok \pdecode2_reg2_ok \pdecode2_reg1_ok }
- connect \Y $255
+ connect \Y $256
end
process $group_157
assign \fus_cu_rdmaskn_i$29 3'000
switch { \fu_enable [9] }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
case 1'1
- assign \fus_cu_rdmaskn_i$29 $255
+ assign \fus_cu_rdmaskn_i$29 $256
end
end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
- wire width 1 \rdflag_INT_ra_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204"
+ wire width 1 \rdflag_INT_rabc_0
process $group_158
- assign \rdflag_INT_ra_0 1'0
- assign \rdflag_INT_ra_0 \pdecode2_reg1_ok
+ assign \rdflag_INT_rabc_0 1'0
+ assign \rdflag_INT_rabc_0 \pdecode2_reg2_ok
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204"
+ wire width 1 \rdflag_INT_rabc_1
+ process $group_159
+ assign \rdflag_INT_rabc_1 1'0
+ assign \rdflag_INT_rabc_1 \pdecode2_reg3_ok
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204"
+ wire width 1 \rdflag_INT_rabc_2
+ process $group_160
+ assign \rdflag_INT_rabc_2 1'0
+ assign \rdflag_INT_rabc_2 \pdecode2_reg1_ok
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
wire width 1 \pick
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $257
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $258
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $258
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $259
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o [0]
+ connect \A \fus_cu_rd__rel_o [1]
connect \B \fu_enable [0]
- connect \Y $257
+ connect \Y $258
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $259
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $260
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $260
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $261
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $257
- connect \B \rdflag_INT_ra_0
- connect \Y $259
+ connect \A $258
+ connect \B \rdflag_INT_rabc_0
+ connect \Y $260
end
- process $group_159
+ process $group_161
assign \pick 1'0
- assign \pick $259
+ assign \pick $260
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$261
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
wire width 1 \pick$262
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
wire width 1 \pick$263
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
wire width 1 \pick$264
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
wire width 1 \pick$265
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
wire width 1 \pick$266
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
wire width 1 \pick$267
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
wire width 1 \pick$268
- process $group_160
- assign \rdpick_INT_ra_i 9'000000000
- assign \rdpick_INT_ra_i [0] \pick
- assign \rdpick_INT_ra_i [1] \pick$261
- assign \rdpick_INT_ra_i [2] \pick$262
- assign \rdpick_INT_ra_i [3] \pick$263
- assign \rdpick_INT_ra_i [4] \pick$264
- assign \rdpick_INT_ra_i [5] \pick$265
- assign \rdpick_INT_ra_i [6] \pick$266
- assign \rdpick_INT_ra_i [7] \pick$267
- assign \rdpick_INT_ra_i [8] \pick$268
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$269
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$270
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$271
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$272
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$273
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$274
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$275
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$276
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$277
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$278
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$279
+ process $group_162
+ assign \rdpick_INT_rabc_i 19'0000000000000000000
+ assign \rdpick_INT_rabc_i [0] \pick
+ assign \rdpick_INT_rabc_i [1] \pick$262
+ assign \rdpick_INT_rabc_i [2] \pick$263
+ assign \rdpick_INT_rabc_i [3] \pick$264
+ assign \rdpick_INT_rabc_i [4] \pick$265
+ assign \rdpick_INT_rabc_i [5] \pick$266
+ assign \rdpick_INT_rabc_i [6] \pick$267
+ assign \rdpick_INT_rabc_i [7] \pick$268
+ assign \rdpick_INT_rabc_i [8] \pick$269
+ assign \rdpick_INT_rabc_i [9] \pick$270
+ assign \rdpick_INT_rabc_i [10] \pick$271
+ assign \rdpick_INT_rabc_i [11] \pick$272
+ assign \rdpick_INT_rabc_i [12] \pick$273
+ assign \rdpick_INT_rabc_i [13] \pick$274
+ assign \rdpick_INT_rabc_i [14] \pick$275
+ assign \rdpick_INT_rabc_i [15] \pick$276
+ assign \rdpick_INT_rabc_i [16] \pick$277
+ assign \rdpick_INT_rabc_i [17] \pick$278
+ assign \rdpick_INT_rabc_i [18] \pick$279
sync init
end
- process $group_161
+ process $group_163
assign \fus_cu_rd__go_i 4'0000
- assign \fus_cu_rd__go_i [0] \rdpick_INT_ra_o [0]
- assign \fus_cu_rd__go_i [1] \rdpick_INT_rbc_o [0]
+ assign \fus_cu_rd__go_i [1] \rdpick_INT_rabc_o [0]
+ assign \fus_cu_rd__go_i [0] \rdpick_INT_rabc_o [10]
assign \fus_cu_rd__go_i [2] \rdpick_XER_xer_so_o [0]
assign \fus_cu_rd__go_i [3] \rdpick_XER_xer_ca_o [0]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 32 \read_en
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
- wire width 32 $269
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
- cell $sshl $270
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_reg1
- connect \Y $269
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 32 $271
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $272
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $273
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_INT_rabc_alu0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $280
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $281
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [0]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $272
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $274
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $269
- connect \S $272
- connect \Y $271
+ connect \A \rdpick_INT_rabc_o [0]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $280
end
- process $group_162
- assign \read_en 32'00000000000000000000000000000000
- assign \read_en $271
+ process $group_164
+ assign \rp_INT_rabc_alu0_0 1'0
+ assign \rp_INT_rabc_alu0_0 $280
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $275
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $276
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [0]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $275
+ wire width 5 \addr_en_INT_rabc_alu0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 5 $282
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $283
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_reg2
+ connect \S \rp_INT_rabc_alu0_0
+ connect \Y $282
end
- process $group_163
- assign \fus_src1_i 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $275 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ process $group_165
+ assign \addr_en_INT_rabc_alu0_0 5'00000
+ assign \addr_en_INT_rabc_alu0_0 $282
+ sync init
+ end
+ process $group_166
+ assign \fus_src2_i 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_INT_rabc_alu0_0 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
- assign \fus_src1_i \int_src1__data_o
+ assign \fus_src2_i \int_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $277
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $278
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $284
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $285
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$30 [0]
+ connect \A \fus_cu_rd__rel_o$30 [1]
connect \B \fu_enable [1]
- connect \Y $277
+ connect \Y $284
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $279
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $280
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $286
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $287
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $277
- connect \B \rdflag_INT_ra_0
- connect \Y $279
+ connect \A $284
+ connect \B \rdflag_INT_rabc_0
+ connect \Y $286
end
- process $group_164
- assign \pick$261 1'0
- assign \pick$261 $279
+ process $group_167
+ assign \pick$262 1'0
+ assign \pick$262 $286
sync init
end
- process $group_165
+ process $group_168
assign \fus_cu_rd__go_i$31 6'000000
- assign \fus_cu_rd__go_i$31 [0] \rdpick_INT_ra_o [1]
- assign \fus_cu_rd__go_i$31 [1] \rdpick_INT_rbc_o [1]
+ assign \fus_cu_rd__go_i$31 [1] \rdpick_INT_rabc_o [1]
+ assign \fus_cu_rd__go_i$31 [0] \rdpick_INT_rabc_o [11]
assign \fus_cu_rd__go_i$31 [2] \rdpick_CR_full_cr_o
assign \fus_cu_rd__go_i$31 [3] \rdpick_CR_cr_a_o [0]
assign \fus_cu_rd__go_i$31 [4] \rdpick_CR_cr_b_o
assign \fus_cu_rd__go_i$31 [5] \rdpick_CR_cr_c_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 32 \read_en$281
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
- wire width 32 $282
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
- cell $sshl $283
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_reg1
- connect \Y $282
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 32 $284
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $285
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $286
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [1]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $285
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $287
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $282
- connect \S $285
- connect \Y $284
- end
- process $group_166
- assign \read_en$281 32'00000000000000000000000000000000
- assign \read_en$281 $284
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_INT_rabc_cr0_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
wire width 1 $288
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
cell $and $289
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [1]
- connect \B \rdpick_INT_ra_en_o
+ connect \A \rdpick_INT_rabc_o [1]
+ connect \B \rdpick_INT_rabc_en_o
connect \Y $288
end
- process $group_167
- assign \fus_src1_i$32 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $288 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- case 1'1
- assign \fus_src1_i$32 \int_src1__data_o
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $290
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $291
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$33 [0]
- connect \B \fu_enable [3]
- connect \Y $290
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $292
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $293
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $290
- connect \B \rdflag_INT_ra_0
- connect \Y $292
- end
- process $group_168
- assign \pick$262 1'0
- assign \pick$262 $292
- sync init
- end
process $group_169
- assign \fus_cu_rd__go_i$34 4'0000
- assign \fus_cu_rd__go_i$34 [0] \rdpick_INT_ra_o [2]
- assign \fus_cu_rd__go_i$34 [1] \rdpick_INT_rbc_o [2]
- assign \fus_cu_rd__go_i$34 [2] \rdpick_FAST_fast1_o [1]
- assign \fus_cu_rd__go_i$34 [3] \rdpick_FAST_fast1_o [4]
+ assign \rp_INT_rabc_cr0_1 1'0
+ assign \rp_INT_rabc_cr0_1 $288
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 32 \read_en$294
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
- wire width 32 $295
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
- cell $sshl $296
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_reg1
- connect \Y $295
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 32 $297
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $298
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $299
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [2]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $298
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $300
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $295
- connect \S $298
- connect \Y $297
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 5 \addr_en_INT_rabc_cr0_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 5 $290
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $291
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_reg2
+ connect \S \rp_INT_rabc_cr0_1
+ connect \Y $290
end
process $group_170
- assign \read_en$294 32'00000000000000000000000000000000
- assign \read_en$294 $297
+ assign \addr_en_INT_rabc_cr0_1 5'00000
+ assign \addr_en_INT_rabc_cr0_1 $290
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $301
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $302
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [2]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $301
- end
process $group_171
- assign \fus_src1_i$35 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $301 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ assign \fus_src2_i$32 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_INT_rabc_cr0_1 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
- assign \fus_src1_i$35 \int_src1__data_o
+ assign \fus_src2_i$32 \int_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $303
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $304
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $292
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $293
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$36 [0]
- connect \B \fu_enable [4]
- connect \Y $303
+ connect \A \fus_cu_rd__rel_o$33 [1]
+ connect \B \fu_enable [3]
+ connect \Y $292
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $305
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $306
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $294
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $295
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $303
- connect \B \rdflag_INT_ra_0
- connect \Y $305
+ connect \A $292
+ connect \B \rdflag_INT_rabc_0
+ connect \Y $294
end
process $group_172
assign \pick$263 1'0
- assign \pick$263 $305
+ assign \pick$263 $294
sync init
end
process $group_173
- assign \fus_cu_rd__go_i$37 2'00
- assign \fus_cu_rd__go_i$37 [0] \rdpick_INT_ra_o [3]
- assign \fus_cu_rd__go_i$37 [1] \rdpick_INT_rbc_o [3]
+ assign \fus_cu_rd__go_i$34 4'0000
+ assign \fus_cu_rd__go_i$34 [1] \rdpick_INT_rabc_o [2]
+ assign \fus_cu_rd__go_i$34 [0] \rdpick_INT_rabc_o [12]
+ assign \fus_cu_rd__go_i$34 [2] \rdpick_FAST_fast1_o [1]
+ assign \fus_cu_rd__go_i$34 [3] \rdpick_FAST_fast1_o [4]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 32 \read_en$307
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
- wire width 32 $308
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
- cell $sshl $309
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_reg1
- connect \Y $308
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 32 $310
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $311
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $312
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_INT_rabc_trap0_2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $296
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $297
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [3]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $311
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $313
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $308
- connect \S $311
- connect \Y $310
+ connect \A \rdpick_INT_rabc_o [2]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $296
end
process $group_174
- assign \read_en$307 32'00000000000000000000000000000000
- assign \read_en$307 $310
+ assign \rp_INT_rabc_trap0_2 1'0
+ assign \rp_INT_rabc_trap0_2 $296
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $314
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $315
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [3]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $314
+ wire width 5 \addr_en_INT_rabc_trap0_2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 5 $298
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $299
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_reg2
+ connect \S \rp_INT_rabc_trap0_2
+ connect \Y $298
end
process $group_175
- assign \fus_src1_i$38 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $314 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ assign \addr_en_INT_rabc_trap0_2 5'00000
+ assign \addr_en_INT_rabc_trap0_2 $298
+ sync init
+ end
+ process $group_176
+ assign \fus_src2_i$35 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_INT_rabc_trap0_2 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
- assign \fus_src1_i$38 \int_src1__data_o
+ assign \fus_src2_i$35 \int_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $316
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $317
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $300
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $301
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$39 [0]
- connect \B \fu_enable [5]
- connect \Y $316
+ connect \A \fus_cu_rd__rel_o$36 [1]
+ connect \B \fu_enable [4]
+ connect \Y $300
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $318
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $319
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $302
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $303
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $316
- connect \B \rdflag_INT_ra_0
- connect \Y $318
+ connect \A $300
+ connect \B \rdflag_INT_rabc_0
+ connect \Y $302
end
- process $group_176
+ process $group_177
assign \pick$264 1'0
- assign \pick$264 $318
+ assign \pick$264 $302
sync init
end
- process $group_177
- assign \fus_cu_rd__go_i$40 6'000000
- assign \fus_cu_rd__go_i$40 [0] \rdpick_INT_ra_o [4]
- assign \fus_cu_rd__go_i$40 [3] \rdpick_XER_xer_so_o [1]
- assign \fus_cu_rd__go_i$40 [5] \rdpick_XER_xer_ca_o [1]
- assign \fus_cu_rd__go_i$40 [4] \rdpick_XER_xer_ov_o
- assign \fus_cu_rd__go_i$40 [2] \rdpick_FAST_fast1_o [2]
- assign \fus_cu_rd__go_i$40 [1] \rdpick_SPR_spr1_o
+ process $group_178
+ assign \fus_cu_rd__go_i$37 2'00
+ assign \fus_cu_rd__go_i$37 [1] \rdpick_INT_rabc_o [3]
+ assign \fus_cu_rd__go_i$37 [0] \rdpick_INT_rabc_o [13]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 32 \read_en$320
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
- wire width 32 $321
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
- cell $sshl $322
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_reg1
- connect \Y $321
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 32 $323
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $324
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $325
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_INT_rabc_logical0_3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $304
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $305
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [4]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $324
+ connect \A \rdpick_INT_rabc_o [3]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $304
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $326
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $321
- connect \S $324
- connect \Y $323
- end
- process $group_178
- assign \read_en$320 32'00000000000000000000000000000000
- assign \read_en$320 $323
+ process $group_179
+ assign \rp_INT_rabc_logical0_3 1'0
+ assign \rp_INT_rabc_logical0_3 $304
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $327
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $328
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [4]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $327
+ wire width 5 \addr_en_INT_rabc_logical0_3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 5 $306
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $307
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_reg2
+ connect \S \rp_INT_rabc_logical0_3
+ connect \Y $306
end
- process $group_179
- assign \fus_src1_i$41 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $327 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ process $group_180
+ assign \addr_en_INT_rabc_logical0_3 5'00000
+ assign \addr_en_INT_rabc_logical0_3 $306
+ sync init
+ end
+ process $group_181
+ assign \fus_src2_i$38 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_INT_rabc_logical0_3 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
- assign \fus_src1_i$41 \int_src1__data_o
+ assign \fus_src2_i$38 \int_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $329
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $330
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $308
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $309
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$42 [0]
+ connect \A \fus_cu_rd__rel_o$39 [1]
connect \B \fu_enable [6]
- connect \Y $329
+ connect \Y $308
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $331
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $332
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $310
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $311
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $329
- connect \B \rdflag_INT_ra_0
- connect \Y $331
+ connect \A $308
+ connect \B \rdflag_INT_rabc_0
+ connect \Y $310
end
- process $group_180
+ process $group_182
assign \pick$265 1'0
- assign \pick$265 $331
+ assign \pick$265 $310
sync init
end
- process $group_181
- assign \fus_cu_rd__go_i$43 3'000
- assign \fus_cu_rd__go_i$43 [0] \rdpick_INT_ra_o [5]
- assign \fus_cu_rd__go_i$43 [1] \rdpick_INT_rbc_o [4]
- assign \fus_cu_rd__go_i$43 [2] \rdpick_XER_xer_so_o [2]
+ process $group_183
+ assign \fus_cu_rd__go_i$40 3'000
+ assign \fus_cu_rd__go_i$40 [1] \rdpick_INT_rabc_o [4]
+ assign \fus_cu_rd__go_i$40 [0] \rdpick_INT_rabc_o [15]
+ assign \fus_cu_rd__go_i$40 [2] \rdpick_XER_xer_so_o [2]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 32 \read_en$333
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
- wire width 32 $334
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
- cell $sshl $335
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_reg1
- connect \Y $334
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 32 $336
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $337
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $338
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_INT_rabc_div0_4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $312
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $313
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [5]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $337
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $339
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $334
- connect \S $337
- connect \Y $336
+ connect \A \rdpick_INT_rabc_o [4]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $312
end
- process $group_182
- assign \read_en$333 32'00000000000000000000000000000000
- assign \read_en$333 $336
+ process $group_184
+ assign \rp_INT_rabc_div0_4 1'0
+ assign \rp_INT_rabc_div0_4 $312
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $340
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $341
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [5]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $340
+ wire width 5 \addr_en_INT_rabc_div0_4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 5 $314
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $315
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_reg2
+ connect \S \rp_INT_rabc_div0_4
+ connect \Y $314
end
- process $group_183
- assign \fus_src1_i$44 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $340 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ process $group_185
+ assign \addr_en_INT_rabc_div0_4 5'00000
+ assign \addr_en_INT_rabc_div0_4 $314
+ sync init
+ end
+ process $group_186
+ assign \fus_src2_i$41 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_INT_rabc_div0_4 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
- assign \fus_src1_i$44 \int_src1__data_o
+ assign \fus_src2_i$41 \int_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $342
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $343
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $316
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $317
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$45 [0]
+ connect \A \fus_cu_rd__rel_o$42 [1]
connect \B \fu_enable [7]
- connect \Y $342
+ connect \Y $316
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $344
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $345
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $318
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $319
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $342
- connect \B \rdflag_INT_ra_0
- connect \Y $344
+ connect \A $316
+ connect \B \rdflag_INT_rabc_0
+ connect \Y $318
end
- process $group_184
+ process $group_187
assign \pick$266 1'0
- assign \pick$266 $344
+ assign \pick$266 $318
sync init
end
- process $group_185
- assign \fus_cu_rd__go_i$46 3'000
- assign \fus_cu_rd__go_i$46 [0] \rdpick_INT_ra_o [6]
- assign \fus_cu_rd__go_i$46 [1] \rdpick_INT_rbc_o [5]
- assign \fus_cu_rd__go_i$46 [2] \rdpick_XER_xer_so_o [3]
+ process $group_188
+ assign \fus_cu_rd__go_i$43 3'000
+ assign \fus_cu_rd__go_i$43 [1] \rdpick_INT_rabc_o [5]
+ assign \fus_cu_rd__go_i$43 [0] \rdpick_INT_rabc_o [16]
+ assign \fus_cu_rd__go_i$43 [2] \rdpick_XER_xer_so_o [3]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 32 \read_en$346
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
- wire width 32 $347
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
- cell $sshl $348
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_reg1
- connect \Y $347
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 32 $349
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $350
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $351
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_INT_rabc_mul0_5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $320
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $321
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [6]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $350
+ connect \A \rdpick_INT_rabc_o [5]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $320
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $352
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $347
- connect \S $350
- connect \Y $349
- end
- process $group_186
- assign \read_en$346 32'00000000000000000000000000000000
- assign \read_en$346 $349
+ process $group_189
+ assign \rp_INT_rabc_mul0_5 1'0
+ assign \rp_INT_rabc_mul0_5 $320
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $353
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $354
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [6]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $353
+ wire width 5 \addr_en_INT_rabc_mul0_5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 5 $322
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $323
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_reg2
+ connect \S \rp_INT_rabc_mul0_5
+ connect \Y $322
end
- process $group_187
- assign \fus_src1_i$47 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $353 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ process $group_190
+ assign \addr_en_INT_rabc_mul0_5 5'00000
+ assign \addr_en_INT_rabc_mul0_5 $322
+ sync init
+ end
+ process $group_191
+ assign \fus_src2_i$44 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_INT_rabc_mul0_5 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
- assign \fus_src1_i$47 \int_src1__data_o
+ assign \fus_src2_i$44 \int_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $355
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $356
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $324
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $325
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$48 [0]
+ connect \A \fus_cu_rd__rel_o$45 [1]
connect \B \fu_enable [8]
- connect \Y $355
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $357
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $358
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $355
- connect \B \rdflag_INT_ra_0
- connect \Y $357
- end
- process $group_188
- assign \pick$267 1'0
- assign \pick$267 $357
- sync init
- end
- process $group_189
- assign \fus_cu_rd__go_i$49 4'0000
- assign \fus_cu_rd__go_i$49 [0] \rdpick_INT_ra_o [7]
- assign \fus_cu_rd__go_i$49 [1] \rdpick_INT_rbc_o [6]
- assign \fus_cu_rd__go_i$49 [2] \rdpick_INT_rbc_o [8]
- assign \fus_cu_rd__go_i$49 [3] \rdpick_XER_xer_ca_o [2]
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 32 \read_en$359
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
- wire width 32 $360
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
- cell $sshl $361
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_reg1
- connect \Y $360
+ connect \Y $324
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 32 $362
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $363
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $364
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $326
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $327
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [7]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $363
+ connect \A $324
+ connect \B \rdflag_INT_rabc_0
+ connect \Y $326
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $365
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $360
- connect \S $363
- connect \Y $362
+ process $group_192
+ assign \pick$267 1'0
+ assign \pick$267 $326
+ sync init
end
- process $group_190
- assign \read_en$359 32'00000000000000000000000000000000
- assign \read_en$359 $362
+ process $group_193
+ assign \fus_cu_rd__go_i$46 4'0000
+ assign \fus_cu_rd__go_i$46 [1] \rdpick_INT_rabc_o [6]
+ assign \fus_cu_rd__go_i$46 [2] \rdpick_INT_rabc_o [8]
+ assign \fus_cu_rd__go_i$46 [0] \rdpick_INT_rabc_o [17]
+ assign \fus_cu_rd__go_i$46 [3] \rdpick_XER_xer_ca_o [2]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $366
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $367
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_INT_rabc_shiftrot0_6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $328
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $329
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [7]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $366
+ connect \A \rdpick_INT_rabc_o [6]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $328
end
- process $group_191
- assign \fus_src1_i$50 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $366 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ process $group_194
+ assign \rp_INT_rabc_shiftrot0_6 1'0
+ assign \rp_INT_rabc_shiftrot0_6 $328
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 5 \addr_en_INT_rabc_shiftrot0_6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 5 $330
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $331
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_reg2
+ connect \S \rp_INT_rabc_shiftrot0_6
+ connect \Y $330
+ end
+ process $group_195
+ assign \addr_en_INT_rabc_shiftrot0_6 5'00000
+ assign \addr_en_INT_rabc_shiftrot0_6 $330
+ sync init
+ end
+ process $group_196
+ assign \fus_src2_i$47 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_INT_rabc_shiftrot0_6 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
- assign \fus_src1_i$50 \int_src1__data_o
+ assign \fus_src2_i$47 \int_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $368
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $369
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $332
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $333
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$51 [0]
+ connect \A \fus_cu_rd__rel_o$48 [1]
connect \B \fu_enable [9]
- connect \Y $368
+ connect \Y $332
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $370
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $371
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $334
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $335
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $368
- connect \B \rdflag_INT_ra_0
- connect \Y $370
+ connect \A $332
+ connect \B \rdflag_INT_rabc_0
+ connect \Y $334
end
- process $group_192
+ process $group_197
assign \pick$268 1'0
- assign \pick$268 $370
+ assign \pick$268 $334
sync init
end
- process $group_193
- assign \fus_cu_rd__go_i$52 3'000
- assign \fus_cu_rd__go_i$52 [0] \rdpick_INT_ra_o [8]
- assign \fus_cu_rd__go_i$52 [1] \rdpick_INT_rbc_o [7]
- assign \fus_cu_rd__go_i$52 [2] \rdpick_INT_rbc_o [9]
+ process $group_198
+ assign \fus_cu_rd__go_i$49 3'000
+ assign \fus_cu_rd__go_i$49 [1] \rdpick_INT_rabc_o [7]
+ assign \fus_cu_rd__go_i$49 [2] \rdpick_INT_rabc_o [9]
+ assign \fus_cu_rd__go_i$49 [0] \rdpick_INT_rabc_o [18]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 32 \read_en$372
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
- wire width 32 $373
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
- cell $sshl $374
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_reg1
- connect \Y $373
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 32 $375
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $376
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $377
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_INT_rabc_ldst0_7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $336
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $337
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [8]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $376
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $378
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $373
- connect \S $376
- connect \Y $375
+ connect \A \rdpick_INT_rabc_o [7]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $336
end
- process $group_194
- assign \read_en$372 32'00000000000000000000000000000000
- assign \read_en$372 $375
+ process $group_199
+ assign \rp_INT_rabc_ldst0_7 1'0
+ assign \rp_INT_rabc_ldst0_7 $336
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $379
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $380
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_INT_ra_o [8]
- connect \B \rdpick_INT_ra_en_o
- connect \Y $379
+ wire width 5 \addr_en_INT_rabc_ldst0_7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 5 $338
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $339
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_reg2
+ connect \S \rp_INT_rabc_ldst0_7
+ connect \Y $338
end
- process $group_195
- assign \fus_src1_i$53 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $379 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ process $group_200
+ assign \addr_en_INT_rabc_ldst0_7 5'00000
+ assign \addr_en_INT_rabc_ldst0_7 $338
+ sync init
+ end
+ process $group_201
+ assign \fus_src2_i$50 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_INT_rabc_ldst0_7 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
- assign \fus_src1_i$53 \int_src1__data_o
+ assign \fus_src2_i$50 \int_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 32 $381
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $382
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $340
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $341
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A \read_en
- connect \B \read_en$281
- connect \Y $381
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_cu_rd__rel_o$45 [2]
+ connect \B \fu_enable [8]
+ connect \Y $340
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 32 $383
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $384
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $342
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $343
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A \read_en$294
- connect \B \read_en$307
- connect \Y $383
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $340
+ connect \B \rdflag_INT_rabc_1
+ connect \Y $342
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 32 $385
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $386
- parameter \A_SIGNED 0
- parameter \A_WIDTH 32
- parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A $381
- connect \B $383
- connect \Y $385
+ process $group_202
+ assign \pick$269 1'0
+ assign \pick$269 $342
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 32 $387
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $388
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_INT_rabc_shiftrot0_8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $344
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $345
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A \read_en$320
- connect \B \read_en$333
- connect \Y $387
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \rdpick_INT_rabc_o [8]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $344
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 32 $389
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $390
- parameter \A_SIGNED 0
- parameter \A_WIDTH 32
- parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A \read_en$359
- connect \B \read_en$372
- connect \Y $389
+ process $group_203
+ assign \rp_INT_rabc_shiftrot0_8 1'0
+ assign \rp_INT_rabc_shiftrot0_8 $344
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 32 $391
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $392
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 5 \addr_en_INT_rabc_shiftrot0_8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 5 $346
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $347
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_reg3
+ connect \S \rp_INT_rabc_shiftrot0_8
+ connect \Y $346
+ end
+ process $group_204
+ assign \addr_en_INT_rabc_shiftrot0_8 5'00000
+ assign \addr_en_INT_rabc_shiftrot0_8 $346
+ sync init
+ end
+ process $group_205
+ assign \fus_src3_i 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_INT_rabc_shiftrot0_8 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ case 1'1
+ assign \fus_src3_i \int_src1__data_o
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $348
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $349
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A \read_en$346
- connect \B $389
- connect \Y $391
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_cu_rd__rel_o$48 [2]
+ connect \B \fu_enable [9]
+ connect \Y $348
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 32 $393
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $394
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $350
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $351
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A $387
- connect \B $391
- connect \Y $393
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $348
+ connect \B \rdflag_INT_rabc_1
+ connect \Y $350
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 32 $395
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $396
+ process $group_206
+ assign \pick$270 1'0
+ assign \pick$270 $350
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_INT_rabc_ldst0_9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $352
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $353
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A $385
- connect \B $393
- connect \Y $395
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \rdpick_INT_rabc_o [9]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $352
end
- process $group_196
- assign \int_src1__ren 32'00000000000000000000000000000000
- assign \int_src1__ren $395
+ process $group_207
+ assign \rp_INT_rabc_ldst0_9 1'0
+ assign \rp_INT_rabc_ldst0_9 $352
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
- wire width 1 \rdflag_INT_rbc_0
- process $group_197
- assign \rdflag_INT_rbc_0 1'0
- assign \rdflag_INT_rbc_0 \pdecode2_reg2_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 5 \addr_en_INT_rabc_ldst0_9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 5 $354
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $355
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_reg3
+ connect \S \rp_INT_rabc_ldst0_9
+ connect \Y $354
+ end
+ process $group_208
+ assign \addr_en_INT_rabc_ldst0_9 5'00000
+ assign \addr_en_INT_rabc_ldst0_9 $354
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
- wire width 1 \rdflag_INT_rbc_1
- process $group_198
- assign \rdflag_INT_rbc_1 1'0
- assign \rdflag_INT_rbc_1 \pdecode2_reg3_ok
+ process $group_209
+ assign \fus_src3_i$51 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_INT_rabc_ldst0_9 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ case 1'1
+ assign \fus_src3_i$51 \int_src1__data_o
+ end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$397
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $398
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $399
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $356
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $357
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o [1]
+ connect \A \fus_cu_rd__rel_o [0]
connect \B \fu_enable [0]
- connect \Y $398
+ connect \Y $356
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $400
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $401
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $358
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $359
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $398
- connect \B \rdflag_INT_rbc_0
- connect \Y $400
+ connect \A $356
+ connect \B \rdflag_INT_rabc_2
+ connect \Y $358
end
- process $group_199
- assign \pick$397 1'0
- assign \pick$397 $400
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$402
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$403
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$404
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$405
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$406
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$407
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$408
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$409
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$410
- process $group_200
- assign \rdpick_INT_rbc_i 10'0000000000
- assign \rdpick_INT_rbc_i [0] \pick$397
- assign \rdpick_INT_rbc_i [1] \pick$402
- assign \rdpick_INT_rbc_i [2] \pick$403
- assign \rdpick_INT_rbc_i [3] \pick$404
- assign \rdpick_INT_rbc_i [4] \pick$405
- assign \rdpick_INT_rbc_i [5] \pick$406
- assign \rdpick_INT_rbc_i [6] \pick$407
- assign \rdpick_INT_rbc_i [7] \pick$408
- assign \rdpick_INT_rbc_i [8] \pick$409
- assign \rdpick_INT_rbc_i [9] \pick$410
+ process $group_210
+ assign \pick$271 1'0
+ assign \pick$271 $358
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 32 \read_en$411
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
- wire width 32 $412
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
- cell $sshl $413
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_reg2
- connect \Y $412
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 32 $414
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $415
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $416
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_INT_rabc_alu0_10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $360
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $361
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rbc_o [0]
- connect \B \rdpick_INT_rbc_en_o
- connect \Y $415
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $417
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $412
- connect \S $415
- connect \Y $414
+ connect \A \rdpick_INT_rabc_o [10]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $360
end
- process $group_201
- assign \read_en$411 32'00000000000000000000000000000000
- assign \read_en$411 $414
+ process $group_211
+ assign \rp_INT_rabc_alu0_10 1'0
+ assign \rp_INT_rabc_alu0_10 $360
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $418
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $419
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rbc_o [0]
- connect \B \rdpick_INT_rbc_en_o
- connect \Y $418
+ wire width 5 \addr_en_INT_rabc_alu0_10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 5 $362
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $363
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_reg1
+ connect \S \rp_INT_rabc_alu0_10
+ connect \Y $362
end
- process $group_202
- assign \fus_src2_i 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $418 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ process $group_212
+ assign \addr_en_INT_rabc_alu0_10 5'00000
+ assign \addr_en_INT_rabc_alu0_10 $362
+ sync init
+ end
+ process $group_213
+ assign \fus_src1_i 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_INT_rabc_alu0_10 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
- assign \fus_src2_i \int_src3__data_o
+ assign \fus_src1_i \int_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $420
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $421
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $364
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $365
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$30 [1]
+ connect \A \fus_cu_rd__rel_o$30 [0]
connect \B \fu_enable [1]
- connect \Y $420
+ connect \Y $364
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $422
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $423
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $366
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $367
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $420
- connect \B \rdflag_INT_rbc_0
- connect \Y $422
+ connect \A $364
+ connect \B \rdflag_INT_rabc_2
+ connect \Y $366
end
- process $group_203
- assign \pick$402 1'0
- assign \pick$402 $422
+ process $group_214
+ assign \pick$272 1'0
+ assign \pick$272 $366
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 32 \read_en$424
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
- wire width 32 $425
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
- cell $sshl $426
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_reg2
- connect \Y $425
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 32 $427
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $428
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $429
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_INT_rabc_cr0_11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $368
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $369
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rbc_o [1]
- connect \B \rdpick_INT_rbc_en_o
- connect \Y $428
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $430
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $425
- connect \S $428
- connect \Y $427
+ connect \A \rdpick_INT_rabc_o [11]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $368
end
- process $group_204
- assign \read_en$424 32'00000000000000000000000000000000
- assign \read_en$424 $427
+ process $group_215
+ assign \rp_INT_rabc_cr0_11 1'0
+ assign \rp_INT_rabc_cr0_11 $368
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $431
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $432
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rbc_o [1]
- connect \B \rdpick_INT_rbc_en_o
- connect \Y $431
+ wire width 5 \addr_en_INT_rabc_cr0_11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 5 $370
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $371
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_reg1
+ connect \S \rp_INT_rabc_cr0_11
+ connect \Y $370
end
- process $group_205
- assign \fus_src2_i$54 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $431 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ process $group_216
+ assign \addr_en_INT_rabc_cr0_11 5'00000
+ assign \addr_en_INT_rabc_cr0_11 $370
+ sync init
+ end
+ process $group_217
+ assign \fus_src1_i$52 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_INT_rabc_cr0_11 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
- assign \fus_src2_i$54 \int_src3__data_o
+ assign \fus_src1_i$52 \int_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $433
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $434
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $372
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $373
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$33 [1]
+ connect \A \fus_cu_rd__rel_o$33 [0]
connect \B \fu_enable [3]
- connect \Y $433
+ connect \Y $372
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $435
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $436
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $374
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $375
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $433
- connect \B \rdflag_INT_rbc_0
- connect \Y $435
+ connect \A $372
+ connect \B \rdflag_INT_rabc_2
+ connect \Y $374
end
- process $group_206
- assign \pick$403 1'0
- assign \pick$403 $435
+ process $group_218
+ assign \pick$273 1'0
+ assign \pick$273 $374
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 32 \read_en$437
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
- wire width 32 $438
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
- cell $sshl $439
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_reg2
- connect \Y $438
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 32 $440
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $441
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $442
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_INT_rabc_trap0_12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $376
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $377
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rbc_o [2]
- connect \B \rdpick_INT_rbc_en_o
- connect \Y $441
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $443
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $438
- connect \S $441
- connect \Y $440
+ connect \A \rdpick_INT_rabc_o [12]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $376
end
- process $group_207
- assign \read_en$437 32'00000000000000000000000000000000
- assign \read_en$437 $440
+ process $group_219
+ assign \rp_INT_rabc_trap0_12 1'0
+ assign \rp_INT_rabc_trap0_12 $376
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $444
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $445
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rbc_o [2]
- connect \B \rdpick_INT_rbc_en_o
- connect \Y $444
+ wire width 5 \addr_en_INT_rabc_trap0_12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 5 $378
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $379
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_reg1
+ connect \S \rp_INT_rabc_trap0_12
+ connect \Y $378
end
- process $group_208
- assign \fus_src2_i$55 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $444 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ process $group_220
+ assign \addr_en_INT_rabc_trap0_12 5'00000
+ assign \addr_en_INT_rabc_trap0_12 $378
+ sync init
+ end
+ process $group_221
+ assign \fus_src1_i$53 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_INT_rabc_trap0_12 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
- assign \fus_src2_i$55 \int_src3__data_o
+ assign \fus_src1_i$53 \int_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $446
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $447
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $380
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $381
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$36 [1]
+ connect \A \fus_cu_rd__rel_o$36 [0]
connect \B \fu_enable [4]
- connect \Y $446
+ connect \Y $380
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $448
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $449
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $382
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $383
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $446
- connect \B \rdflag_INT_rbc_0
- connect \Y $448
+ connect \A $380
+ connect \B \rdflag_INT_rabc_2
+ connect \Y $382
end
- process $group_209
- assign \pick$404 1'0
- assign \pick$404 $448
+ process $group_222
+ assign \pick$274 1'0
+ assign \pick$274 $382
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 32 \read_en$450
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
- wire width 32 $451
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
- cell $sshl $452
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_reg2
- connect \Y $451
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 32 $453
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $454
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $455
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_INT_rabc_logical0_13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $384
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $385
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rbc_o [3]
- connect \B \rdpick_INT_rbc_en_o
- connect \Y $454
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $456
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $451
- connect \S $454
- connect \Y $453
+ connect \A \rdpick_INT_rabc_o [13]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $384
end
- process $group_210
- assign \read_en$450 32'00000000000000000000000000000000
- assign \read_en$450 $453
+ process $group_223
+ assign \rp_INT_rabc_logical0_13 1'0
+ assign \rp_INT_rabc_logical0_13 $384
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $457
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $458
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rbc_o [3]
- connect \B \rdpick_INT_rbc_en_o
- connect \Y $457
+ wire width 5 \addr_en_INT_rabc_logical0_13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 5 $386
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $387
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_reg1
+ connect \S \rp_INT_rabc_logical0_13
+ connect \Y $386
end
- process $group_211
- assign \fus_src2_i$56 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $457 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ process $group_224
+ assign \addr_en_INT_rabc_logical0_13 5'00000
+ assign \addr_en_INT_rabc_logical0_13 $386
+ sync init
+ end
+ process $group_225
+ assign \fus_src1_i$54 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_INT_rabc_logical0_13 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
- assign \fus_src2_i$56 \int_src3__data_o
+ assign \fus_src1_i$54 \int_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $459
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $460
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $388
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $389
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$42 [1]
- connect \B \fu_enable [6]
- connect \Y $459
+ connect \A \fus_cu_rd__rel_o$55 [0]
+ connect \B \fu_enable [5]
+ connect \Y $388
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $461
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $462
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $390
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $391
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $459
- connect \B \rdflag_INT_rbc_0
- connect \Y $461
+ connect \A $388
+ connect \B \rdflag_INT_rabc_2
+ connect \Y $390
end
- process $group_212
- assign \pick$405 1'0
- assign \pick$405 $461
+ process $group_226
+ assign \pick$275 1'0
+ assign \pick$275 $390
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 32 \read_en$463
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
- wire width 32 $464
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
- cell $sshl $465
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_reg2
- connect \Y $464
+ process $group_227
+ assign \fus_cu_rd__go_i$56 6'000000
+ assign \fus_cu_rd__go_i$56 [0] \rdpick_INT_rabc_o [14]
+ assign \fus_cu_rd__go_i$56 [3] \rdpick_XER_xer_so_o [1]
+ assign \fus_cu_rd__go_i$56 [5] \rdpick_XER_xer_ca_o [1]
+ assign \fus_cu_rd__go_i$56 [4] \rdpick_XER_xer_ov_o
+ assign \fus_cu_rd__go_i$56 [2] \rdpick_FAST_fast1_o [2]
+ assign \fus_cu_rd__go_i$56 [1] \rdpick_SPR_spr1_o
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 32 $466
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $467
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $468
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_INT_rabc_spr0_14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $392
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $393
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rbc_o [4]
- connect \B \rdpick_INT_rbc_en_o
- connect \Y $467
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $469
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $464
- connect \S $467
- connect \Y $466
+ connect \A \rdpick_INT_rabc_o [14]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $392
end
- process $group_213
- assign \read_en$463 32'00000000000000000000000000000000
- assign \read_en$463 $466
+ process $group_228
+ assign \rp_INT_rabc_spr0_14 1'0
+ assign \rp_INT_rabc_spr0_14 $392
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $470
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $471
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rbc_o [4]
- connect \B \rdpick_INT_rbc_en_o
- connect \Y $470
+ wire width 5 \addr_en_INT_rabc_spr0_14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 5 $394
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $395
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_reg1
+ connect \S \rp_INT_rabc_spr0_14
+ connect \Y $394
end
- process $group_214
- assign \fus_src2_i$57 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $470 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ process $group_229
+ assign \addr_en_INT_rabc_spr0_14 5'00000
+ assign \addr_en_INT_rabc_spr0_14 $394
+ sync init
+ end
+ process $group_230
+ assign \fus_src1_i$57 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_INT_rabc_spr0_14 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
- assign \fus_src2_i$57 \int_src3__data_o
+ assign \fus_src1_i$57 \int_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $472
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $473
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $396
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $397
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$45 [1]
- connect \B \fu_enable [7]
- connect \Y $472
+ connect \A \fus_cu_rd__rel_o$39 [0]
+ connect \B \fu_enable [6]
+ connect \Y $396
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $474
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $475
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $398
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $399
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $472
- connect \B \rdflag_INT_rbc_0
- connect \Y $474
+ connect \A $396
+ connect \B \rdflag_INT_rabc_2
+ connect \Y $398
end
- process $group_215
- assign \pick$406 1'0
- assign \pick$406 $474
+ process $group_231
+ assign \pick$276 1'0
+ assign \pick$276 $398
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 32 \read_en$476
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
- wire width 32 $477
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
- cell $sshl $478
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_reg2
- connect \Y $477
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 32 $479
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $480
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $481
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_INT_rabc_div0_15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $400
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $401
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rbc_o [5]
- connect \B \rdpick_INT_rbc_en_o
- connect \Y $480
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $482
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $477
- connect \S $480
- connect \Y $479
+ connect \A \rdpick_INT_rabc_o [15]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $400
end
- process $group_216
- assign \read_en$476 32'00000000000000000000000000000000
- assign \read_en$476 $479
+ process $group_232
+ assign \rp_INT_rabc_div0_15 1'0
+ assign \rp_INT_rabc_div0_15 $400
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $483
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $484
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rbc_o [5]
- connect \B \rdpick_INT_rbc_en_o
- connect \Y $483
+ wire width 5 \addr_en_INT_rabc_div0_15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 5 $402
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $403
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_reg1
+ connect \S \rp_INT_rabc_div0_15
+ connect \Y $402
end
- process $group_217
- assign \fus_src2_i$58 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $483 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ process $group_233
+ assign \addr_en_INT_rabc_div0_15 5'00000
+ assign \addr_en_INT_rabc_div0_15 $402
+ sync init
+ end
+ process $group_234
+ assign \fus_src1_i$58 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_INT_rabc_div0_15 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
- assign \fus_src2_i$58 \int_src3__data_o
+ assign \fus_src1_i$58 \int_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $485
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $486
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $404
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $405
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$48 [1]
- connect \B \fu_enable [8]
- connect \Y $485
+ connect \A \fus_cu_rd__rel_o$42 [0]
+ connect \B \fu_enable [7]
+ connect \Y $404
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $487
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $488
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $406
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $407
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $485
- connect \B \rdflag_INT_rbc_0
- connect \Y $487
+ connect \A $404
+ connect \B \rdflag_INT_rabc_2
+ connect \Y $406
end
- process $group_218
- assign \pick$407 1'0
- assign \pick$407 $487
+ process $group_235
+ assign \pick$277 1'0
+ assign \pick$277 $406
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 32 \read_en$489
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
- wire width 32 $490
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
- cell $sshl $491
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_reg2
- connect \Y $490
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 32 $492
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $493
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $494
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_INT_rabc_mul0_16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $408
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $409
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rbc_o [6]
- connect \B \rdpick_INT_rbc_en_o
- connect \Y $493
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $495
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $490
- connect \S $493
- connect \Y $492
+ connect \A \rdpick_INT_rabc_o [16]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $408
end
- process $group_219
- assign \read_en$489 32'00000000000000000000000000000000
- assign \read_en$489 $492
+ process $group_236
+ assign \rp_INT_rabc_mul0_16 1'0
+ assign \rp_INT_rabc_mul0_16 $408
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $496
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $497
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rbc_o [6]
- connect \B \rdpick_INT_rbc_en_o
- connect \Y $496
+ wire width 5 \addr_en_INT_rabc_mul0_16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 5 $410
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $411
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_reg1
+ connect \S \rp_INT_rabc_mul0_16
+ connect \Y $410
end
- process $group_220
- assign \fus_src2_i$59 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $496 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ process $group_237
+ assign \addr_en_INT_rabc_mul0_16 5'00000
+ assign \addr_en_INT_rabc_mul0_16 $410
+ sync init
+ end
+ process $group_238
+ assign \fus_src1_i$59 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_INT_rabc_mul0_16 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
- assign \fus_src2_i$59 \int_src3__data_o
+ assign \fus_src1_i$59 \int_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $498
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $499
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $412
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $413
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$51 [1]
- connect \B \fu_enable [9]
- connect \Y $498
+ connect \A \fus_cu_rd__rel_o$45 [0]
+ connect \B \fu_enable [8]
+ connect \Y $412
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $500
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $501
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $414
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $415
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $498
- connect \B \rdflag_INT_rbc_0
- connect \Y $500
+ connect \A $412
+ connect \B \rdflag_INT_rabc_2
+ connect \Y $414
end
- process $group_221
- assign \pick$408 1'0
- assign \pick$408 $500
+ process $group_239
+ assign \pick$278 1'0
+ assign \pick$278 $414
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 32 \read_en$502
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
- wire width 32 $503
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
- cell $sshl $504
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_reg2
- connect \Y $503
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 32 $505
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $506
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $507
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_INT_rabc_shiftrot0_17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $416
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $417
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rbc_o [7]
- connect \B \rdpick_INT_rbc_en_o
- connect \Y $506
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $508
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $503
- connect \S $506
- connect \Y $505
+ connect \A \rdpick_INT_rabc_o [17]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $416
end
- process $group_222
- assign \read_en$502 32'00000000000000000000000000000000
- assign \read_en$502 $505
+ process $group_240
+ assign \rp_INT_rabc_shiftrot0_17 1'0
+ assign \rp_INT_rabc_shiftrot0_17 $416
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $509
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $510
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rbc_o [7]
- connect \B \rdpick_INT_rbc_en_o
- connect \Y $509
+ wire width 5 \addr_en_INT_rabc_shiftrot0_17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 5 $418
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $419
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_reg1
+ connect \S \rp_INT_rabc_shiftrot0_17
+ connect \Y $418
end
- process $group_223
- assign \fus_src2_i$60 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $509 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ process $group_241
+ assign \addr_en_INT_rabc_shiftrot0_17 5'00000
+ assign \addr_en_INT_rabc_shiftrot0_17 $418
+ sync init
+ end
+ process $group_242
+ assign \fus_src1_i$60 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_INT_rabc_shiftrot0_17 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
- assign \fus_src2_i$60 \int_src3__data_o
+ assign \fus_src1_i$60 \int_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $511
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $512
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $420
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $421
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$48 [2]
- connect \B \fu_enable [8]
- connect \Y $511
+ connect \A \fus_cu_rd__rel_o$48 [0]
+ connect \B \fu_enable [9]
+ connect \Y $420
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $513
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $514
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $422
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $423
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $511
- connect \B \rdflag_INT_rbc_1
- connect \Y $513
+ connect \A $420
+ connect \B \rdflag_INT_rabc_2
+ connect \Y $422
end
- process $group_224
- assign \pick$409 1'0
- assign \pick$409 $513
+ process $group_243
+ assign \pick$279 1'0
+ assign \pick$279 $422
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 32 \read_en$515
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55"
- wire width 32 $516
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55"
- cell $sshl $517
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_reg3
- connect \Y $516
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 32 $518
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $519
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $520
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_INT_rabc_ldst0_18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $424
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $425
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rbc_o [8]
- connect \B \rdpick_INT_rbc_en_o
- connect \Y $519
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $521
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $516
- connect \S $519
- connect \Y $518
+ connect \A \rdpick_INT_rabc_o [18]
+ connect \B \rdpick_INT_rabc_en_o
+ connect \Y $424
end
- process $group_225
- assign \read_en$515 32'00000000000000000000000000000000
- assign \read_en$515 $518
+ process $group_244
+ assign \rp_INT_rabc_ldst0_18 1'0
+ assign \rp_INT_rabc_ldst0_18 $424
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $522
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $523
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rbc_o [8]
- connect \B \rdpick_INT_rbc_en_o
- connect \Y $522
+ wire width 5 \addr_en_INT_rabc_ldst0_18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 5 $426
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $427
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_reg1
+ connect \S \rp_INT_rabc_ldst0_18
+ connect \Y $426
end
- process $group_226
- assign \fus_src3_i 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $522 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ process $group_245
+ assign \addr_en_INT_rabc_ldst0_18 5'00000
+ assign \addr_en_INT_rabc_ldst0_18 $426
+ sync init
+ end
+ process $group_246
+ assign \fus_src1_i$61 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_INT_rabc_ldst0_18 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
- assign \fus_src3_i \int_src3__data_o
+ assign \fus_src1_i$61 \int_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $524
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $525
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 5 $428
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $429
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$51 [2]
- connect \B \fu_enable [9]
- connect \Y $524
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \addr_en_INT_rabc_alu0_0
+ connect \B \addr_en_INT_rabc_cr0_1
+ connect \Y $428
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $526
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $527
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 5 $430
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $431
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $524
- connect \B \rdflag_INT_rbc_1
- connect \Y $526
- end
- process $group_227
- assign \pick$410 1'0
- assign \pick$410 $526
- sync init
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \addr_en_INT_rabc_trap0_2
+ connect \B \addr_en_INT_rabc_logical0_3
+ connect \Y $430
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 32 \read_en$528
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55"
- wire width 32 $529
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55"
- cell $sshl $530
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 5 $432
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ cell $or $433
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_reg3
- connect \Y $529
+ parameter \Y_WIDTH 5
+ connect \A $428
+ connect \B $430
+ connect \Y $432
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 32 $531
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $532
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $533
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 5 $434
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $435
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rbc_o [9]
- connect \B \rdpick_INT_rbc_en_o
- connect \Y $532
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \addr_en_INT_rabc_div0_4
+ connect \B \addr_en_INT_rabc_mul0_5
+ connect \Y $434
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $534
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $529
- connect \S $532
- connect \Y $531
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 5 $436
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $437
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \addr_en_INT_rabc_ldst0_7
+ connect \B \addr_en_INT_rabc_shiftrot0_8
+ connect \Y $436
end
- process $group_228
- assign \read_en$528 32'00000000000000000000000000000000
- assign \read_en$528 $531
- sync init
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 5 $438
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ cell $or $439
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \addr_en_INT_rabc_shiftrot0_6
+ connect \B $436
+ connect \Y $438
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $535
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $536
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 5 $440
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ cell $or $441
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_INT_rbc_o [9]
- connect \B \rdpick_INT_rbc_en_o
- connect \Y $535
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A $434
+ connect \B $438
+ connect \Y $440
end
- process $group_229
- assign \fus_src3_i$61 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $535 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- case 1'1
- assign \fus_src3_i$61 \int_src3__data_o
- end
- sync init
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 5 $442
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ cell $or $443
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A $432
+ connect \B $440
+ connect \Y $442
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 32 $537
+ wire width 5 $444
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $538
+ cell $or $445
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A \read_en$411
- connect \B \read_en$424
- connect \Y $537
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \addr_en_INT_rabc_ldst0_9
+ connect \B \addr_en_INT_rabc_alu0_10
+ connect \Y $444
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 32 $539
+ wire width 5 $446
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $540
+ cell $or $447
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A \read_en$450
- connect \B \read_en$463
- connect \Y $539
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \addr_en_INT_rabc_trap0_12
+ connect \B \addr_en_INT_rabc_logical0_13
+ connect \Y $446
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 32 $541
+ wire width 5 $448
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $542
+ cell $or $449
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A \read_en$437
- connect \B $539
- connect \Y $541
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \addr_en_INT_rabc_cr0_11
+ connect \B $446
+ connect \Y $448
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 32 $543
+ wire width 5 $450
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $544
+ cell $or $451
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A $537
- connect \B $541
- connect \Y $543
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A $444
+ connect \B $448
+ connect \Y $450
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 32 $545
+ wire width 5 $452
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $546
+ cell $or $453
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A \read_en$476
- connect \B \read_en$489
- connect \Y $545
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \addr_en_INT_rabc_spr0_14
+ connect \B \addr_en_INT_rabc_div0_15
+ connect \Y $452
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 32 $547
+ wire width 5 $454
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $548
+ cell $or $455
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A \read_en$515
- connect \B \read_en$528
- connect \Y $547
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \addr_en_INT_rabc_shiftrot0_17
+ connect \B \addr_en_INT_rabc_ldst0_18
+ connect \Y $454
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 32 $549
+ wire width 5 $456
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $550
+ cell $or $457
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A \read_en$502
- connect \B $547
- connect \Y $549
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \addr_en_INT_rabc_mul0_16
+ connect \B $454
+ connect \Y $456
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 32 $551
+ wire width 5 $458
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $552
+ cell $or $459
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A $545
- connect \B $549
- connect \Y $551
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A $452
+ connect \B $456
+ connect \Y $458
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 32 $553
+ wire width 5 $460
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $554
+ cell $or $461
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A $543
- connect \B $551
- connect \Y $553
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A $450
+ connect \B $458
+ connect \Y $460
end
- process $group_230
- assign \int_src3__ren 32'00000000000000000000000000000000
- assign \int_src3__ren $553
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 5 $462
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ cell $or $463
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A $442
+ connect \B $460
+ connect \Y $462
+ end
+ process $group_247
+ assign \int_src1__addr 5'00000
+ assign \int_src1__addr $462
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262"
+ wire width 1 $464
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262"
+ cell $reduce_bool $465
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 19
+ parameter \Y_WIDTH 1
+ connect \A { \rp_INT_rabc_ldst0_18 \rp_INT_rabc_shiftrot0_17 \rp_INT_rabc_mul0_16 \rp_INT_rabc_div0_15 \rp_INT_rabc_spr0_14 \rp_INT_rabc_logical0_13 \rp_INT_rabc_trap0_12 \rp_INT_rabc_cr0_11 \rp_INT_rabc_alu0_10 \rp_INT_rabc_ldst0_9 \rp_INT_rabc_shiftrot0_8 \rp_INT_rabc_ldst0_7 \rp_INT_rabc_shiftrot0_6 \rp_INT_rabc_mul0_5 \rp_INT_rabc_div0_4 \rp_INT_rabc_logical0_3 \rp_INT_rabc_trap0_2 \rp_INT_rabc_cr0_1 \rp_INT_rabc_alu0_0 }
+ connect \Y $464
+ end
+ process $group_248
+ assign \int_src1__ren 1'0
+ assign \int_src1__ren $464
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204"
wire width 1 \rdflag_XER_xer_so_0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
- wire width 1 $555
+ wire width 1 $466
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
- cell $and $556
+ cell $and $467
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pdecode2_oe
connect \B \pdecode2_oe_ok
- connect \Y $555
+ connect \Y $466
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
- wire width 1 $557
+ wire width 1 $468
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
- cell $or $558
+ cell $or $469
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $555
+ connect \A $466
connect \B \pdecode2_xer_in
- connect \Y $557
+ connect \Y $468
end
- process $group_231
+ process $group_249
assign \rdflag_XER_xer_so_0 1'0
- assign \rdflag_XER_xer_so_0 $557
+ assign \rdflag_XER_xer_so_0 $468
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$559
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $560
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $561
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$470
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $471
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $472
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_rd__rel_o [2]
connect \B \fu_enable [0]
- connect \Y $560
+ connect \Y $471
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $562
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $563
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $473
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $474
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $560
+ connect \A $471
connect \B \rdflag_XER_xer_so_0
- connect \Y $562
+ connect \Y $473
end
- process $group_232
- assign \pick$559 1'0
- assign \pick$559 $562
+ process $group_250
+ assign \pick$470 1'0
+ assign \pick$470 $473
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$564
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$565
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$566
- process $group_233
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$475
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$476
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$477
+ process $group_251
assign \rdpick_XER_xer_so_i 4'0000
- assign \rdpick_XER_xer_so_i [0] \pick$559
- assign \rdpick_XER_xer_so_i [1] \pick$564
- assign \rdpick_XER_xer_so_i [2] \pick$565
- assign \rdpick_XER_xer_so_i [3] \pick$566
+ assign \rdpick_XER_xer_so_i [0] \pick$470
+ assign \rdpick_XER_xer_so_i [1] \pick$475
+ assign \rdpick_XER_xer_so_i [2] \pick$476
+ assign \rdpick_XER_xer_so_i [3] \pick$477
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 1 \read_en$567
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $568
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $569
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $570
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_XER_xer_so_alu0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $478
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $479
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_XER_xer_so_o [0]
connect \B \rdpick_XER_xer_so_en_o
- connect \Y $569
+ connect \Y $478
+ end
+ process $group_252
+ assign \rp_XER_xer_so_alu0_0 1'0
+ assign \rp_XER_xer_so_alu0_0 $478
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $571
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 1 \addr_en_XER_xer_so_alu0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 1 $480
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $481
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
- connect \S $569
- connect \Y $568
+ connect \S \rp_XER_xer_so_alu0_0
+ connect \Y $480
end
- process $group_234
- assign \read_en$567 1'0
- assign \read_en$567 $568
+ process $group_253
+ assign \addr_en_XER_xer_so_alu0_0 1'0
+ assign \addr_en_XER_xer_so_alu0_0 $480
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $572
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $573
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_XER_xer_so_o [0]
- connect \B \rdpick_XER_xer_so_en_o
- connect \Y $572
- end
- process $group_235
+ process $group_254
assign \fus_src3_i$62 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $572 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_XER_xer_so_alu0_0 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
assign \fus_src3_i$62 \xer_src1__data_o [0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $574
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $575
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $482
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $483
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$39 [3]
+ connect \A \fus_cu_rd__rel_o$55 [3]
connect \B \fu_enable [5]
- connect \Y $574
+ connect \Y $482
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $576
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $577
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $484
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $485
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $574
+ connect \A $482
connect \B \rdflag_XER_xer_so_0
- connect \Y $576
+ connect \Y $484
end
- process $group_236
- assign \pick$564 1'0
- assign \pick$564 $576
+ process $group_255
+ assign \pick$475 1'0
+ assign \pick$475 $484
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 1 \read_en$578
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $579
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $580
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $581
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_XER_xer_so_spr0_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $486
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $487
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_XER_xer_so_o [1]
connect \B \rdpick_XER_xer_so_en_o
- connect \Y $580
+ connect \Y $486
+ end
+ process $group_256
+ assign \rp_XER_xer_so_spr0_1 1'0
+ assign \rp_XER_xer_so_spr0_1 $486
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $582
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 1 \addr_en_XER_xer_so_spr0_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 1 $488
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $489
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
- connect \S $580
- connect \Y $579
+ connect \S \rp_XER_xer_so_spr0_1
+ connect \Y $488
end
- process $group_237
- assign \read_en$578 1'0
- assign \read_en$578 $579
+ process $group_257
+ assign \addr_en_XER_xer_so_spr0_1 1'0
+ assign \addr_en_XER_xer_so_spr0_1 $488
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $583
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $584
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_XER_xer_so_o [1]
- connect \B \rdpick_XER_xer_so_en_o
- connect \Y $583
- end
- process $group_238
+ process $group_258
assign \fus_src4_i 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $583 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_XER_xer_so_spr0_1 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
assign \fus_src4_i \xer_src1__data_o [0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $585
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $586
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $490
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $491
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$42 [2]
+ connect \A \fus_cu_rd__rel_o$39 [2]
connect \B \fu_enable [6]
- connect \Y $585
+ connect \Y $490
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $587
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $588
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $492
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $493
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $585
+ connect \A $490
connect \B \rdflag_XER_xer_so_0
- connect \Y $587
+ connect \Y $492
end
- process $group_239
- assign \pick$565 1'0
- assign \pick$565 $587
+ process $group_259
+ assign \pick$476 1'0
+ assign \pick$476 $492
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 1 \read_en$589
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $590
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $591
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $592
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_XER_xer_so_div0_2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $494
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $495
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_XER_xer_so_o [2]
connect \B \rdpick_XER_xer_so_en_o
- connect \Y $591
+ connect \Y $494
+ end
+ process $group_260
+ assign \rp_XER_xer_so_div0_2 1'0
+ assign \rp_XER_xer_so_div0_2 $494
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $593
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 1 \addr_en_XER_xer_so_div0_2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 1 $496
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $497
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
- connect \S $591
- connect \Y $590
+ connect \S \rp_XER_xer_so_div0_2
+ connect \Y $496
end
- process $group_240
- assign \read_en$589 1'0
- assign \read_en$589 $590
+ process $group_261
+ assign \addr_en_XER_xer_so_div0_2 1'0
+ assign \addr_en_XER_xer_so_div0_2 $496
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $594
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $595
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_XER_xer_so_o [2]
- connect \B \rdpick_XER_xer_so_en_o
- connect \Y $594
- end
- process $group_241
+ process $group_262
assign \fus_src3_i$63 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $594 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_XER_xer_so_div0_2 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
assign \fus_src3_i$63 \xer_src1__data_o [0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $596
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $597
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $498
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $499
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$45 [2]
+ connect \A \fus_cu_rd__rel_o$42 [2]
connect \B \fu_enable [7]
- connect \Y $596
+ connect \Y $498
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $598
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $599
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $500
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $501
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $596
+ connect \A $498
connect \B \rdflag_XER_xer_so_0
- connect \Y $598
+ connect \Y $500
end
- process $group_242
- assign \pick$566 1'0
- assign \pick$566 $598
+ process $group_263
+ assign \pick$477 1'0
+ assign \pick$477 $500
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 1 \read_en$600
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $601
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $602
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $603
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_XER_xer_so_mul0_3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $502
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $503
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_XER_xer_so_o [3]
connect \B \rdpick_XER_xer_so_en_o
- connect \Y $602
+ connect \Y $502
+ end
+ process $group_264
+ assign \rp_XER_xer_so_mul0_3 1'0
+ assign \rp_XER_xer_so_mul0_3 $502
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $604
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 1 \addr_en_XER_xer_so_mul0_3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 1 $504
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $505
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
- connect \S $602
- connect \Y $601
+ connect \S \rp_XER_xer_so_mul0_3
+ connect \Y $504
end
- process $group_243
- assign \read_en$600 1'0
- assign \read_en$600 $601
+ process $group_265
+ assign \addr_en_XER_xer_so_mul0_3 1'0
+ assign \addr_en_XER_xer_so_mul0_3 $504
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $605
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $606
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_XER_xer_so_o [3]
- connect \B \rdpick_XER_xer_so_en_o
- connect \Y $605
- end
- process $group_244
+ process $group_266
assign \fus_src3_i$64 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $605 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_XER_xer_so_mul0_3 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
assign \fus_src3_i$64 \xer_src1__data_o [0]
end
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 3 $607
+ wire width 3 $506
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 1 $608
+ wire width 1 $507
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $609
+ cell $or $508
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \read_en$567
- connect \B \read_en$578
- connect \Y $608
+ connect \A \addr_en_XER_xer_so_alu0_0
+ connect \B \addr_en_XER_xer_so_spr0_1
+ connect \Y $507
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 1 $610
+ wire width 1 $509
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $611
+ cell $or $510
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \read_en$589
- connect \B \read_en$600
- connect \Y $610
+ connect \A \addr_en_XER_xer_so_div0_2
+ connect \B \addr_en_XER_xer_so_mul0_3
+ connect \Y $509
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 1 $612
+ wire width 1 $511
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $613
+ cell $or $512
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $608
- connect \B $610
- connect \Y $612
+ connect \A $507
+ connect \B $509
+ connect \Y $511
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $pos $614
+ cell $pos $513
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 3
- connect \A $612
- connect \Y $607
+ connect \A $511
+ connect \Y $506
end
- process $group_245
+ process $group_267
assign \xer_src1__ren 3'000
- assign \xer_src1__ren $607
+ assign \xer_src1__ren $506
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204"
wire width 1 \rdflag_XER_xer_ca_0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
- wire width 1 $615
+ wire width 1 $514
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
- cell $eq $616
+ cell $eq $515
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pdecode2_input_carry
connect \B 2'10
- connect \Y $615
+ connect \Y $514
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
- wire width 1 $617
+ wire width 1 $516
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
- cell $or $618
+ cell $or $517
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $615
+ connect \A $514
connect \B \pdecode2_xer_in
- connect \Y $617
+ connect \Y $516
end
- process $group_246
+ process $group_268
assign \rdflag_XER_xer_ca_0 1'0
- assign \rdflag_XER_xer_ca_0 $617
+ assign \rdflag_XER_xer_ca_0 $516
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$619
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $620
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $621
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$518
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $519
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $520
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_rd__rel_o [3]
connect \B \fu_enable [0]
- connect \Y $620
+ connect \Y $519
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $622
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $623
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $521
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $522
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $620
+ connect \A $519
connect \B \rdflag_XER_xer_ca_0
- connect \Y $622
+ connect \Y $521
end
- process $group_247
- assign \pick$619 1'0
- assign \pick$619 $622
+ process $group_269
+ assign \pick$518 1'0
+ assign \pick$518 $521
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$624
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$625
- process $group_248
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$523
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$524
+ process $group_270
assign \rdpick_XER_xer_ca_i 3'000
- assign \rdpick_XER_xer_ca_i [0] \pick$619
- assign \rdpick_XER_xer_ca_i [1] \pick$624
- assign \rdpick_XER_xer_ca_i [2] \pick$625
+ assign \rdpick_XER_xer_ca_i [0] \pick$518
+ assign \rdpick_XER_xer_ca_i [1] \pick$523
+ assign \rdpick_XER_xer_ca_i [2] \pick$524
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 2 \read_en$626
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 2 $627
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $628
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $629
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_XER_xer_ca_alu0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $525
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $526
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_XER_xer_ca_o [0]
connect \B \rdpick_XER_xer_ca_en_o
- connect \Y $628
+ connect \Y $525
+ end
+ process $group_271
+ assign \rp_XER_xer_ca_alu0_0 1'0
+ assign \rp_XER_xer_ca_alu0_0 $525
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $630
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 2 \addr_en_XER_xer_ca_alu0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 2 $527
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $528
parameter \WIDTH 2
connect \A 2'00
connect \B 2'10
- connect \S $628
- connect \Y $627
+ connect \S \rp_XER_xer_ca_alu0_0
+ connect \Y $527
end
- process $group_249
- assign \read_en$626 2'00
- assign \read_en$626 $627
+ process $group_272
+ assign \addr_en_XER_xer_ca_alu0_0 2'00
+ assign \addr_en_XER_xer_ca_alu0_0 $527
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $631
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $632
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_XER_xer_ca_o [0]
- connect \B \rdpick_XER_xer_ca_en_o
- connect \Y $631
- end
- process $group_250
+ process $group_273
assign \fus_src4_i$65 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $631 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_XER_xer_ca_alu0_0 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
assign \fus_src4_i$65 \xer_src2__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $633
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $634
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $529
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $530
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$39 [5]
+ connect \A \fus_cu_rd__rel_o$55 [5]
connect \B \fu_enable [5]
- connect \Y $633
+ connect \Y $529
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $635
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $636
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $531
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $532
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $633
+ connect \A $529
connect \B \rdflag_XER_xer_ca_0
- connect \Y $635
+ connect \Y $531
end
- process $group_251
- assign \pick$624 1'0
- assign \pick$624 $635
+ process $group_274
+ assign \pick$523 1'0
+ assign \pick$523 $531
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 2 \read_en$637
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 2 $638
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $639
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $640
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_XER_xer_ca_spr0_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $533
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $534
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_XER_xer_ca_o [1]
connect \B \rdpick_XER_xer_ca_en_o
- connect \Y $639
+ connect \Y $533
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $641
+ process $group_275
+ assign \rp_XER_xer_ca_spr0_1 1'0
+ assign \rp_XER_xer_ca_spr0_1 $533
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 2 \addr_en_XER_xer_ca_spr0_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 2 $535
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $536
parameter \WIDTH 2
connect \A 2'00
connect \B 2'10
- connect \S $639
- connect \Y $638
+ connect \S \rp_XER_xer_ca_spr0_1
+ connect \Y $535
end
- process $group_252
- assign \read_en$637 2'00
- assign \read_en$637 $638
+ process $group_276
+ assign \addr_en_XER_xer_ca_spr0_1 2'00
+ assign \addr_en_XER_xer_ca_spr0_1 $535
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $642
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $643
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_XER_xer_ca_o [1]
- connect \B \rdpick_XER_xer_ca_en_o
- connect \Y $642
- end
- process $group_253
+ process $group_277
assign \fus_src6_i 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $642 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_XER_xer_ca_spr0_1 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
assign \fus_src6_i \xer_src2__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $644
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $645
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $537
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $538
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$48 [3]
+ connect \A \fus_cu_rd__rel_o$45 [3]
connect \B \fu_enable [8]
- connect \Y $644
+ connect \Y $537
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $646
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $647
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $539
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $540
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $644
+ connect \A $537
connect \B \rdflag_XER_xer_ca_0
- connect \Y $646
+ connect \Y $539
end
- process $group_254
- assign \pick$625 1'0
- assign \pick$625 $646
+ process $group_278
+ assign \pick$524 1'0
+ assign \pick$524 $539
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 2 \read_en$648
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 2 $649
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $650
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $651
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_XER_xer_ca_shiftrot0_2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $541
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $542
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_XER_xer_ca_o [2]
connect \B \rdpick_XER_xer_ca_en_o
- connect \Y $650
+ connect \Y $541
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $652
+ process $group_279
+ assign \rp_XER_xer_ca_shiftrot0_2 1'0
+ assign \rp_XER_xer_ca_shiftrot0_2 $541
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 2 \addr_en_XER_xer_ca_shiftrot0_2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 2 $543
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $544
parameter \WIDTH 2
connect \A 2'00
connect \B 2'10
- connect \S $650
- connect \Y $649
+ connect \S \rp_XER_xer_ca_shiftrot0_2
+ connect \Y $543
end
- process $group_255
- assign \read_en$648 2'00
- assign \read_en$648 $649
+ process $group_280
+ assign \addr_en_XER_xer_ca_shiftrot0_2 2'00
+ assign \addr_en_XER_xer_ca_shiftrot0_2 $543
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $653
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $654
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_XER_xer_ca_o [2]
- connect \B \rdpick_XER_xer_ca_en_o
- connect \Y $653
- end
- process $group_256
+ process $group_281
assign \fus_src4_i$66 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $653 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_XER_xer_ca_shiftrot0_2 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
assign \fus_src4_i$66 \xer_src2__data_o
end
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 3 $655
+ wire width 3 $545
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 2 $656
+ wire width 2 $546
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $657
+ cell $or $547
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
- connect \A \read_en$637
- connect \B \read_en$648
- connect \Y $656
+ connect \A \addr_en_XER_xer_ca_spr0_1
+ connect \B \addr_en_XER_xer_ca_shiftrot0_2
+ connect \Y $546
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 2 $658
+ wire width 2 $548
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $659
+ cell $or $549
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
- connect \A \read_en$626
- connect \B $656
- connect \Y $658
+ connect \A \addr_en_XER_xer_ca_alu0_0
+ connect \B $546
+ connect \Y $548
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $pos $660
+ cell $pos $550
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 3
- connect \A $658
- connect \Y $655
+ connect \A $548
+ connect \Y $545
end
- process $group_257
+ process $group_282
assign \xer_src2__ren 3'000
- assign \xer_src2__ren $655
+ assign \xer_src2__ren $545
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204"
wire width 1 \rdflag_XER_xer_ov_0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
- wire width 1 $661
+ wire width 1 $551
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
- cell $and $662
+ cell $and $552
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pdecode2_oe
connect \B \pdecode2_oe_ok
- connect \Y $661
+ connect \Y $551
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
- wire width 1 $663
+ wire width 1 $553
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
- cell $or $664
+ cell $or $554
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $661
+ connect \A $551
connect \B \pdecode2_xer_in
- connect \Y $663
+ connect \Y $553
end
- process $group_258
+ process $group_283
assign \rdflag_XER_xer_ov_0 1'0
- assign \rdflag_XER_xer_ov_0 $663
+ assign \rdflag_XER_xer_ov_0 $553
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$665
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $666
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $667
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$555
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $556
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $557
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$39 [4]
+ connect \A \fus_cu_rd__rel_o$55 [4]
connect \B \fu_enable [5]
- connect \Y $666
+ connect \Y $556
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $668
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $669
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $558
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $559
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $666
+ connect \A $556
connect \B \rdflag_XER_xer_ov_0
- connect \Y $668
+ connect \Y $558
end
- process $group_259
- assign \pick$665 1'0
- assign \pick$665 $668
+ process $group_284
+ assign \pick$555 1'0
+ assign \pick$555 $558
sync init
end
- process $group_260
+ process $group_285
assign \rdpick_XER_xer_ov_i 1'0
- assign \rdpick_XER_xer_ov_i \pick$665
+ assign \rdpick_XER_xer_ov_i \pick$555
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 3 \read_en$670
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 3 $671
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $672
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $673
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_XER_xer_ov_spr0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $560
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $561
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_XER_xer_ov_o
connect \B \rdpick_XER_xer_ov_en_o
- connect \Y $672
+ connect \Y $560
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $674
+ process $group_286
+ assign \rp_XER_xer_ov_spr0_0 1'0
+ assign \rp_XER_xer_ov_spr0_0 $560
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 3 \addr_en_XER_xer_ov_spr0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 3 $562
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $563
parameter \WIDTH 3
connect \A 3'000
connect \B 3'100
- connect \S $672
- connect \Y $671
+ connect \S \rp_XER_xer_ov_spr0_0
+ connect \Y $562
end
- process $group_261
- assign \read_en$670 3'000
- assign \read_en$670 $671
+ process $group_287
+ assign \addr_en_XER_xer_ov_spr0_0 3'000
+ assign \addr_en_XER_xer_ov_spr0_0 $562
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $675
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $676
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_XER_xer_ov_o
- connect \B \rdpick_XER_xer_ov_en_o
- connect \Y $675
- end
- process $group_262
+ process $group_288
assign \fus_src5_i 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $675 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_XER_xer_ov_spr0_0 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
assign \fus_src5_i \xer_src3__data_o
end
sync init
end
- process $group_263
+ process $group_289
assign \xer_src3__ren 3'000
- assign \xer_src3__ren \read_en$670
+ assign \xer_src3__ren \addr_en_XER_xer_ov_spr0_0
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204"
wire width 1 \rdflag_CR_full_cr_0
- process $group_264
+ process $group_290
assign \rdflag_CR_full_cr_0 1'0
assign \rdflag_CR_full_cr_0 \pdecode2_read_cr_whole
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$677
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $678
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $679
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$564
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $565
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $566
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_rd__rel_o$30 [2]
connect \B \fu_enable [1]
- connect \Y $678
+ connect \Y $565
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $680
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $681
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $567
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $568
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $678
+ connect \A $565
connect \B \rdflag_CR_full_cr_0
- connect \Y $680
+ connect \Y $567
end
- process $group_265
- assign \pick$677 1'0
- assign \pick$677 $680
+ process $group_291
+ assign \pick$564 1'0
+ assign \pick$564 $567
sync init
end
- process $group_266
+ process $group_292
assign \rdpick_CR_full_cr_i 1'0
- assign \rdpick_CR_full_cr_i \pick$677
+ assign \rdpick_CR_full_cr_i \pick$564
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 8 \read_en$682
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 8 $683
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $684
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $685
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_CR_full_cr_cr0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $569
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $570
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_CR_full_cr_o
connect \B \rdpick_CR_full_cr_en_o
- connect \Y $684
+ connect \Y $569
+ end
+ process $group_293
+ assign \rp_CR_full_cr_cr0_0 1'0
+ assign \rp_CR_full_cr_cr0_0 $569
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $686
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 8 \addr_en_CR_full_cr_cr0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 8 $571
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $572
parameter \WIDTH 8
connect \A 8'00000000
connect \B 8'11111111
- connect \S $684
- connect \Y $683
+ connect \S \rp_CR_full_cr_cr0_0
+ connect \Y $571
end
- process $group_267
- assign \read_en$682 8'00000000
- assign \read_en$682 $683
+ process $group_294
+ assign \addr_en_CR_full_cr_cr0_0 8'00000000
+ assign \addr_en_CR_full_cr_cr0_0 $571
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $687
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $688
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_CR_full_cr_o
- connect \B \rdpick_CR_full_cr_en_o
- connect \Y $687
- end
- process $group_268
+ process $group_295
assign \fus_src3_i$67 32'00000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $687 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_CR_full_cr_cr0_0 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
assign \fus_src3_i$67 \cr_full_rd__data_o
end
sync init
end
- process $group_269
+ process $group_296
assign \cr_full_rd__ren 8'00000000
- assign \cr_full_rd__ren \read_en$682
+ assign \cr_full_rd__ren \addr_en_CR_full_cr_cr0_0
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204"
wire width 1 \rdflag_CR_cr_a_0
- process $group_270
+ process $group_297
assign \rdflag_CR_cr_a_0 1'0
assign \rdflag_CR_cr_a_0 \pdecode2_cr_in1_ok
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$689
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $690
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $691
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$573
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $574
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $575
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_rd__rel_o$30 [3]
connect \B \fu_enable [1]
- connect \Y $690
+ connect \Y $574
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $576
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $577
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $574
+ connect \B \rdflag_CR_cr_a_0
+ connect \Y $576
+ end
+ process $group_298
+ assign \pick$573 1'0
+ assign \pick$573 $576
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$578
+ process $group_299
+ assign \rdpick_CR_cr_a_i 2'00
+ assign \rdpick_CR_cr_a_i [0] \pick$573
+ assign \rdpick_CR_cr_a_i [1] \pick$578
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $692
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $693
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_CR_cr_a_cr0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $579
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $580
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $690
- connect \B \rdflag_CR_cr_a_0
- connect \Y $692
- end
- process $group_271
- assign \pick$689 1'0
- assign \pick$689 $692
- sync init
+ connect \A \rdpick_CR_cr_a_o [0]
+ connect \B \rdpick_CR_cr_a_en_o
+ connect \Y $579
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$694
- process $group_272
- assign \rdpick_CR_cr_a_i 2'00
- assign \rdpick_CR_cr_a_i [0] \pick$689
- assign \rdpick_CR_cr_a_i [1] \pick$694
+ process $group_300
+ assign \rp_CR_cr_a_cr0_0 1'0
+ assign \rp_CR_cr_a_cr0_0 $579
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 16 \read_en$695
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 16 \addr_en_CR_cr_a_cr0_0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
- wire width 4 $696
+ wire width 4 $581
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
- cell $sub $697
+ cell $sub $582
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A 3'111
connect \B \pdecode2_cr_in1
- connect \Y $696
+ connect \Y $581
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
- wire width 16 $698
+ wire width 16 $583
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
- cell $sshl $699
+ cell $sshl $584
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A 1'1
- connect \B $696
- connect \Y $698
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 16 $700
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $701
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $702
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_CR_cr_a_o [0]
- connect \B \rdpick_CR_cr_a_en_o
- connect \Y $701
+ connect \B $581
+ connect \Y $583
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $703
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 16 $585
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $586
parameter \WIDTH 16
connect \A 16'0000000000000000
- connect \B $698
- connect \S $701
- connect \Y $700
+ connect \B $583
+ connect \S \rp_CR_cr_a_cr0_0
+ connect \Y $585
end
- process $group_273
- assign \read_en$695 16'0000000000000000
- assign \read_en$695 $700
+ process $group_301
+ assign \addr_en_CR_cr_a_cr0_0 16'0000000000000000
+ assign \addr_en_CR_cr_a_cr0_0 $585
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $704
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $705
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_CR_cr_a_o [0]
- connect \B \rdpick_CR_cr_a_en_o
- connect \Y $704
- end
- process $group_274
+ process $group_302
assign \fus_src4_i$68 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $704 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_CR_cr_a_cr0_0 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
assign \fus_src4_i$68 \cr_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $706
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $707
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $587
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $588
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_rd__rel_o$69 [2]
connect \B \fu_enable [2]
- connect \Y $706
+ connect \Y $587
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $708
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $709
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $589
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $590
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $706
+ connect \A $587
connect \B \rdflag_CR_cr_a_0
- connect \Y $708
+ connect \Y $589
end
- process $group_275
- assign \pick$694 1'0
- assign \pick$694 $708
+ process $group_303
+ assign \pick$578 1'0
+ assign \pick$578 $589
sync init
end
- process $group_276
+ process $group_304
assign \fus_cu_rd__go_i$70 3'000
assign \fus_cu_rd__go_i$70 [2] \rdpick_CR_cr_a_o [1]
assign \fus_cu_rd__go_i$70 [0] \rdpick_FAST_fast1_o [0]
assign \fus_cu_rd__go_i$70 [1] \rdpick_FAST_fast1_o [3]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 16 \read_en$710
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_CR_cr_a_branch0_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $591
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $592
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \rdpick_CR_cr_a_o [1]
+ connect \B \rdpick_CR_cr_a_en_o
+ connect \Y $591
+ end
+ process $group_305
+ assign \rp_CR_cr_a_branch0_1 1'0
+ assign \rp_CR_cr_a_branch0_1 $591
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 16 \addr_en_CR_cr_a_branch0_1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
- wire width 4 $711
+ wire width 4 $593
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
- cell $sub $712
+ cell $sub $594
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A 3'111
connect \B \pdecode2_cr_in1
- connect \Y $711
+ connect \Y $593
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
- wire width 16 $713
+ wire width 16 $595
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
- cell $sshl $714
+ cell $sshl $596
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A 1'1
- connect \B $711
- connect \Y $713
+ connect \B $593
+ connect \Y $595
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 16 $715
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $716
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $717
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_CR_cr_a_o [1]
- connect \B \rdpick_CR_cr_a_en_o
- connect \Y $716
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $718
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 16 $597
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $598
parameter \WIDTH 16
connect \A 16'0000000000000000
- connect \B $713
- connect \S $716
- connect \Y $715
+ connect \B $595
+ connect \S \rp_CR_cr_a_branch0_1
+ connect \Y $597
end
- process $group_277
- assign \read_en$710 16'0000000000000000
- assign \read_en$710 $715
+ process $group_306
+ assign \addr_en_CR_cr_a_branch0_1 16'0000000000000000
+ assign \addr_en_CR_cr_a_branch0_1 $597
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $719
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $720
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_CR_cr_a_o [1]
- connect \B \rdpick_CR_cr_a_en_o
- connect \Y $719
- end
- process $group_278
+ process $group_307
assign \fus_src3_i$71 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $719 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_CR_cr_a_branch0_1 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
assign \fus_src3_i$71 \cr_src1__data_o
end
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 16 $721
+ wire width 16 $599
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 16 $722
+ wire width 16 $600
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $723
+ cell $or $601
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
- connect \A \read_en$695
- connect \B \read_en$710
- connect \Y $722
+ connect \A \addr_en_CR_cr_a_cr0_0
+ connect \B \addr_en_CR_cr_a_branch0_1
+ connect \Y $600
end
- connect $721 $722
- process $group_279
+ connect $599 $600
+ process $group_308
assign \cr_src1__ren 8'00000000
- assign \cr_src1__ren $721 [7:0]
+ assign \cr_src1__ren $599 [7:0]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204"
wire width 1 \rdflag_CR_cr_b_0
- process $group_280
+ process $group_309
assign \rdflag_CR_cr_b_0 1'0
assign \rdflag_CR_cr_b_0 \pdecode2_cr_in2_ok
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$724
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $725
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $726
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$602
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $603
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $604
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_rd__rel_o$30 [4]
connect \B \fu_enable [1]
- connect \Y $725
+ connect \Y $603
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $727
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $728
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $605
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $606
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $725
+ connect \A $603
connect \B \rdflag_CR_cr_b_0
- connect \Y $727
+ connect \Y $605
end
- process $group_281
- assign \pick$724 1'0
- assign \pick$724 $727
+ process $group_310
+ assign \pick$602 1'0
+ assign \pick$602 $605
sync init
end
- process $group_282
+ process $group_311
assign \rdpick_CR_cr_b_i 1'0
- assign \rdpick_CR_cr_b_i \pick$724
+ assign \rdpick_CR_cr_b_i \pick$602
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_CR_cr_b_cr0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $607
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $608
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \rdpick_CR_cr_b_o
+ connect \B \rdpick_CR_cr_b_en_o
+ connect \Y $607
+ end
+ process $group_312
+ assign \rp_CR_cr_b_cr0_0 1'0
+ assign \rp_CR_cr_b_cr0_0 $607
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 16 \read_en$729
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 16 \addr_en_CR_cr_b_cr0_0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
- wire width 4 $730
+ wire width 4 $609
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
- cell $sub $731
+ cell $sub $610
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A 3'111
connect \B \pdecode2_cr_in2
- connect \Y $730
+ connect \Y $609
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
- wire width 16 $732
+ wire width 16 $611
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
- cell $sshl $733
+ cell $sshl $612
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A 1'1
- connect \B $730
- connect \Y $732
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 16 $734
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $735
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $736
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_CR_cr_b_o
- connect \B \rdpick_CR_cr_b_en_o
- connect \Y $735
+ connect \B $609
+ connect \Y $611
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $737
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 16 $613
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $614
parameter \WIDTH 16
connect \A 16'0000000000000000
- connect \B $732
- connect \S $735
- connect \Y $734
+ connect \B $611
+ connect \S \rp_CR_cr_b_cr0_0
+ connect \Y $613
end
- process $group_283
- assign \read_en$729 16'0000000000000000
- assign \read_en$729 $734
+ process $group_313
+ assign \addr_en_CR_cr_b_cr0_0 16'0000000000000000
+ assign \addr_en_CR_cr_b_cr0_0 $613
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $738
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $739
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_CR_cr_b_o
- connect \B \rdpick_CR_cr_b_en_o
- connect \Y $738
- end
- process $group_284
+ process $group_314
assign \fus_src5_i$72 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $738 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_CR_cr_b_cr0_0 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
assign \fus_src5_i$72 \cr_src2__data_o
end
sync init
end
- process $group_285
+ process $group_315
assign \cr_src2__ren 8'00000000
- assign \cr_src2__ren \read_en$729 [7:0]
+ assign \cr_src2__ren \addr_en_CR_cr_b_cr0_0 [7:0]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204"
wire width 1 \rdflag_CR_cr_c_0
- process $group_286
+ process $group_316
assign \rdflag_CR_cr_c_0 1'0
assign \rdflag_CR_cr_c_0 \pdecode2_cr_in2_ok$1
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$740
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $741
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $742
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$615
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $616
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $617
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_rd__rel_o$30 [5]
connect \B \fu_enable [1]
- connect \Y $741
+ connect \Y $616
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $743
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $744
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $618
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $619
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $741
+ connect \A $616
connect \B \rdflag_CR_cr_c_0
- connect \Y $743
+ connect \Y $618
end
- process $group_287
- assign \pick$740 1'0
- assign \pick$740 $743
+ process $group_317
+ assign \pick$615 1'0
+ assign \pick$615 $618
sync init
end
- process $group_288
+ process $group_318
assign \rdpick_CR_cr_c_i 1'0
- assign \rdpick_CR_cr_c_i \pick$740
+ assign \rdpick_CR_cr_c_i \pick$615
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_CR_cr_c_cr0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $620
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $621
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \rdpick_CR_cr_c_o
+ connect \B \rdpick_CR_cr_c_en_o
+ connect \Y $620
+ end
+ process $group_319
+ assign \rp_CR_cr_c_cr0_0 1'0
+ assign \rp_CR_cr_c_cr0_0 $620
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 16 \read_en$745
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 16 \addr_en_CR_cr_c_cr0_0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
- wire width 4 $746
+ wire width 4 $622
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
- cell $sub $747
+ cell $sub $623
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A 3'111
connect \B \pdecode2_cr_in2$2
- connect \Y $746
+ connect \Y $622
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
- wire width 16 $748
+ wire width 16 $624
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
- cell $sshl $749
+ cell $sshl $625
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A 1'1
- connect \B $746
- connect \Y $748
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 16 $750
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $751
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $752
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_CR_cr_c_o
- connect \B \rdpick_CR_cr_c_en_o
- connect \Y $751
+ connect \B $622
+ connect \Y $624
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $753
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 16 $626
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $627
parameter \WIDTH 16
connect \A 16'0000000000000000
- connect \B $748
- connect \S $751
- connect \Y $750
+ connect \B $624
+ connect \S \rp_CR_cr_c_cr0_0
+ connect \Y $626
end
- process $group_289
- assign \read_en$745 16'0000000000000000
- assign \read_en$745 $750
+ process $group_320
+ assign \addr_en_CR_cr_c_cr0_0 16'0000000000000000
+ assign \addr_en_CR_cr_c_cr0_0 $626
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $754
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $755
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_CR_cr_c_o
- connect \B \rdpick_CR_cr_c_en_o
- connect \Y $754
- end
- process $group_290
+ process $group_321
assign \fus_src6_i$73 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $754 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_CR_cr_c_cr0_0 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
assign \fus_src6_i$73 \cr_src3__data_o
end
sync init
end
- process $group_291
+ process $group_322
assign \cr_src3__ren 8'00000000
- assign \cr_src3__ren \read_en$745 [7:0]
+ assign \cr_src3__ren \addr_en_CR_cr_c_cr0_0 [7:0]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204"
wire width 1 \rdflag_FAST_fast1_0
- process $group_292
+ process $group_323
assign \rdflag_FAST_fast1_0 1'0
assign \rdflag_FAST_fast1_0 \pdecode2_fast1_ok
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204"
wire width 1 \rdflag_FAST_fast1_1
- process $group_293
+ process $group_324
assign \rdflag_FAST_fast1_1 1'0
assign \rdflag_FAST_fast1_1 \pdecode2_fast2_ok
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$756
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $757
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $758
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$628
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $629
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $630
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_rd__rel_o$69 [0]
connect \B \fu_enable [2]
- connect \Y $757
+ connect \Y $629
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $759
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $760
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $631
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $632
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $757
+ connect \A $629
connect \B \rdflag_FAST_fast1_0
- connect \Y $759
+ connect \Y $631
end
- process $group_294
- assign \pick$756 1'0
- assign \pick$756 $759
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$761
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$762
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$763
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$764
- process $group_295
+ process $group_325
+ assign \pick$628 1'0
+ assign \pick$628 $631
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$633
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$634
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$635
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$636
+ process $group_326
assign \rdpick_FAST_fast1_i 5'00000
- assign \rdpick_FAST_fast1_i [0] \pick$756
- assign \rdpick_FAST_fast1_i [1] \pick$761
- assign \rdpick_FAST_fast1_i [2] \pick$762
- assign \rdpick_FAST_fast1_i [3] \pick$763
- assign \rdpick_FAST_fast1_i [4] \pick$764
+ assign \rdpick_FAST_fast1_i [0] \pick$628
+ assign \rdpick_FAST_fast1_i [1] \pick$633
+ assign \rdpick_FAST_fast1_i [2] \pick$634
+ assign \rdpick_FAST_fast1_i [3] \pick$635
+ assign \rdpick_FAST_fast1_i [4] \pick$636
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 8 \read_en$765
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
- wire width 8 $766
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
- cell $sshl $767
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 3
- parameter \Y_WIDTH 8
- connect \A 1'1
- connect \B \pdecode2_fast1
- connect \Y $766
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 8 $768
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $769
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $770
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_FAST_fast1_branch0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $637
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $638
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_FAST_fast1_o [0]
connect \B \rdpick_FAST_fast1_en_o
- connect \Y $769
+ connect \Y $637
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $771
- parameter \WIDTH 8
- connect \A 8'00000000
- connect \B $766
- connect \S $769
- connect \Y $768
- end
- process $group_296
- assign \read_en$765 8'00000000
- assign \read_en$765 $768
+ process $group_327
+ assign \rp_FAST_fast1_branch0_0 1'0
+ assign \rp_FAST_fast1_branch0_0 $637
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $772
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $773
+ wire width 8 \addr_en_FAST_fast1_branch0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
+ wire width 8 $639
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
+ cell $sshl $640
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_FAST_fast1_o [0]
- connect \B \rdpick_FAST_fast1_en_o
- connect \Y $772
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 8
+ connect \A 1'1
+ connect \B \pdecode2_fast1
+ connect \Y $639
end
- process $group_297
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 8 $641
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $642
+ parameter \WIDTH 8
+ connect \A 8'00000000
+ connect \B $639
+ connect \S \rp_FAST_fast1_branch0_0
+ connect \Y $641
+ end
+ process $group_328
+ assign \addr_en_FAST_fast1_branch0_0 8'00000000
+ assign \addr_en_FAST_fast1_branch0_0 $641
+ sync init
+ end
+ process $group_329
assign \fus_src1_i$74 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $772 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_FAST_fast1_branch0_0 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
assign \fus_src1_i$74 \fast_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $774
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $775
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $643
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $644
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_rd__rel_o$33 [2]
connect \B \fu_enable [3]
- connect \Y $774
+ connect \Y $643
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $776
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $777
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $645
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $646
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $774
+ connect \A $643
connect \B \rdflag_FAST_fast1_0
- connect \Y $776
+ connect \Y $645
end
- process $group_298
- assign \pick$761 1'0
- assign \pick$761 $776
+ process $group_330
+ assign \pick$633 1'0
+ assign \pick$633 $645
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 8 \read_en$778
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
- wire width 8 $779
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
- cell $sshl $780
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 3
- parameter \Y_WIDTH 8
- connect \A 1'1
- connect \B \pdecode2_fast1
- connect \Y $779
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 8 $781
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $782
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $783
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_FAST_fast1_trap0_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $647
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $648
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_FAST_fast1_o [1]
connect \B \rdpick_FAST_fast1_en_o
- connect \Y $782
+ connect \Y $647
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $784
- parameter \WIDTH 8
- connect \A 8'00000000
- connect \B $779
- connect \S $782
- connect \Y $781
- end
- process $group_299
- assign \read_en$778 8'00000000
- assign \read_en$778 $781
+ process $group_331
+ assign \rp_FAST_fast1_trap0_1 1'0
+ assign \rp_FAST_fast1_trap0_1 $647
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $785
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $786
+ wire width 8 \addr_en_FAST_fast1_trap0_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
+ wire width 8 $649
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
+ cell $sshl $650
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_FAST_fast1_o [1]
- connect \B \rdpick_FAST_fast1_en_o
- connect \Y $785
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 8
+ connect \A 1'1
+ connect \B \pdecode2_fast1
+ connect \Y $649
end
- process $group_300
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 8 $651
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $652
+ parameter \WIDTH 8
+ connect \A 8'00000000
+ connect \B $649
+ connect \S \rp_FAST_fast1_trap0_1
+ connect \Y $651
+ end
+ process $group_332
+ assign \addr_en_FAST_fast1_trap0_1 8'00000000
+ assign \addr_en_FAST_fast1_trap0_1 $651
+ sync init
+ end
+ process $group_333
assign \fus_src3_i$75 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $785 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_FAST_fast1_trap0_1 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
assign \fus_src3_i$75 \fast_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $787
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $788
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $653
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $654
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$39 [2]
+ connect \A \fus_cu_rd__rel_o$55 [2]
connect \B \fu_enable [5]
- connect \Y $787
+ connect \Y $653
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $789
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $790
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $655
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $656
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $787
+ connect \A $653
connect \B \rdflag_FAST_fast1_0
- connect \Y $789
+ connect \Y $655
end
- process $group_301
- assign \pick$762 1'0
- assign \pick$762 $789
+ process $group_334
+ assign \pick$634 1'0
+ assign \pick$634 $655
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 8 \read_en$791
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
- wire width 8 $792
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
- cell $sshl $793
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 3
- parameter \Y_WIDTH 8
- connect \A 1'1
- connect \B \pdecode2_fast1
- connect \Y $792
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 8 $794
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $795
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $796
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_FAST_fast1_spr0_2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $657
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $658
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_FAST_fast1_o [2]
connect \B \rdpick_FAST_fast1_en_o
- connect \Y $795
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $797
- parameter \WIDTH 8
- connect \A 8'00000000
- connect \B $792
- connect \S $795
- connect \Y $794
+ connect \Y $657
end
- process $group_302
- assign \read_en$791 8'00000000
- assign \read_en$791 $794
+ process $group_335
+ assign \rp_FAST_fast1_spr0_2 1'0
+ assign \rp_FAST_fast1_spr0_2 $657
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $798
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $799
+ wire width 8 \addr_en_FAST_fast1_spr0_2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
+ wire width 8 $659
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
+ cell $sshl $660
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_FAST_fast1_o [2]
- connect \B \rdpick_FAST_fast1_en_o
- connect \Y $798
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 8
+ connect \A 1'1
+ connect \B \pdecode2_fast1
+ connect \Y $659
end
- process $group_303
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 8 $661
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $662
+ parameter \WIDTH 8
+ connect \A 8'00000000
+ connect \B $659
+ connect \S \rp_FAST_fast1_spr0_2
+ connect \Y $661
+ end
+ process $group_336
+ assign \addr_en_FAST_fast1_spr0_2 8'00000000
+ assign \addr_en_FAST_fast1_spr0_2 $661
+ sync init
+ end
+ process $group_337
assign \fus_src3_i$76 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $798 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_FAST_fast1_spr0_2 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
assign \fus_src3_i$76 \fast_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $800
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $801
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $663
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $664
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_rd__rel_o$69 [1]
connect \B \fu_enable [2]
- connect \Y $800
+ connect \Y $663
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $802
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $803
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $665
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $666
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $800
+ connect \A $663
connect \B \rdflag_FAST_fast1_1
- connect \Y $802
+ connect \Y $665
end
- process $group_304
- assign \pick$763 1'0
- assign \pick$763 $802
+ process $group_338
+ assign \pick$635 1'0
+ assign \pick$635 $665
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 8 \read_en$804
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108"
- wire width 8 $805
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108"
- cell $sshl $806
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 3
- parameter \Y_WIDTH 8
- connect \A 1'1
- connect \B \pdecode2_fast2
- connect \Y $805
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 8 $807
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $808
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $809
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_FAST_fast1_branch0_3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $667
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $668
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_FAST_fast1_o [3]
connect \B \rdpick_FAST_fast1_en_o
- connect \Y $808
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $810
- parameter \WIDTH 8
- connect \A 8'00000000
- connect \B $805
- connect \S $808
- connect \Y $807
+ connect \Y $667
end
- process $group_305
- assign \read_en$804 8'00000000
- assign \read_en$804 $807
+ process $group_339
+ assign \rp_FAST_fast1_branch0_3 1'0
+ assign \rp_FAST_fast1_branch0_3 $667
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $811
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $812
+ wire width 8 \addr_en_FAST_fast1_branch0_3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108"
+ wire width 8 $669
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108"
+ cell $sshl $670
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_FAST_fast1_o [3]
- connect \B \rdpick_FAST_fast1_en_o
- connect \Y $811
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 8
+ connect \A 1'1
+ connect \B \pdecode2_fast2
+ connect \Y $669
end
- process $group_306
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 8 $671
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $672
+ parameter \WIDTH 8
+ connect \A 8'00000000
+ connect \B $669
+ connect \S \rp_FAST_fast1_branch0_3
+ connect \Y $671
+ end
+ process $group_340
+ assign \addr_en_FAST_fast1_branch0_3 8'00000000
+ assign \addr_en_FAST_fast1_branch0_3 $671
+ sync init
+ end
+ process $group_341
assign \fus_src2_i$77 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $811 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_FAST_fast1_branch0_3 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
assign \fus_src2_i$77 \fast_src1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $813
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $814
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $673
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $674
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_rd__rel_o$33 [3]
connect \B \fu_enable [3]
- connect \Y $813
+ connect \Y $673
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $815
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $816
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $675
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $676
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $813
+ connect \A $673
connect \B \rdflag_FAST_fast1_1
- connect \Y $815
+ connect \Y $675
end
- process $group_307
- assign \pick$764 1'0
- assign \pick$764 $815
+ process $group_342
+ assign \pick$636 1'0
+ assign \pick$636 $675
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 8 \read_en$817
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108"
- wire width 8 $818
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108"
- cell $sshl $819
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 3
- parameter \Y_WIDTH 8
- connect \A 1'1
- connect \B \pdecode2_fast2
- connect \Y $818
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 8 $820
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $821
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $822
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_FAST_fast1_trap0_4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $677
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $678
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_FAST_fast1_o [4]
connect \B \rdpick_FAST_fast1_en_o
- connect \Y $821
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $823
- parameter \WIDTH 8
- connect \A 8'00000000
- connect \B $818
- connect \S $821
- connect \Y $820
+ connect \Y $677
end
- process $group_308
- assign \read_en$817 8'00000000
- assign \read_en$817 $820
+ process $group_343
+ assign \rp_FAST_fast1_trap0_4 1'0
+ assign \rp_FAST_fast1_trap0_4 $677
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $824
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $825
+ wire width 8 \addr_en_FAST_fast1_trap0_4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108"
+ wire width 8 $679
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108"
+ cell $sshl $680
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_FAST_fast1_o [4]
- connect \B \rdpick_FAST_fast1_en_o
- connect \Y $824
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 8
+ connect \A 1'1
+ connect \B \pdecode2_fast2
+ connect \Y $679
end
- process $group_309
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 8 $681
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $682
+ parameter \WIDTH 8
+ connect \A 8'00000000
+ connect \B $679
+ connect \S \rp_FAST_fast1_trap0_4
+ connect \Y $681
+ end
+ process $group_344
+ assign \addr_en_FAST_fast1_trap0_4 8'00000000
+ assign \addr_en_FAST_fast1_trap0_4 $681
+ sync init
+ end
+ process $group_345
assign \fus_src4_i$78 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $824 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_FAST_fast1_trap0_4 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
assign \fus_src4_i$78 \fast_src1__data_o
end
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 8 $826
+ wire width 8 $683
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 8 $827
+ wire width 8 $684
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $828
+ cell $or $685
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A \read_en$765
- connect \B \read_en$778
- connect \Y $827
+ connect \A \addr_en_FAST_fast1_branch0_0
+ connect \B \addr_en_FAST_fast1_trap0_1
+ connect \Y $684
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 8 $829
+ wire width 8 $686
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $830
+ cell $or $687
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A \read_en$804
- connect \B \read_en$817
- connect \Y $829
+ connect \A \addr_en_FAST_fast1_branch0_3
+ connect \B \addr_en_FAST_fast1_trap0_4
+ connect \Y $686
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 8 $831
+ wire width 8 $688
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $832
+ cell $or $689
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A \read_en$791
- connect \B $829
- connect \Y $831
+ connect \A \addr_en_FAST_fast1_spr0_2
+ connect \B $686
+ connect \Y $688
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 8 $833
+ wire width 8 $690
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $834
+ cell $or $691
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $827
- connect \B $831
- connect \Y $833
+ connect \A $684
+ connect \B $688
+ connect \Y $690
end
- connect $826 $833
- process $group_310
+ connect $683 $690
+ process $group_346
assign \fast_src1__ren 5'00000
- assign \fast_src1__ren $826 [4:0]
+ assign \fast_src1__ren $683 [4:0]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204"
wire width 1 \rdflag_SPR_spr1_0
- process $group_311
+ process $group_347
assign \rdflag_SPR_spr1_0 1'0
assign \rdflag_SPR_spr1_0 \pdecode2_spr1_ok
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
- wire width 1 \pick$835
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $836
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $837
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227"
+ wire width 1 \pick$692
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $693
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $694
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_cu_rd__rel_o$39 [1]
+ connect \A \fus_cu_rd__rel_o$55 [1]
connect \B \fu_enable [5]
- connect \Y $836
+ connect \Y $693
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- wire width 1 $838
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
- cell $and $839
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ wire width 1 $695
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228"
+ cell $and $696
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $836
+ connect \A $693
connect \B \rdflag_SPR_spr1_0
- connect \Y $838
+ connect \Y $695
end
- process $group_312
- assign \pick$835 1'0
- assign \pick$835 $838
+ process $group_348
+ assign \pick$692 1'0
+ assign \pick$692 $695
sync init
end
- process $group_313
+ process $group_349
assign \rdpick_SPR_spr1_i 1'0
- assign \rdpick_SPR_spr1_i \pick$835
+ assign \rdpick_SPR_spr1_i \pick$692
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:232"
- wire width 10 \read_en$840
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 10 $841
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- wire width 1 $842
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $and $843
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237"
+ wire width 1 \rp_SPR_spr1_spr0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ wire width 1 $697
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239"
+ cell $and $698
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rdpick_SPR_spr1_o
connect \B \rdpick_SPR_spr1_en_o
- connect \Y $842
+ connect \Y $697
+ end
+ process $group_350
+ assign \rp_SPR_spr1_spr0_0 1'0
+ assign \rp_SPR_spr1_spr0_0 $697
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
- cell $mux $844
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 10 \addr_en_SPR_spr1_spr0_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ wire width 10 $699
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
+ cell $mux $700
parameter \WIDTH 10
connect \A 10'0000000000
connect \B \pdecode2_spr1
- connect \S $842
- connect \Y $841
+ connect \S \rp_SPR_spr1_spr0_0
+ connect \Y $699
end
- process $group_314
- assign \read_en$840 10'0000000000
- assign \read_en$840 $841
+ process $group_351
+ assign \addr_en_SPR_spr1_spr0_0 10'0000000000
+ assign \addr_en_SPR_spr1_spr0_0 $699
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- wire width 1 $845
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- cell $and $846
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rdpick_SPR_spr1_o
- connect \B \rdpick_SPR_spr1_en_o
- connect \Y $845
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfiles.py:158"
- wire width 64 $memory_w_data
- process $group_315
+ process $group_352
assign \fus_src2_i$79 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
- switch { $845 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
+ switch { \rp_SPR_spr1_spr0_0 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247"
case 1'1
- assign \fus_src2_i$79 $memory_w_data
+ assign \fus_src2_i$79 \spr_spr1__data_o
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfiles.py:158"
- wire width 1 $memory_w_en
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 10 \write_en
- process $group_316
- assign $memory_w_en 1'0
- assign $memory_w_en \read_en$840 [0]
- assign $memory_w_en \write_en [0]
+ process $group_353
+ assign \spr_spr1__addr 7'0000000
+ assign \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [6:0]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262"
+ wire width 1 $701
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262"
+ cell $reduce_bool $702
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A { \rp_SPR_spr1_spr0_0 }
+ connect \Y $701
+ end
+ process $group_354
+ assign \spr_spr1__ren 1'0
+ assign \spr_spr1__ren $701
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_alu0_o_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $847
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $848
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $703
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $704
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_o_ok
connect \B \fus_cu_busy_o
- connect \Y $847
+ connect \Y $703
end
- process $group_317
+ process $group_355
assign \wrflag_alu0_o_0 1'0
- assign \wrflag_alu0_o_0 $847
+ assign \wrflag_alu0_o_0 $703
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $849
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $850
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $705
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $706
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o [0]
connect \B \fu_enable [0]
- connect \Y $849
+ connect \Y $705
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $851
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $852
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $707
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $708
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$81 [0]
connect \B \fu_enable [1]
- connect \Y $851
+ connect \Y $707
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $853
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $854
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $709
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $710
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$84 [0]
connect \B \fu_enable [3]
- connect \Y $853
+ connect \Y $709
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $855
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $856
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $711
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $712
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$87 [0]
connect \B \fu_enable [4]
- connect \Y $855
+ connect \Y $711
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $857
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $858
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $713
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $714
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$90 [0]
connect \B \fu_enable [5]
- connect \Y $857
+ connect \Y $713
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $859
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $860
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $715
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $716
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$93 [0]
connect \B \fu_enable [6]
- connect \Y $859
+ connect \Y $715
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $861
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $862
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $717
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $718
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$96 [0]
connect \B \fu_enable [7]
- connect \Y $861
+ connect \Y $717
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $863
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $864
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $719
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $720
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$99 [0]
connect \B \fu_enable [8]
- connect \Y $863
+ connect \Y $719
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $865
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $866
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $721
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $722
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$101 [0]
connect \B \fu_enable [9]
- connect \Y $865
+ connect \Y $721
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $867
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $868
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $723
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $724
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$101 [1]
connect \B \fu_enable [9]
- connect \Y $867
+ connect \Y $723
end
- process $group_318
+ process $group_356
assign \wrpick_INT_o_i 10'0000000000
- assign \wrpick_INT_o_i [0] $849
- assign \wrpick_INT_o_i [1] $851
- assign \wrpick_INT_o_i [2] $853
- assign \wrpick_INT_o_i [3] $855
- assign \wrpick_INT_o_i [4] $857
- assign \wrpick_INT_o_i [5] $859
- assign \wrpick_INT_o_i [6] $861
- assign \wrpick_INT_o_i [7] $863
- assign \wrpick_INT_o_i [8] $865
- assign \wrpick_INT_o_i [9] $867
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+ assign \wrpick_INT_o_i [0] $705
+ assign \wrpick_INT_o_i [1] $707
+ assign \wrpick_INT_o_i [2] $709
+ assign \wrpick_INT_o_i [3] $711
+ assign \wrpick_INT_o_i [4] $713
+ assign \wrpick_INT_o_i [5] $715
+ assign \wrpick_INT_o_i [6] $717
+ assign \wrpick_INT_o_i [7] $719
+ assign \wrpick_INT_o_i [8] $721
+ assign \wrpick_INT_o_i [9] $723
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
wire width 1 \wr_pick
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $869
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $870
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $725
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $726
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [0]
connect \B \wrpick_INT_o_en_o
- connect \Y $869
+ connect \Y $725
end
- process $group_319
+ process $group_357
assign \wr_pick 1'0
- assign \wr_pick $869
+ assign \wr_pick $725
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
wire width 1 \wr_pick_dly
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
wire width 1 \wr_pick_dly$next
- process $group_320
+ process $group_358
assign \wr_pick_dly$next \wr_pick_dly
assign \wr_pick_dly$next \wr_pick
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
wire width 1 \wr_pick_rise
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $871
+ wire width 1 $727
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $872
+ cell $not $728
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_pick_dly
- connect \Y $871
+ connect \Y $727
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $873
+ wire width 1 $729
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $874
+ cell $and $730
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_pick
- connect \B $871
- connect \Y $873
+ connect \B $727
+ connect \Y $729
end
- process $group_321
+ process $group_359
assign \wr_pick_rise 1'0
- assign \wr_pick_rise $873
+ assign \wr_pick_rise $729
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$875
+ wire width 1 \wr_pick_rise$731
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$876
+ wire width 1 \wr_pick_rise$732
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$877
+ wire width 1 \wr_pick_rise$733
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$878
- process $group_322
+ wire width 1 \wr_pick_rise$734
+ process $group_360
assign \fus_cu_wr__go_i 5'00000
assign \fus_cu_wr__go_i [0] \wr_pick_rise
- assign \fus_cu_wr__go_i [1] \wr_pick_rise$875
- assign \fus_cu_wr__go_i [2] \wr_pick_rise$876
- assign \fus_cu_wr__go_i [3] \wr_pick_rise$877
- assign \fus_cu_wr__go_i [4] \wr_pick_rise$878
+ assign \fus_cu_wr__go_i [1] \wr_pick_rise$731
+ assign \fus_cu_wr__go_i [2] \wr_pick_rise$732
+ assign \fus_cu_wr__go_i [3] \wr_pick_rise$733
+ assign \fus_cu_wr__go_i [4] \wr_pick_rise$734
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 32 \write_en$879
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
- wire width 32 $880
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
- cell $sshl $881
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_rego
- connect \Y $880
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 32 $882
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $883
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $884
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $735
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $736
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_pick
connect \B \wrpick_INT_o_en_o
- connect \Y $883
+ connect \Y $735
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $885
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $880
- connect \S $883
- connect \Y $882
+ process $group_361
+ assign \wp 1'0
+ assign \wp $735
+ sync init
end
- process $group_323
- assign \write_en$879 32'00000000000000000000000000000000
- assign \write_en$879 $882
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 5 \addr_en
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 5 $737
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $738
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_rego
+ connect \S \wp
+ connect \Y $737
+ end
+ process $group_362
+ assign \addr_en 5'00000
+ assign \addr_en $737
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_cr0_o_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $886
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $887
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $739
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $740
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_o_ok$80
connect \B \fus_cu_busy_o$4
- connect \Y $886
+ connect \Y $739
end
- process $group_324
+ process $group_363
assign \wrflag_cr0_o_0 1'0
- assign \wrflag_cr0_o_0 $886
+ assign \wrflag_cr0_o_0 $739
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$888
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $889
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $890
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$741
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $742
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $743
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [1]
connect \B \wrpick_INT_o_en_o
- connect \Y $889
+ connect \Y $742
end
- process $group_325
- assign \wr_pick$888 1'0
- assign \wr_pick$888 $889
+ process $group_364
+ assign \wr_pick$741 1'0
+ assign \wr_pick$741 $742
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$891
+ wire width 1 \wr_pick_dly$744
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$891$next
- process $group_326
- assign \wr_pick_dly$891$next \wr_pick_dly$891
- assign \wr_pick_dly$891$next \wr_pick$888
+ wire width 1 \wr_pick_dly$744$next
+ process $group_365
+ assign \wr_pick_dly$744$next \wr_pick_dly$744
+ assign \wr_pick_dly$744$next \wr_pick$741
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$891$next 1'0
+ assign \wr_pick_dly$744$next 1'0
end
sync init
- update \wr_pick_dly$891 1'0
+ update \wr_pick_dly$744 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$891 \wr_pick_dly$891$next
+ update \wr_pick_dly$744 \wr_pick_dly$744$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$892
+ wire width 1 \wr_pick_rise$745
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $893
+ wire width 1 $746
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $894
+ cell $not $747
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$891
- connect \Y $893
+ connect \A \wr_pick_dly$744
+ connect \Y $746
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $895
+ wire width 1 $748
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $896
+ cell $and $749
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$888
- connect \B $893
- connect \Y $895
+ connect \A \wr_pick$741
+ connect \B $746
+ connect \Y $748
end
- process $group_327
- assign \wr_pick_rise$892 1'0
- assign \wr_pick_rise$892 $895
+ process $group_366
+ assign \wr_pick_rise$745 1'0
+ assign \wr_pick_rise$745 $748
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$897
+ wire width 1 \wr_pick_rise$750
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$898
- process $group_328
+ wire width 1 \wr_pick_rise$751
+ process $group_367
assign \fus_cu_wr__go_i$82 3'000
- assign \fus_cu_wr__go_i$82 [0] \wr_pick_rise$892
- assign \fus_cu_wr__go_i$82 [1] \wr_pick_rise$897
- assign \fus_cu_wr__go_i$82 [2] \wr_pick_rise$898
+ assign \fus_cu_wr__go_i$82 [0] \wr_pick_rise$745
+ assign \fus_cu_wr__go_i$82 [1] \wr_pick_rise$750
+ assign \fus_cu_wr__go_i$82 [2] \wr_pick_rise$751
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 32 \write_en$899
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
- wire width 32 $900
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
- cell $sshl $901
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_rego
- connect \Y $900
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 32 $902
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $903
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $904
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$752
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $753
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $754
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$888
+ connect \A \wr_pick$741
connect \B \wrpick_INT_o_en_o
- connect \Y $903
+ connect \Y $753
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $905
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $900
- connect \S $903
- connect \Y $902
+ process $group_368
+ assign \wp$752 1'0
+ assign \wp$752 $753
+ sync init
end
- process $group_329
- assign \write_en$899 32'00000000000000000000000000000000
- assign \write_en$899 $902
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 5 \addr_en$755
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 5 $756
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $757
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_rego
+ connect \S \wp$752
+ connect \Y $756
+ end
+ process $group_369
+ assign \addr_en$755 5'00000
+ assign \addr_en$755 $756
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_trap0_o_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $906
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $907
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $758
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $759
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_o_ok$83
connect \B \fus_cu_busy_o$10
- connect \Y $906
+ connect \Y $758
end
- process $group_330
+ process $group_370
assign \wrflag_trap0_o_0 1'0
- assign \wrflag_trap0_o_0 $906
+ assign \wrflag_trap0_o_0 $758
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$908
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $909
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $910
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$760
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $761
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $762
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [2]
connect \B \wrpick_INT_o_en_o
- connect \Y $909
+ connect \Y $761
end
- process $group_331
- assign \wr_pick$908 1'0
- assign \wr_pick$908 $909
+ process $group_371
+ assign \wr_pick$760 1'0
+ assign \wr_pick$760 $761
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$911
+ wire width 1 \wr_pick_dly$763
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$911$next
- process $group_332
- assign \wr_pick_dly$911$next \wr_pick_dly$911
- assign \wr_pick_dly$911$next \wr_pick$908
+ wire width 1 \wr_pick_dly$763$next
+ process $group_372
+ assign \wr_pick_dly$763$next \wr_pick_dly$763
+ assign \wr_pick_dly$763$next \wr_pick$760
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$911$next 1'0
+ assign \wr_pick_dly$763$next 1'0
end
sync init
- update \wr_pick_dly$911 1'0
+ update \wr_pick_dly$763 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$911 \wr_pick_dly$911$next
+ update \wr_pick_dly$763 \wr_pick_dly$763$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$912
+ wire width 1 \wr_pick_rise$764
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $913
+ wire width 1 $765
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $914
+ cell $not $766
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$911
- connect \Y $913
+ connect \A \wr_pick_dly$763
+ connect \Y $765
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $915
+ wire width 1 $767
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $916
+ cell $and $768
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$908
- connect \B $913
- connect \Y $915
+ connect \A \wr_pick$760
+ connect \B $765
+ connect \Y $767
end
- process $group_333
- assign \wr_pick_rise$912 1'0
- assign \wr_pick_rise$912 $915
+ process $group_373
+ assign \wr_pick_rise$764 1'0
+ assign \wr_pick_rise$764 $767
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$917
+ wire width 1 \wr_pick_rise$769
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$918
+ wire width 1 \wr_pick_rise$770
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$919
+ wire width 1 \wr_pick_rise$771
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$920
- process $group_334
+ wire width 1 \wr_pick_rise$772
+ process $group_374
assign \fus_cu_wr__go_i$85 5'00000
- assign \fus_cu_wr__go_i$85 [0] \wr_pick_rise$912
- assign \fus_cu_wr__go_i$85 [1] \wr_pick_rise$917
- assign \fus_cu_wr__go_i$85 [2] \wr_pick_rise$918
- assign \fus_cu_wr__go_i$85 [3] \wr_pick_rise$919
- assign \fus_cu_wr__go_i$85 [4] \wr_pick_rise$920
+ assign \fus_cu_wr__go_i$85 [0] \wr_pick_rise$764
+ assign \fus_cu_wr__go_i$85 [1] \wr_pick_rise$769
+ assign \fus_cu_wr__go_i$85 [2] \wr_pick_rise$770
+ assign \fus_cu_wr__go_i$85 [3] \wr_pick_rise$771
+ assign \fus_cu_wr__go_i$85 [4] \wr_pick_rise$772
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 32 \write_en$921
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
- wire width 32 $922
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
- cell $sshl $923
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_rego
- connect \Y $922
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 32 $924
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $925
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $926
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$773
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $774
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $775
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$908
+ connect \A \wr_pick$760
connect \B \wrpick_INT_o_en_o
- connect \Y $925
+ connect \Y $774
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $927
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $922
- connect \S $925
- connect \Y $924
+ process $group_375
+ assign \wp$773 1'0
+ assign \wp$773 $774
+ sync init
end
- process $group_335
- assign \write_en$921 32'00000000000000000000000000000000
- assign \write_en$921 $924
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 5 \addr_en$776
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 5 $777
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $778
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_rego
+ connect \S \wp$773
+ connect \Y $777
+ end
+ process $group_376
+ assign \addr_en$776 5'00000
+ assign \addr_en$776 $777
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_logical0_o_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $928
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $929
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $779
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $780
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_o_ok$86
connect \B \fus_cu_busy_o$13
- connect \Y $928
+ connect \Y $779
end
- process $group_336
+ process $group_377
assign \wrflag_logical0_o_0 1'0
- assign \wrflag_logical0_o_0 $928
+ assign \wrflag_logical0_o_0 $779
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$930
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $931
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $932
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$781
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $782
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $783
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [3]
connect \B \wrpick_INT_o_en_o
- connect \Y $931
+ connect \Y $782
end
- process $group_337
- assign \wr_pick$930 1'0
- assign \wr_pick$930 $931
+ process $group_378
+ assign \wr_pick$781 1'0
+ assign \wr_pick$781 $782
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$933
+ wire width 1 \wr_pick_dly$784
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$933$next
- process $group_338
- assign \wr_pick_dly$933$next \wr_pick_dly$933
- assign \wr_pick_dly$933$next \wr_pick$930
+ wire width 1 \wr_pick_dly$784$next
+ process $group_379
+ assign \wr_pick_dly$784$next \wr_pick_dly$784
+ assign \wr_pick_dly$784$next \wr_pick$781
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$933$next 1'0
+ assign \wr_pick_dly$784$next 1'0
end
sync init
- update \wr_pick_dly$933 1'0
+ update \wr_pick_dly$784 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$933 \wr_pick_dly$933$next
+ update \wr_pick_dly$784 \wr_pick_dly$784$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$934
+ wire width 1 \wr_pick_rise$785
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $935
+ wire width 1 $786
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $936
+ cell $not $787
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$933
- connect \Y $935
+ connect \A \wr_pick_dly$784
+ connect \Y $786
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $937
+ wire width 1 $788
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $938
+ cell $and $789
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$930
- connect \B $935
- connect \Y $937
+ connect \A \wr_pick$781
+ connect \B $786
+ connect \Y $788
end
- process $group_339
- assign \wr_pick_rise$934 1'0
- assign \wr_pick_rise$934 $937
+ process $group_380
+ assign \wr_pick_rise$785 1'0
+ assign \wr_pick_rise$785 $788
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$939
+ wire width 1 \wr_pick_rise$790
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$940
- process $group_340
+ wire width 1 \wr_pick_rise$791
+ process $group_381
assign \fus_cu_wr__go_i$88 3'000
- assign \fus_cu_wr__go_i$88 [0] \wr_pick_rise$934
- assign \fus_cu_wr__go_i$88 [1] \wr_pick_rise$939
- assign \fus_cu_wr__go_i$88 [2] \wr_pick_rise$940
+ assign \fus_cu_wr__go_i$88 [0] \wr_pick_rise$785
+ assign \fus_cu_wr__go_i$88 [1] \wr_pick_rise$790
+ assign \fus_cu_wr__go_i$88 [2] \wr_pick_rise$791
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 32 \write_en$941
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
- wire width 32 $942
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
- cell $sshl $943
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_rego
- connect \Y $942
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 32 $944
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $945
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $946
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$792
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $793
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $794
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$930
+ connect \A \wr_pick$781
connect \B \wrpick_INT_o_en_o
- connect \Y $945
+ connect \Y $793
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $947
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $942
- connect \S $945
- connect \Y $944
+ process $group_382
+ assign \wp$792 1'0
+ assign \wp$792 $793
+ sync init
end
- process $group_341
- assign \write_en$941 32'00000000000000000000000000000000
- assign \write_en$941 $944
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 5 \addr_en$795
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 5 $796
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $797
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_rego
+ connect \S \wp$792
+ connect \Y $796
+ end
+ process $group_383
+ assign \addr_en$795 5'00000
+ assign \addr_en$795 $796
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_spr0_o_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $948
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $949
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $798
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $799
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_o_ok$89
connect \B \fus_cu_busy_o$16
- connect \Y $948
+ connect \Y $798
end
- process $group_342
+ process $group_384
assign \wrflag_spr0_o_0 1'0
- assign \wrflag_spr0_o_0 $948
+ assign \wrflag_spr0_o_0 $798
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$950
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $951
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $952
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$800
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $801
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $802
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [4]
connect \B \wrpick_INT_o_en_o
- connect \Y $951
+ connect \Y $801
end
- process $group_343
- assign \wr_pick$950 1'0
- assign \wr_pick$950 $951
+ process $group_385
+ assign \wr_pick$800 1'0
+ assign \wr_pick$800 $801
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$953
+ wire width 1 \wr_pick_dly$803
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$953$next
- process $group_344
- assign \wr_pick_dly$953$next \wr_pick_dly$953
- assign \wr_pick_dly$953$next \wr_pick$950
+ wire width 1 \wr_pick_dly$803$next
+ process $group_386
+ assign \wr_pick_dly$803$next \wr_pick_dly$803
+ assign \wr_pick_dly$803$next \wr_pick$800
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$953$next 1'0
+ assign \wr_pick_dly$803$next 1'0
end
sync init
- update \wr_pick_dly$953 1'0
+ update \wr_pick_dly$803 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$953 \wr_pick_dly$953$next
+ update \wr_pick_dly$803 \wr_pick_dly$803$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$954
+ wire width 1 \wr_pick_rise$804
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $955
+ wire width 1 $805
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $956
+ cell $not $806
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$953
- connect \Y $955
+ connect \A \wr_pick_dly$803
+ connect \Y $805
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $957
+ wire width 1 $807
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $958
+ cell $and $808
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$950
- connect \B $955
- connect \Y $957
+ connect \A \wr_pick$800
+ connect \B $805
+ connect \Y $807
end
- process $group_345
- assign \wr_pick_rise$954 1'0
- assign \wr_pick_rise$954 $957
+ process $group_387
+ assign \wr_pick_rise$804 1'0
+ assign \wr_pick_rise$804 $807
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$959
+ wire width 1 \wr_pick_rise$809
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$960
+ wire width 1 \wr_pick_rise$810
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$961
+ wire width 1 \wr_pick_rise$811
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$962
+ wire width 1 \wr_pick_rise$812
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$963
- process $group_346
+ wire width 1 \wr_pick_rise$813
+ process $group_388
assign \fus_cu_wr__go_i$91 6'000000
- assign \fus_cu_wr__go_i$91 [0] \wr_pick_rise$954
- assign \fus_cu_wr__go_i$91 [5] \wr_pick_rise$959
- assign \fus_cu_wr__go_i$91 [4] \wr_pick_rise$960
- assign \fus_cu_wr__go_i$91 [3] \wr_pick_rise$961
- assign \fus_cu_wr__go_i$91 [2] \wr_pick_rise$962
- assign \fus_cu_wr__go_i$91 [1] \wr_pick_rise$963
+ assign \fus_cu_wr__go_i$91 [0] \wr_pick_rise$804
+ assign \fus_cu_wr__go_i$91 [5] \wr_pick_rise$809
+ assign \fus_cu_wr__go_i$91 [4] \wr_pick_rise$810
+ assign \fus_cu_wr__go_i$91 [3] \wr_pick_rise$811
+ assign \fus_cu_wr__go_i$91 [2] \wr_pick_rise$812
+ assign \fus_cu_wr__go_i$91 [1] \wr_pick_rise$813
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 32 \write_en$964
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
- wire width 32 $965
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
- cell $sshl $966
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_rego
- connect \Y $965
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 32 $967
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $968
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $969
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$814
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $815
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $816
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$950
+ connect \A \wr_pick$800
connect \B \wrpick_INT_o_en_o
- connect \Y $968
+ connect \Y $815
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $970
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $965
- connect \S $968
- connect \Y $967
+ process $group_389
+ assign \wp$814 1'0
+ assign \wp$814 $815
+ sync init
end
- process $group_347
- assign \write_en$964 32'00000000000000000000000000000000
- assign \write_en$964 $967
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 5 \addr_en$817
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 5 $818
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $819
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_rego
+ connect \S \wp$814
+ connect \Y $818
+ end
+ process $group_390
+ assign \addr_en$817 5'00000
+ assign \addr_en$817 $818
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_div0_o_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $971
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $972
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $820
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $821
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_o_ok$92
connect \B \fus_cu_busy_o$19
- connect \Y $971
+ connect \Y $820
end
- process $group_348
+ process $group_391
assign \wrflag_div0_o_0 1'0
- assign \wrflag_div0_o_0 $971
+ assign \wrflag_div0_o_0 $820
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$973
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $974
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $975
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$822
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $823
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $824
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [5]
connect \B \wrpick_INT_o_en_o
- connect \Y $974
+ connect \Y $823
end
- process $group_349
- assign \wr_pick$973 1'0
- assign \wr_pick$973 $974
+ process $group_392
+ assign \wr_pick$822 1'0
+ assign \wr_pick$822 $823
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$976
+ wire width 1 \wr_pick_dly$825
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$976$next
- process $group_350
- assign \wr_pick_dly$976$next \wr_pick_dly$976
- assign \wr_pick_dly$976$next \wr_pick$973
+ wire width 1 \wr_pick_dly$825$next
+ process $group_393
+ assign \wr_pick_dly$825$next \wr_pick_dly$825
+ assign \wr_pick_dly$825$next \wr_pick$822
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$976$next 1'0
+ assign \wr_pick_dly$825$next 1'0
end
sync init
- update \wr_pick_dly$976 1'0
+ update \wr_pick_dly$825 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$976 \wr_pick_dly$976$next
+ update \wr_pick_dly$825 \wr_pick_dly$825$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$977
+ wire width 1 \wr_pick_rise$826
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $978
+ wire width 1 $827
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $979
+ cell $not $828
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$976
- connect \Y $978
+ connect \A \wr_pick_dly$825
+ connect \Y $827
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $980
+ wire width 1 $829
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $981
+ cell $and $830
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$973
- connect \B $978
- connect \Y $980
+ connect \A \wr_pick$822
+ connect \B $827
+ connect \Y $829
end
- process $group_351
- assign \wr_pick_rise$977 1'0
- assign \wr_pick_rise$977 $980
+ process $group_394
+ assign \wr_pick_rise$826 1'0
+ assign \wr_pick_rise$826 $829
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$982
+ wire width 1 \wr_pick_rise$831
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$983
+ wire width 1 \wr_pick_rise$832
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$984
- process $group_352
+ wire width 1 \wr_pick_rise$833
+ process $group_395
assign \fus_cu_wr__go_i$94 4'0000
- assign \fus_cu_wr__go_i$94 [0] \wr_pick_rise$977
- assign \fus_cu_wr__go_i$94 [1] \wr_pick_rise$982
- assign \fus_cu_wr__go_i$94 [2] \wr_pick_rise$983
- assign \fus_cu_wr__go_i$94 [3] \wr_pick_rise$984
+ assign \fus_cu_wr__go_i$94 [0] \wr_pick_rise$826
+ assign \fus_cu_wr__go_i$94 [1] \wr_pick_rise$831
+ assign \fus_cu_wr__go_i$94 [2] \wr_pick_rise$832
+ assign \fus_cu_wr__go_i$94 [3] \wr_pick_rise$833
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 32 \write_en$985
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
- wire width 32 $986
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
- cell $sshl $987
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_rego
- connect \Y $986
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 32 $988
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $989
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $990
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$834
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $835
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $836
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$973
+ connect \A \wr_pick$822
connect \B \wrpick_INT_o_en_o
- connect \Y $989
+ connect \Y $835
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $991
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $986
- connect \S $989
- connect \Y $988
+ process $group_396
+ assign \wp$834 1'0
+ assign \wp$834 $835
+ sync init
end
- process $group_353
- assign \write_en$985 32'00000000000000000000000000000000
- assign \write_en$985 $988
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 5 \addr_en$837
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 5 $838
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $839
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_rego
+ connect \S \wp$834
+ connect \Y $838
+ end
+ process $group_397
+ assign \addr_en$837 5'00000
+ assign \addr_en$837 $838
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_mul0_o_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $992
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $993
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $840
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $841
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_o_ok$95
connect \B \fus_cu_busy_o$22
- connect \Y $992
+ connect \Y $840
end
- process $group_354
+ process $group_398
assign \wrflag_mul0_o_0 1'0
- assign \wrflag_mul0_o_0 $992
+ assign \wrflag_mul0_o_0 $840
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$994
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $995
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $996
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$842
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $843
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $844
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [6]
connect \B \wrpick_INT_o_en_o
- connect \Y $995
+ connect \Y $843
end
- process $group_355
- assign \wr_pick$994 1'0
- assign \wr_pick$994 $995
+ process $group_399
+ assign \wr_pick$842 1'0
+ assign \wr_pick$842 $843
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$997
+ wire width 1 \wr_pick_dly$845
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$997$next
- process $group_356
- assign \wr_pick_dly$997$next \wr_pick_dly$997
- assign \wr_pick_dly$997$next \wr_pick$994
+ wire width 1 \wr_pick_dly$845$next
+ process $group_400
+ assign \wr_pick_dly$845$next \wr_pick_dly$845
+ assign \wr_pick_dly$845$next \wr_pick$842
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$997$next 1'0
+ assign \wr_pick_dly$845$next 1'0
end
sync init
- update \wr_pick_dly$997 1'0
+ update \wr_pick_dly$845 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$997 \wr_pick_dly$997$next
+ update \wr_pick_dly$845 \wr_pick_dly$845$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$998
+ wire width 1 \wr_pick_rise$846
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $999
+ wire width 1 $847
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1000
+ cell $not $848
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$997
- connect \Y $999
+ connect \A \wr_pick_dly$845
+ connect \Y $847
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1001
+ wire width 1 $849
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1002
+ cell $and $850
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$994
- connect \B $999
- connect \Y $1001
+ connect \A \wr_pick$842
+ connect \B $847
+ connect \Y $849
end
- process $group_357
- assign \wr_pick_rise$998 1'0
- assign \wr_pick_rise$998 $1001
+ process $group_401
+ assign \wr_pick_rise$846 1'0
+ assign \wr_pick_rise$846 $849
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$1003
+ wire width 1 \wr_pick_rise$851
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$1004
+ wire width 1 \wr_pick_rise$852
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$1005
- process $group_358
+ wire width 1 \wr_pick_rise$853
+ process $group_402
assign \fus_cu_wr__go_i$97 4'0000
- assign \fus_cu_wr__go_i$97 [0] \wr_pick_rise$998
- assign \fus_cu_wr__go_i$97 [1] \wr_pick_rise$1003
- assign \fus_cu_wr__go_i$97 [2] \wr_pick_rise$1004
- assign \fus_cu_wr__go_i$97 [3] \wr_pick_rise$1005
+ assign \fus_cu_wr__go_i$97 [0] \wr_pick_rise$846
+ assign \fus_cu_wr__go_i$97 [1] \wr_pick_rise$851
+ assign \fus_cu_wr__go_i$97 [2] \wr_pick_rise$852
+ assign \fus_cu_wr__go_i$97 [3] \wr_pick_rise$853
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 32 \write_en$1006
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
- wire width 32 $1007
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
- cell $sshl $1008
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_rego
- connect \Y $1007
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 32 $1009
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$854
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $855
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $856
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$994
+ connect \A \wr_pick$842
connect \B \wrpick_INT_o_en_o
- connect \Y $1010
+ connect \Y $855
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1012
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $1007
- connect \S $1010
- connect \Y $1009
+ process $group_403
+ assign \wp$854 1'0
+ assign \wp$854 $855
+ sync init
end
- process $group_359
- assign \write_en$1006 32'00000000000000000000000000000000
- assign \write_en$1006 $1009
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 5 \addr_en$857
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 5 $858
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $859
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_rego
+ connect \S \wp$854
+ connect \Y $858
+ end
+ process $group_404
+ assign \addr_en$857 5'00000
+ assign \addr_en$857 $858
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_shiftrot0_o_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1013
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1014
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $860
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $861
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_o_ok$98
connect \B \fus_cu_busy_o$25
- connect \Y $1013
+ connect \Y $860
end
- process $group_360
+ process $group_405
assign \wrflag_shiftrot0_o_0 1'0
- assign \wrflag_shiftrot0_o_0 $1013
+ assign \wrflag_shiftrot0_o_0 $860
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1015
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1016
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1017
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$862
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $863
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $864
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [7]
connect \B \wrpick_INT_o_en_o
- connect \Y $1016
+ connect \Y $863
end
- process $group_361
- assign \wr_pick$1015 1'0
- assign \wr_pick$1015 $1016
+ process $group_406
+ assign \wr_pick$862 1'0
+ assign \wr_pick$862 $863
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1018
+ wire width 1 \wr_pick_dly$865
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1018$next
- process $group_362
- assign \wr_pick_dly$1018$next \wr_pick_dly$1018
- assign \wr_pick_dly$1018$next \wr_pick$1015
+ wire width 1 \wr_pick_dly$865$next
+ process $group_407
+ assign \wr_pick_dly$865$next \wr_pick_dly$865
+ assign \wr_pick_dly$865$next \wr_pick$862
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1018$next 1'0
+ assign \wr_pick_dly$865$next 1'0
end
sync init
- update \wr_pick_dly$1018 1'0
+ update \wr_pick_dly$865 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1018 \wr_pick_dly$1018$next
+ update \wr_pick_dly$865 \wr_pick_dly$865$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$1019
+ wire width 1 \wr_pick_rise$866
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1020
+ wire width 1 $867
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1021
+ cell $not $868
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1018
- connect \Y $1020
+ connect \A \wr_pick_dly$865
+ connect \Y $867
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1022
+ wire width 1 $869
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1023
+ cell $and $870
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1015
- connect \B $1020
- connect \Y $1022
+ connect \A \wr_pick$862
+ connect \B $867
+ connect \Y $869
end
- process $group_363
- assign \wr_pick_rise$1019 1'0
- assign \wr_pick_rise$1019 $1022
+ process $group_408
+ assign \wr_pick_rise$866 1'0
+ assign \wr_pick_rise$866 $869
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$1024
+ wire width 1 \wr_pick_rise$871
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$1025
- process $group_364
+ wire width 1 \wr_pick_rise$872
+ process $group_409
assign \fus_cu_wr__go_i$100 3'000
- assign \fus_cu_wr__go_i$100 [0] \wr_pick_rise$1019
- assign \fus_cu_wr__go_i$100 [1] \wr_pick_rise$1024
- assign \fus_cu_wr__go_i$100 [2] \wr_pick_rise$1025
+ assign \fus_cu_wr__go_i$100 [0] \wr_pick_rise$866
+ assign \fus_cu_wr__go_i$100 [1] \wr_pick_rise$871
+ assign \fus_cu_wr__go_i$100 [2] \wr_pick_rise$872
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 32 \write_en$1026
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
- wire width 32 $1027
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
- cell $sshl $1028
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_rego
- connect \Y $1027
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 32 $1029
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1030
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1031
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$873
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $874
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $875
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1015
+ connect \A \wr_pick$862
connect \B \wrpick_INT_o_en_o
- connect \Y $1030
+ connect \Y $874
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1032
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $1027
- connect \S $1030
- connect \Y $1029
+ process $group_410
+ assign \wp$873 1'0
+ assign \wp$873 $874
+ sync init
end
- process $group_365
- assign \write_en$1026 32'00000000000000000000000000000000
- assign \write_en$1026 $1029
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 5 \addr_en$876
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 5 $877
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $878
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_rego
+ connect \S \wp$873
+ connect \Y $877
+ end
+ process $group_411
+ assign \addr_en$876 5'00000
+ assign \addr_en$876 $877
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_ldst0_o_0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire width 1 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1033
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1034
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $879
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $880
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \o_ok
connect \B \fus_cu_busy_o$28
- connect \Y $1033
+ connect \Y $879
end
- process $group_366
+ process $group_412
assign \wrflag_ldst0_o_0 1'0
- assign \wrflag_ldst0_o_0 $1033
+ assign \wrflag_ldst0_o_0 $879
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1035
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1036
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1037
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$881
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $882
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $883
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [8]
connect \B \wrpick_INT_o_en_o
- connect \Y $1036
+ connect \Y $882
end
- process $group_367
- assign \wr_pick$1035 1'0
- assign \wr_pick$1035 $1036
+ process $group_413
+ assign \wr_pick$881 1'0
+ assign \wr_pick$881 $882
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1038
+ wire width 1 \wr_pick_dly$884
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1038$next
- process $group_368
- assign \wr_pick_dly$1038$next \wr_pick_dly$1038
- assign \wr_pick_dly$1038$next \wr_pick$1035
+ wire width 1 \wr_pick_dly$884$next
+ process $group_414
+ assign \wr_pick_dly$884$next \wr_pick_dly$884
+ assign \wr_pick_dly$884$next \wr_pick$881
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1038$next 1'0
+ assign \wr_pick_dly$884$next 1'0
end
sync init
- update \wr_pick_dly$1038 1'0
+ update \wr_pick_dly$884 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1038 \wr_pick_dly$1038$next
+ update \wr_pick_dly$884 \wr_pick_dly$884$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$1039
+ wire width 1 \wr_pick_rise$885
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1040
+ wire width 1 $886
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1041
+ cell $not $887
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1038
- connect \Y $1040
+ connect \A \wr_pick_dly$884
+ connect \Y $886
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1042
+ wire width 1 $888
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1043
+ cell $and $889
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1035
- connect \B $1040
- connect \Y $1042
+ connect \A \wr_pick$881
+ connect \B $886
+ connect \Y $888
end
- process $group_369
- assign \wr_pick_rise$1039 1'0
- assign \wr_pick_rise$1039 $1042
+ process $group_415
+ assign \wr_pick_rise$885 1'0
+ assign \wr_pick_rise$885 $888
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$1044
- process $group_370
+ wire width 1 \wr_pick_rise$890
+ process $group_416
assign \fus_cu_wr__go_i$102 2'00
- assign \fus_cu_wr__go_i$102 [0] \wr_pick_rise$1039
- assign \fus_cu_wr__go_i$102 [1] \wr_pick_rise$1044
+ assign \fus_cu_wr__go_i$102 [0] \wr_pick_rise$885
+ assign \fus_cu_wr__go_i$102 [1] \wr_pick_rise$890
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 32 \write_en$1045
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
- wire width 32 $1046
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
- cell $sshl $1047
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_rego
- connect \Y $1046
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 32 $1048
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1049
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1050
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$891
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $892
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $893
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1035
+ connect \A \wr_pick$881
connect \B \wrpick_INT_o_en_o
- connect \Y $1049
+ connect \Y $892
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1051
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $1046
- connect \S $1049
- connect \Y $1048
+ process $group_417
+ assign \wp$891 1'0
+ assign \wp$891 $892
+ sync init
end
- process $group_371
- assign \write_en$1045 32'00000000000000000000000000000000
- assign \write_en$1045 $1048
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 5 \addr_en$894
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 5 $895
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $896
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_rego
+ connect \S \wp$891
+ connect \Y $895
+ end
+ process $group_418
+ assign \addr_en$894 5'00000
+ assign \addr_en$894 $895
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_ldst0_o_1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire width 1 \ea_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1052
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1053
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $897
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $898
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ea_ok
connect \B \fus_cu_busy_o$28
- connect \Y $1052
+ connect \Y $897
end
- process $group_372
+ process $group_419
assign \wrflag_ldst0_o_1 1'0
- assign \wrflag_ldst0_o_1 $1052
+ assign \wrflag_ldst0_o_1 $897
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1054
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1055
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1056
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$899
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $900
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $901
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [9]
connect \B \wrpick_INT_o_en_o
- connect \Y $1055
+ connect \Y $900
end
- process $group_373
- assign \wr_pick$1054 1'0
- assign \wr_pick$1054 $1055
+ process $group_420
+ assign \wr_pick$899 1'0
+ assign \wr_pick$899 $900
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1057
+ wire width 1 \wr_pick_dly$902
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1057$next
- process $group_374
- assign \wr_pick_dly$1057$next \wr_pick_dly$1057
- assign \wr_pick_dly$1057$next \wr_pick$1054
+ wire width 1 \wr_pick_dly$902$next
+ process $group_421
+ assign \wr_pick_dly$902$next \wr_pick_dly$902
+ assign \wr_pick_dly$902$next \wr_pick$899
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1057$next 1'0
+ assign \wr_pick_dly$902$next 1'0
end
sync init
- update \wr_pick_dly$1057 1'0
+ update \wr_pick_dly$902 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1057 \wr_pick_dly$1057$next
+ update \wr_pick_dly$902 \wr_pick_dly$902$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1058
+ wire width 1 $903
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1059
+ cell $not $904
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1057
- connect \Y $1058
+ connect \A \wr_pick_dly$902
+ connect \Y $903
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1060
+ wire width 1 $905
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1061
+ cell $and $906
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1054
- connect \B $1058
- connect \Y $1060
+ connect \A \wr_pick$899
+ connect \B $903
+ connect \Y $905
end
- process $group_375
- assign \wr_pick_rise$1044 1'0
- assign \wr_pick_rise$1044 $1060
+ process $group_422
+ assign \wr_pick_rise$890 1'0
+ assign \wr_pick_rise$890 $905
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 32 \write_en$1062
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:131"
- wire width 32 $1063
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:131"
- cell $sshl $1064
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 32
- connect \A 1'1
- connect \B \pdecode2_ea
- connect \Y $1063
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 32 $1065
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1066
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1067
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$907
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $908
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $909
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1054
+ connect \A \wr_pick$899
connect \B \wrpick_INT_o_en_o
- connect \Y $1066
+ connect \Y $908
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1068
- parameter \WIDTH 32
- connect \A 32'00000000000000000000000000000000
- connect \B $1063
- connect \S $1066
- connect \Y $1065
+ process $group_423
+ assign \wp$907 1'0
+ assign \wp$907 $908
+ sync init
end
- process $group_376
- assign \write_en$1062 32'00000000000000000000000000000000
- assign \write_en$1062 $1065
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 5 \addr_en$910
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 5 $911
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $912
+ parameter \WIDTH 5
+ connect \A 5'00000
+ connect \B \pdecode2_ea
+ connect \S \wp$907
+ connect \Y $911
+ end
+ process $group_424
+ assign \addr_en$910 5'00000
+ assign \addr_en$910 $911
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 65 $1069
+ wire width 65 $913
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $1070
+ wire width 64 $914
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1071
+ cell $or $915
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \fus_dest1_o
connect \B \fus_dest1_o$103
- connect \Y $1070
+ connect \Y $914
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $1072
+ wire width 64 $916
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1073
+ cell $or $917
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \fus_dest1_o$105
connect \B \fus_dest1_o$106
- connect \Y $1072
+ connect \Y $916
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $1074
+ wire width 64 $918
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1075
+ cell $or $919
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
connect \A \fus_dest1_o$104
- connect \B $1072
- connect \Y $1074
+ connect \B $916
+ connect \Y $918
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $1076
+ wire width 64 $920
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1077
+ cell $or $921
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $1070
- connect \B $1074
- connect \Y $1076
+ connect \A $914
+ connect \B $918
+ connect \Y $920
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $1078
+ wire width 64 $922
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1079
+ cell $or $923
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \fus_dest1_o$107
connect \B \fus_dest1_o$108
- connect \Y $1078
+ connect \Y $922
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 65 $1080
+ wire width 65 $924
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1081
+ cell $or $925
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A { \o_ok \fus_o }
connect \B { \ea_ok \fus_ea }
- connect \Y $1080
+ connect \Y $924
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 65 $1082
+ wire width 65 $926
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1083
+ cell $or $927
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 65
parameter \Y_WIDTH 65
connect \A \fus_dest1_o$109
- connect \B $1080
- connect \Y $1082
+ connect \B $924
+ connect \Y $926
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 65 $1084
+ wire width 65 $928
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1085
+ cell $or $929
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $1078
- connect \B $1082
- connect \Y $1084
+ connect \A $922
+ connect \B $926
+ connect \Y $928
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 65 $1086
+ wire width 65 $930
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1087
+ cell $or $931
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $1076
- connect \B $1084
- connect \Y $1086
+ connect \A $920
+ connect \B $928
+ connect \Y $930
end
- connect $1069 $1086
- process $group_377
- assign \int_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \int_data_i $1069 [63:0]
+ connect $913 $930
+ process $group_425
+ assign \int_dest1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \int_dest1__data_i $913 [63:0]
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 32 $1088
+ wire width 5 $932
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1089
+ cell $or $933
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A \write_en$879
- connect \B \write_en$899
- connect \Y $1088
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \addr_en
+ connect \B \addr_en$755
+ connect \Y $932
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 32 $1090
+ wire width 5 $934
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1091
+ cell $or $935
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A \write_en$941
- connect \B \write_en$964
- connect \Y $1090
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \addr_en$795
+ connect \B \addr_en$817
+ connect \Y $934
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 32 $1092
+ wire width 5 $936
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1093
+ cell $or $937
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A \write_en$921
- connect \B $1090
- connect \Y $1092
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \addr_en$776
+ connect \B $934
+ connect \Y $936
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 32 $1094
+ wire width 5 $938
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1095
+ cell $or $939
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A $1088
- connect \B $1092
- connect \Y $1094
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A $932
+ connect \B $936
+ connect \Y $938
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 32 $1096
+ wire width 5 $940
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1097
+ cell $or $941
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A \write_en$985
- connect \B \write_en$1006
- connect \Y $1096
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \addr_en$837
+ connect \B \addr_en$857
+ connect \Y $940
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 32 $1098
+ wire width 5 $942
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1099
+ cell $or $943
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A \write_en$1045
- connect \B \write_en$1062
- connect \Y $1098
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \addr_en$894
+ connect \B \addr_en$910
+ connect \Y $942
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 32 $1100
+ wire width 5 $944
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1101
+ cell $or $945
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A \write_en$1026
- connect \B $1098
- connect \Y $1100
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \addr_en$876
+ connect \B $942
+ connect \Y $944
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 32 $1102
+ wire width 5 $946
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1103
+ cell $or $947
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A $1096
- connect \B $1100
- connect \Y $1102
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A $940
+ connect \B $944
+ connect \Y $946
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 32 $1104
+ wire width 5 $948
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1105
+ cell $or $949
parameter \A_SIGNED 0
- parameter \A_WIDTH 32
+ parameter \A_WIDTH 5
parameter \B_SIGNED 0
- parameter \B_WIDTH 32
- parameter \Y_WIDTH 32
- connect \A $1094
- connect \B $1102
- connect \Y $1104
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A $938
+ connect \B $946
+ connect \Y $948
end
- process $group_378
- assign \int_wen 32'00000000000000000000000000000000
- assign \int_wen $1104
+ process $group_426
+ assign \int_dest1__addr 5'00000
+ assign \int_dest1__addr $948
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 1 $950
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $951
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wp
+ connect \B \wp$752
+ connect \Y $950
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 1 $952
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $953
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wp$792
+ connect \B \wp$814
+ connect \Y $952
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 1 $954
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ cell $or $955
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wp$773
+ connect \B $952
+ connect \Y $954
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 1 $956
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ cell $or $957
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $950
+ connect \B $954
+ connect \Y $956
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 1 $958
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $959
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wp$834
+ connect \B \wp$854
+ connect \Y $958
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 1 $960
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $961
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wp$891
+ connect \B \wp$907
+ connect \Y $960
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 1 $962
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ cell $or $963
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wp$873
+ connect \B $960
+ connect \Y $962
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 1 $964
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ cell $or $965
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $958
+ connect \B $962
+ connect \Y $964
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 1 $966
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ cell $or $967
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $956
+ connect \B $964
+ connect \Y $966
+ end
+ process $group_427
+ assign \int_dest1__wen 1'0
+ assign \int_dest1__wen $966
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_cr0_full_cr_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1106
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1107
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $968
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $969
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_full_cr_ok
connect \B \fus_cu_busy_o$4
- connect \Y $1106
+ connect \Y $968
end
- process $group_379
+ process $group_428
assign \wrflag_cr0_full_cr_1 1'0
- assign \wrflag_cr0_full_cr_1 $1106
+ assign \wrflag_cr0_full_cr_1 $968
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1108
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1109
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $970
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $971
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$81 [1]
connect \B \fu_enable [1]
- connect \Y $1108
+ connect \Y $970
end
- process $group_380
+ process $group_429
assign \wrpick_CR_full_cr_i 1'0
- assign \wrpick_CR_full_cr_i $1108
+ assign \wrpick_CR_full_cr_i $970
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1112
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$972
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $973
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $974
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_full_cr_o
connect \B \wrpick_CR_full_cr_en_o
- connect \Y $1111
+ connect \Y $973
end
- process $group_381
- assign \wr_pick$1110 1'0
- assign \wr_pick$1110 $1111
+ process $group_430
+ assign \wr_pick$972 1'0
+ assign \wr_pick$972 $973
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1113
+ wire width 1 \wr_pick_dly$975
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1113$next
- process $group_382
- assign \wr_pick_dly$1113$next \wr_pick_dly$1113
- assign \wr_pick_dly$1113$next \wr_pick$1110
+ wire width 1 \wr_pick_dly$975$next
+ process $group_431
+ assign \wr_pick_dly$975$next \wr_pick_dly$975
+ assign \wr_pick_dly$975$next \wr_pick$972
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1113$next 1'0
+ assign \wr_pick_dly$975$next 1'0
end
sync init
- update \wr_pick_dly$1113 1'0
+ update \wr_pick_dly$975 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1113 \wr_pick_dly$1113$next
+ update \wr_pick_dly$975 \wr_pick_dly$975$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1114
+ wire width 1 $976
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1115
+ cell $not $977
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1113
- connect \Y $1114
+ connect \A \wr_pick_dly$975
+ connect \Y $976
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1116
+ wire width 1 $978
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1117
+ cell $and $979
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1110
- connect \B $1114
- connect \Y $1116
+ connect \A \wr_pick$972
+ connect \B $976
+ connect \Y $978
end
- process $group_383
- assign \wr_pick_rise$897 1'0
- assign \wr_pick_rise$897 $1116
+ process $group_432
+ assign \wr_pick_rise$750 1'0
+ assign \wr_pick_rise$750 $978
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 8 \write_en$1118
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 8 $1119
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1120
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1121
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$980
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $981
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $982
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1110
+ connect \A \wr_pick$972
connect \B \wrpick_CR_full_cr_en_o
- connect \Y $1120
+ connect \Y $981
+ end
+ process $group_433
+ assign \wp$980 1'0
+ assign \wp$980 $981
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1122
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 8 \addr_en$983
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 8 $984
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $985
parameter \WIDTH 8
connect \A 8'00000000
connect \B 8'11111111
- connect \S $1120
- connect \Y $1119
+ connect \S \wp$980
+ connect \Y $984
end
- process $group_384
- assign \write_en$1118 8'00000000
- assign \write_en$1118 $1119
+ process $group_434
+ assign \addr_en$983 8'00000000
+ assign \addr_en$983 $984
sync init
end
- process $group_385
+ process $group_435
assign \cr_full_wr__data_i 32'00000000000000000000000000000000
assign \cr_full_wr__data_i \fus_dest2_o
sync init
end
- process $group_386
+ process $group_436
assign \cr_full_wr__wen 8'00000000
- assign \cr_full_wr__wen \write_en$1118
+ assign \cr_full_wr__wen \addr_en$983
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_alu0_cr_a_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1123
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1124
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $986
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $987
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cr_a_ok
connect \B \fus_cu_busy_o
- connect \Y $1123
+ connect \Y $986
end
- process $group_387
+ process $group_437
assign \wrflag_alu0_cr_a_1 1'0
- assign \wrflag_alu0_cr_a_1 $1123
+ assign \wrflag_alu0_cr_a_1 $986
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1125
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1126
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $988
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $989
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o [1]
connect \B \fu_enable [0]
- connect \Y $1125
+ connect \Y $988
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1127
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1128
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $990
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $991
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$81 [2]
connect \B \fu_enable [1]
- connect \Y $1127
+ connect \Y $990
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1129
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1130
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $992
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $993
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$87 [1]
connect \B \fu_enable [4]
- connect \Y $1129
+ connect \Y $992
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1131
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1132
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $994
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $995
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$93 [1]
connect \B \fu_enable [6]
- connect \Y $1131
+ connect \Y $994
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1133
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1134
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $996
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $997
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$96 [1]
connect \B \fu_enable [7]
- connect \Y $1133
+ connect \Y $996
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1135
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1136
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $998
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $999
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$99 [1]
connect \B \fu_enable [8]
- connect \Y $1135
+ connect \Y $998
end
- process $group_388
+ process $group_438
assign \wrpick_CR_cr_a_i 6'000000
- assign \wrpick_CR_cr_a_i [0] $1125
- assign \wrpick_CR_cr_a_i [1] $1127
- assign \wrpick_CR_cr_a_i [2] $1129
- assign \wrpick_CR_cr_a_i [3] $1131
- assign \wrpick_CR_cr_a_i [4] $1133
- assign \wrpick_CR_cr_a_i [5] $1135
+ assign \wrpick_CR_cr_a_i [0] $988
+ assign \wrpick_CR_cr_a_i [1] $990
+ assign \wrpick_CR_cr_a_i [2] $992
+ assign \wrpick_CR_cr_a_i [3] $994
+ assign \wrpick_CR_cr_a_i [4] $996
+ assign \wrpick_CR_cr_a_i [5] $998
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1137
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1138
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1139
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1002
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_cr_a_o [0]
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $1138
+ connect \Y $1001
end
- process $group_389
- assign \wr_pick$1137 1'0
- assign \wr_pick$1137 $1138
+ process $group_439
+ assign \wr_pick$1000 1'0
+ assign \wr_pick$1000 $1001
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1140
+ wire width 1 \wr_pick_dly$1003
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1140$next
- process $group_390
- assign \wr_pick_dly$1140$next \wr_pick_dly$1140
- assign \wr_pick_dly$1140$next \wr_pick$1137
+ wire width 1 \wr_pick_dly$1003$next
+ process $group_440
+ assign \wr_pick_dly$1003$next \wr_pick_dly$1003
+ assign \wr_pick_dly$1003$next \wr_pick$1000
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1140$next 1'0
+ assign \wr_pick_dly$1003$next 1'0
end
sync init
- update \wr_pick_dly$1140 1'0
+ update \wr_pick_dly$1003 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1140 \wr_pick_dly$1140$next
+ update \wr_pick_dly$1003 \wr_pick_dly$1003$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1141
+ wire width 1 $1004
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1142
+ cell $not $1005
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1140
- connect \Y $1141
+ connect \A \wr_pick_dly$1003
+ connect \Y $1004
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1143
+ wire width 1 $1006
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1144
+ cell $and $1007
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1137
- connect \B $1141
- connect \Y $1143
+ connect \A \wr_pick$1000
+ connect \B $1004
+ connect \Y $1006
end
- process $group_391
- assign \wr_pick_rise$875 1'0
- assign \wr_pick_rise$875 $1143
+ process $group_441
+ assign \wr_pick_rise$731 1'0
+ assign \wr_pick_rise$731 $1006
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1008
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1009
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1010
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_pick$1000
+ connect \B \wrpick_CR_cr_a_en_o
+ connect \Y $1009
+ end
+ process $group_442
+ assign \wp$1008 1'0
+ assign \wp$1008 $1009
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 16 \write_en$1145
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 16 \addr_en$1011
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- wire width 4 $1146
+ wire width 4 $1012
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- cell $sub $1147
+ cell $sub $1013
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A 3'111
connect \B \pdecode2_cr_out
- connect \Y $1146
+ connect \Y $1012
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- wire width 16 $1148
+ wire width 16 $1014
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- cell $sshl $1149
+ cell $sshl $1015
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A 1'1
- connect \B $1146
- connect \Y $1148
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 16 $1150
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1151
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1152
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_pick$1137
- connect \B \wrpick_CR_cr_a_en_o
- connect \Y $1151
+ connect \B $1012
+ connect \Y $1014
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1153
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 16 $1016
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1017
parameter \WIDTH 16
connect \A 16'0000000000000000
- connect \B $1148
- connect \S $1151
- connect \Y $1150
+ connect \B $1014
+ connect \S \wp$1008
+ connect \Y $1016
end
- process $group_392
- assign \write_en$1145 16'0000000000000000
- assign \write_en$1145 $1150
+ process $group_443
+ assign \addr_en$1011 16'0000000000000000
+ assign \addr_en$1011 $1016
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_cr0_cr_a_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1154
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1155
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1018
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1019
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cr_a_ok$110
connect \B \fus_cu_busy_o$4
- connect \Y $1154
+ connect \Y $1018
end
- process $group_393
+ process $group_444
assign \wrflag_cr0_cr_a_2 1'0
- assign \wrflag_cr0_cr_a_2 $1154
+ assign \wrflag_cr0_cr_a_2 $1018
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1156
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1157
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1158
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1020
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1021
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1022
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_cr_a_o [1]
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $1157
+ connect \Y $1021
end
- process $group_394
- assign \wr_pick$1156 1'0
- assign \wr_pick$1156 $1157
+ process $group_445
+ assign \wr_pick$1020 1'0
+ assign \wr_pick$1020 $1021
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1159
+ wire width 1 \wr_pick_dly$1023
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1159$next
- process $group_395
- assign \wr_pick_dly$1159$next \wr_pick_dly$1159
- assign \wr_pick_dly$1159$next \wr_pick$1156
+ wire width 1 \wr_pick_dly$1023$next
+ process $group_446
+ assign \wr_pick_dly$1023$next \wr_pick_dly$1023
+ assign \wr_pick_dly$1023$next \wr_pick$1020
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1159$next 1'0
+ assign \wr_pick_dly$1023$next 1'0
end
sync init
- update \wr_pick_dly$1159 1'0
+ update \wr_pick_dly$1023 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1159 \wr_pick_dly$1159$next
+ update \wr_pick_dly$1023 \wr_pick_dly$1023$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1160
+ wire width 1 $1024
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1161
+ cell $not $1025
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1159
- connect \Y $1160
+ connect \A \wr_pick_dly$1023
+ connect \Y $1024
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1162
+ wire width 1 $1026
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1163
+ cell $and $1027
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1156
- connect \B $1160
- connect \Y $1162
+ connect \A \wr_pick$1020
+ connect \B $1024
+ connect \Y $1026
end
- process $group_396
- assign \wr_pick_rise$898 1'0
- assign \wr_pick_rise$898 $1162
+ process $group_447
+ assign \wr_pick_rise$751 1'0
+ assign \wr_pick_rise$751 $1026
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1028
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1029
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1030
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_pick$1020
+ connect \B \wrpick_CR_cr_a_en_o
+ connect \Y $1029
+ end
+ process $group_448
+ assign \wp$1028 1'0
+ assign \wp$1028 $1029
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 16 \write_en$1164
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 16 \addr_en$1031
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- wire width 4 $1165
+ wire width 4 $1032
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- cell $sub $1166
+ cell $sub $1033
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A 3'111
connect \B \pdecode2_cr_out
- connect \Y $1165
+ connect \Y $1032
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- wire width 16 $1167
+ wire width 16 $1034
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- cell $sshl $1168
+ cell $sshl $1035
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A 1'1
- connect \B $1165
- connect \Y $1167
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 16 $1169
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1170
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1171
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_pick$1156
- connect \B \wrpick_CR_cr_a_en_o
- connect \Y $1170
+ connect \B $1032
+ connect \Y $1034
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1172
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 16 $1036
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1037
parameter \WIDTH 16
connect \A 16'0000000000000000
- connect \B $1167
- connect \S $1170
- connect \Y $1169
+ connect \B $1034
+ connect \S \wp$1028
+ connect \Y $1036
end
- process $group_397
- assign \write_en$1164 16'0000000000000000
- assign \write_en$1164 $1169
+ process $group_449
+ assign \addr_en$1031 16'0000000000000000
+ assign \addr_en$1031 $1036
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_logical0_cr_a_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1173
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1174
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1038
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1039
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cr_a_ok$111
connect \B \fus_cu_busy_o$13
- connect \Y $1173
+ connect \Y $1038
end
- process $group_398
+ process $group_450
assign \wrflag_logical0_cr_a_1 1'0
- assign \wrflag_logical0_cr_a_1 $1173
+ assign \wrflag_logical0_cr_a_1 $1038
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1175
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1176
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1177
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1040
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1041
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1042
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_cr_a_o [2]
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $1176
+ connect \Y $1041
end
- process $group_399
- assign \wr_pick$1175 1'0
- assign \wr_pick$1175 $1176
+ process $group_451
+ assign \wr_pick$1040 1'0
+ assign \wr_pick$1040 $1041
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1178
+ wire width 1 \wr_pick_dly$1043
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1178$next
- process $group_400
- assign \wr_pick_dly$1178$next \wr_pick_dly$1178
- assign \wr_pick_dly$1178$next \wr_pick$1175
+ wire width 1 \wr_pick_dly$1043$next
+ process $group_452
+ assign \wr_pick_dly$1043$next \wr_pick_dly$1043
+ assign \wr_pick_dly$1043$next \wr_pick$1040
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1178$next 1'0
+ assign \wr_pick_dly$1043$next 1'0
end
sync init
- update \wr_pick_dly$1178 1'0
+ update \wr_pick_dly$1043 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1178 \wr_pick_dly$1178$next
+ update \wr_pick_dly$1043 \wr_pick_dly$1043$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1179
+ wire width 1 $1044
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1180
+ cell $not $1045
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1178
- connect \Y $1179
+ connect \A \wr_pick_dly$1043
+ connect \Y $1044
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1181
+ wire width 1 $1046
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1182
+ cell $and $1047
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1175
- connect \B $1179
- connect \Y $1181
+ connect \A \wr_pick$1040
+ connect \B $1044
+ connect \Y $1046
end
- process $group_401
- assign \wr_pick_rise$939 1'0
- assign \wr_pick_rise$939 $1181
+ process $group_453
+ assign \wr_pick_rise$790 1'0
+ assign \wr_pick_rise$790 $1046
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1048
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1049
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1050
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_pick$1040
+ connect \B \wrpick_CR_cr_a_en_o
+ connect \Y $1049
+ end
+ process $group_454
+ assign \wp$1048 1'0
+ assign \wp$1048 $1049
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 16 \write_en$1183
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 16 \addr_en$1051
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- wire width 4 $1184
+ wire width 4 $1052
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- cell $sub $1185
+ cell $sub $1053
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A 3'111
connect \B \pdecode2_cr_out
- connect \Y $1184
+ connect \Y $1052
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- wire width 16 $1186
+ wire width 16 $1054
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- cell $sshl $1187
+ cell $sshl $1055
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A 1'1
- connect \B $1184
- connect \Y $1186
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 16 $1188
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1189
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1190
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_pick$1175
- connect \B \wrpick_CR_cr_a_en_o
- connect \Y $1189
+ connect \B $1052
+ connect \Y $1054
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1191
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 16 $1056
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1057
parameter \WIDTH 16
connect \A 16'0000000000000000
- connect \B $1186
- connect \S $1189
- connect \Y $1188
+ connect \B $1054
+ connect \S \wp$1048
+ connect \Y $1056
end
- process $group_402
- assign \write_en$1183 16'0000000000000000
- assign \write_en$1183 $1188
+ process $group_455
+ assign \addr_en$1051 16'0000000000000000
+ assign \addr_en$1051 $1056
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_div0_cr_a_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1192
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1193
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1058
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1059
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cr_a_ok$112
connect \B \fus_cu_busy_o$19
- connect \Y $1192
+ connect \Y $1058
end
- process $group_403
+ process $group_456
assign \wrflag_div0_cr_a_1 1'0
- assign \wrflag_div0_cr_a_1 $1192
+ assign \wrflag_div0_cr_a_1 $1058
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1194
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1195
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1196
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1060
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1061
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1062
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_cr_a_o [3]
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $1195
+ connect \Y $1061
end
- process $group_404
- assign \wr_pick$1194 1'0
- assign \wr_pick$1194 $1195
+ process $group_457
+ assign \wr_pick$1060 1'0
+ assign \wr_pick$1060 $1061
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1197
+ wire width 1 \wr_pick_dly$1063
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1197$next
- process $group_405
- assign \wr_pick_dly$1197$next \wr_pick_dly$1197
- assign \wr_pick_dly$1197$next \wr_pick$1194
+ wire width 1 \wr_pick_dly$1063$next
+ process $group_458
+ assign \wr_pick_dly$1063$next \wr_pick_dly$1063
+ assign \wr_pick_dly$1063$next \wr_pick$1060
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1197$next 1'0
+ assign \wr_pick_dly$1063$next 1'0
end
sync init
- update \wr_pick_dly$1197 1'0
+ update \wr_pick_dly$1063 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1197 \wr_pick_dly$1197$next
+ update \wr_pick_dly$1063 \wr_pick_dly$1063$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1198
+ wire width 1 $1064
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1199
+ cell $not $1065
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1197
- connect \Y $1198
+ connect \A \wr_pick_dly$1063
+ connect \Y $1064
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1200
+ wire width 1 $1066
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1201
+ cell $and $1067
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1194
- connect \B $1198
- connect \Y $1200
+ connect \A \wr_pick$1060
+ connect \B $1064
+ connect \Y $1066
end
- process $group_406
- assign \wr_pick_rise$982 1'0
- assign \wr_pick_rise$982 $1200
+ process $group_459
+ assign \wr_pick_rise$831 1'0
+ assign \wr_pick_rise$831 $1066
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1068
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1069
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1070
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_pick$1060
+ connect \B \wrpick_CR_cr_a_en_o
+ connect \Y $1069
+ end
+ process $group_460
+ assign \wp$1068 1'0
+ assign \wp$1068 $1069
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 16 \write_en$1202
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 16 \addr_en$1071
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- wire width 4 $1203
+ wire width 4 $1072
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- cell $sub $1204
+ cell $sub $1073
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A 3'111
connect \B \pdecode2_cr_out
- connect \Y $1203
+ connect \Y $1072
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- wire width 16 $1205
+ wire width 16 $1074
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- cell $sshl $1206
+ cell $sshl $1075
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A 1'1
- connect \B $1203
- connect \Y $1205
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 16 $1207
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1208
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1209
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_pick$1194
- connect \B \wrpick_CR_cr_a_en_o
- connect \Y $1208
+ connect \B $1072
+ connect \Y $1074
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1210
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 16 $1076
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1077
parameter \WIDTH 16
connect \A 16'0000000000000000
- connect \B $1205
- connect \S $1208
- connect \Y $1207
+ connect \B $1074
+ connect \S \wp$1068
+ connect \Y $1076
end
- process $group_407
- assign \write_en$1202 16'0000000000000000
- assign \write_en$1202 $1207
+ process $group_461
+ assign \addr_en$1071 16'0000000000000000
+ assign \addr_en$1071 $1076
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_mul0_cr_a_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1211
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1212
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1078
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1079
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cr_a_ok$113
connect \B \fus_cu_busy_o$22
- connect \Y $1211
+ connect \Y $1078
end
- process $group_408
+ process $group_462
assign \wrflag_mul0_cr_a_1 1'0
- assign \wrflag_mul0_cr_a_1 $1211
+ assign \wrflag_mul0_cr_a_1 $1078
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1213
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1214
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1215
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1080
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1081
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1082
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_cr_a_o [4]
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $1214
+ connect \Y $1081
end
- process $group_409
- assign \wr_pick$1213 1'0
- assign \wr_pick$1213 $1214
+ process $group_463
+ assign \wr_pick$1080 1'0
+ assign \wr_pick$1080 $1081
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1216
+ wire width 1 \wr_pick_dly$1083
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1216$next
- process $group_410
- assign \wr_pick_dly$1216$next \wr_pick_dly$1216
- assign \wr_pick_dly$1216$next \wr_pick$1213
+ wire width 1 \wr_pick_dly$1083$next
+ process $group_464
+ assign \wr_pick_dly$1083$next \wr_pick_dly$1083
+ assign \wr_pick_dly$1083$next \wr_pick$1080
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1216$next 1'0
+ assign \wr_pick_dly$1083$next 1'0
end
sync init
- update \wr_pick_dly$1216 1'0
+ update \wr_pick_dly$1083 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1216 \wr_pick_dly$1216$next
+ update \wr_pick_dly$1083 \wr_pick_dly$1083$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1217
+ wire width 1 $1084
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1218
+ cell $not $1085
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1216
- connect \Y $1217
+ connect \A \wr_pick_dly$1083
+ connect \Y $1084
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1219
+ wire width 1 $1086
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1220
+ cell $and $1087
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1213
- connect \B $1217
- connect \Y $1219
+ connect \A \wr_pick$1080
+ connect \B $1084
+ connect \Y $1086
end
- process $group_411
- assign \wr_pick_rise$1003 1'0
- assign \wr_pick_rise$1003 $1219
+ process $group_465
+ assign \wr_pick_rise$851 1'0
+ assign \wr_pick_rise$851 $1086
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1088
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1089
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1090
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_pick$1080
+ connect \B \wrpick_CR_cr_a_en_o
+ connect \Y $1089
+ end
+ process $group_466
+ assign \wp$1088 1'0
+ assign \wp$1088 $1089
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 16 \write_en$1221
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 16 \addr_en$1091
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- wire width 4 $1222
+ wire width 4 $1092
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- cell $sub $1223
+ cell $sub $1093
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A 3'111
connect \B \pdecode2_cr_out
- connect \Y $1222
+ connect \Y $1092
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- wire width 16 $1224
+ wire width 16 $1094
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- cell $sshl $1225
+ cell $sshl $1095
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A 1'1
- connect \B $1222
- connect \Y $1224
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 16 $1226
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1227
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1228
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_pick$1213
- connect \B \wrpick_CR_cr_a_en_o
- connect \Y $1227
+ connect \B $1092
+ connect \Y $1094
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1229
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 16 $1096
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1097
parameter \WIDTH 16
connect \A 16'0000000000000000
- connect \B $1224
- connect \S $1227
- connect \Y $1226
+ connect \B $1094
+ connect \S \wp$1088
+ connect \Y $1096
end
- process $group_412
- assign \write_en$1221 16'0000000000000000
- assign \write_en$1221 $1226
+ process $group_467
+ assign \addr_en$1091 16'0000000000000000
+ assign \addr_en$1091 $1096
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_shiftrot0_cr_a_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1230
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1231
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1098
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1099
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cr_a_ok$114
connect \B \fus_cu_busy_o$25
- connect \Y $1230
+ connect \Y $1098
end
- process $group_413
+ process $group_468
assign \wrflag_shiftrot0_cr_a_1 1'0
- assign \wrflag_shiftrot0_cr_a_1 $1230
+ assign \wrflag_shiftrot0_cr_a_1 $1098
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1232
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1233
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1234
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1102
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_cr_a_o [5]
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $1233
+ connect \Y $1101
end
- process $group_414
- assign \wr_pick$1232 1'0
- assign \wr_pick$1232 $1233
+ process $group_469
+ assign \wr_pick$1100 1'0
+ assign \wr_pick$1100 $1101
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1235
+ wire width 1 \wr_pick_dly$1103
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1235$next
- process $group_415
- assign \wr_pick_dly$1235$next \wr_pick_dly$1235
- assign \wr_pick_dly$1235$next \wr_pick$1232
+ wire width 1 \wr_pick_dly$1103$next
+ process $group_470
+ assign \wr_pick_dly$1103$next \wr_pick_dly$1103
+ assign \wr_pick_dly$1103$next \wr_pick$1100
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1235$next 1'0
+ assign \wr_pick_dly$1103$next 1'0
end
sync init
- update \wr_pick_dly$1235 1'0
+ update \wr_pick_dly$1103 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1235 \wr_pick_dly$1235$next
+ update \wr_pick_dly$1103 \wr_pick_dly$1103$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1236
+ wire width 1 $1104
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1237
+ cell $not $1105
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1235
- connect \Y $1236
+ connect \A \wr_pick_dly$1103
+ connect \Y $1104
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1238
+ wire width 1 $1106
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1239
+ cell $and $1107
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1232
- connect \B $1236
- connect \Y $1238
+ connect \A \wr_pick$1100
+ connect \B $1104
+ connect \Y $1106
end
- process $group_416
- assign \wr_pick_rise$1024 1'0
- assign \wr_pick_rise$1024 $1238
+ process $group_471
+ assign \wr_pick_rise$871 1'0
+ assign \wr_pick_rise$871 $1106
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1108
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1109
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1110
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_pick$1100
+ connect \B \wrpick_CR_cr_a_en_o
+ connect \Y $1109
+ end
+ process $group_472
+ assign \wp$1108 1'0
+ assign \wp$1108 $1109
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 16 \write_en$1240
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 16 \addr_en$1111
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- wire width 4 $1241
+ wire width 4 $1112
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- cell $sub $1242
+ cell $sub $1113
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A 3'111
connect \B \pdecode2_cr_out
- connect \Y $1241
+ connect \Y $1112
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- wire width 16 $1243
+ wire width 16 $1114
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
- cell $sshl $1244
+ cell $sshl $1115
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A 1'1
- connect \B $1241
- connect \Y $1243
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 16 $1245
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1246
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1247
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_pick$1232
- connect \B \wrpick_CR_cr_a_en_o
- connect \Y $1246
+ connect \B $1112
+ connect \Y $1114
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1248
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 16 $1116
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1117
parameter \WIDTH 16
connect \A 16'0000000000000000
- connect \B $1243
- connect \S $1246
- connect \Y $1245
+ connect \B $1114
+ connect \S \wp$1108
+ connect \Y $1116
end
- process $group_417
- assign \write_en$1240 16'0000000000000000
- assign \write_en$1240 $1245
+ process $group_473
+ assign \addr_en$1111 16'0000000000000000
+ assign \addr_en$1111 $1116
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 4 $1249
+ wire width 4 $1118
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1250
+ cell $or $1119
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \fus_dest3_o
connect \B \fus_dest2_o$116
- connect \Y $1249
+ connect \Y $1118
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 4 $1251
+ wire width 4 $1120
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1252
+ cell $or $1121
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
connect \A \fus_dest2_o$115
- connect \B $1249
- connect \Y $1251
+ connect \B $1118
+ connect \Y $1120
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 4 $1253
+ wire width 4 $1122
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1254
+ cell $or $1123
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \fus_dest2_o$118
connect \B \fus_dest2_o$119
- connect \Y $1253
+ connect \Y $1122
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 4 $1255
+ wire width 4 $1124
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1256
+ cell $or $1125
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
connect \A \fus_dest2_o$117
- connect \B $1253
- connect \Y $1255
+ connect \B $1122
+ connect \Y $1124
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 4 $1257
+ wire width 4 $1126
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1258
+ cell $or $1127
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A $1251
- connect \B $1255
- connect \Y $1257
+ connect \A $1120
+ connect \B $1124
+ connect \Y $1126
end
- process $group_418
+ process $group_474
assign \cr_data_i 4'0000
- assign \cr_data_i $1257
+ assign \cr_data_i $1126
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 16 $1259
+ wire width 16 $1128
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 16 $1260
+ wire width 16 $1129
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1261
+ cell $or $1130
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
- connect \A \write_en$1164
- connect \B \write_en$1183
- connect \Y $1260
+ connect \A \addr_en$1031
+ connect \B \addr_en$1051
+ connect \Y $1129
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 16 $1262
+ wire width 16 $1131
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1263
+ cell $or $1132
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
- connect \A \write_en$1145
- connect \B $1260
- connect \Y $1262
+ connect \A \addr_en$1011
+ connect \B $1129
+ connect \Y $1131
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 16 $1264
+ wire width 16 $1133
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1265
+ cell $or $1134
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
- connect \A \write_en$1221
- connect \B \write_en$1240
- connect \Y $1264
+ connect \A \addr_en$1091
+ connect \B \addr_en$1111
+ connect \Y $1133
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 16 $1266
+ wire width 16 $1135
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1267
+ cell $or $1136
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
- connect \A \write_en$1202
- connect \B $1264
- connect \Y $1266
+ connect \A \addr_en$1071
+ connect \B $1133
+ connect \Y $1135
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 16 $1268
+ wire width 16 $1137
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1269
+ cell $or $1138
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
- connect \A $1262
- connect \B $1266
- connect \Y $1268
+ connect \A $1131
+ connect \B $1135
+ connect \Y $1137
end
- connect $1259 $1268
- process $group_419
+ connect $1128 $1137
+ process $group_475
assign \cr_wen 8'00000000
- assign \cr_wen $1259 [7:0]
+ assign \cr_wen $1128 [7:0]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_alu0_xer_ca_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1270
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1271
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1139
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1140
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_xer_ca_ok
connect \B \fus_cu_busy_o
- connect \Y $1270
+ connect \Y $1139
end
- process $group_420
+ process $group_476
assign \wrflag_alu0_xer_ca_2 1'0
- assign \wrflag_alu0_xer_ca_2 $1270
+ assign \wrflag_alu0_xer_ca_2 $1139
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1272
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1273
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1141
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1142
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o [2]
connect \B \fu_enable [0]
- connect \Y $1272
+ connect \Y $1141
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1274
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1275
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1143
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1144
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$87 [2]
connect \B \fu_enable [4]
- connect \Y $1274
+ connect \Y $1143
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1276
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1277
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1145
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1146
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$90 [5]
connect \B \fu_enable [5]
- connect \Y $1276
+ connect \Y $1145
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1278
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1279
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1147
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1148
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$99 [2]
connect \B \fu_enable [8]
- connect \Y $1278
+ connect \Y $1147
end
- process $group_421
+ process $group_477
assign \wrpick_XER_xer_ca_i 4'0000
- assign \wrpick_XER_xer_ca_i [0] $1272
- assign \wrpick_XER_xer_ca_i [1] $1274
- assign \wrpick_XER_xer_ca_i [2] $1276
- assign \wrpick_XER_xer_ca_i [3] $1278
+ assign \wrpick_XER_xer_ca_i [0] $1141
+ assign \wrpick_XER_xer_ca_i [1] $1143
+ assign \wrpick_XER_xer_ca_i [2] $1145
+ assign \wrpick_XER_xer_ca_i [3] $1147
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1280
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1281
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1282
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1149
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1150
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1151
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ca_o [0]
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $1281
+ connect \Y $1150
end
- process $group_422
- assign \wr_pick$1280 1'0
- assign \wr_pick$1280 $1281
+ process $group_478
+ assign \wr_pick$1149 1'0
+ assign \wr_pick$1149 $1150
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1283
+ wire width 1 \wr_pick_dly$1152
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1283$next
- process $group_423
- assign \wr_pick_dly$1283$next \wr_pick_dly$1283
- assign \wr_pick_dly$1283$next \wr_pick$1280
+ wire width 1 \wr_pick_dly$1152$next
+ process $group_479
+ assign \wr_pick_dly$1152$next \wr_pick_dly$1152
+ assign \wr_pick_dly$1152$next \wr_pick$1149
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1283$next 1'0
+ assign \wr_pick_dly$1152$next 1'0
end
sync init
- update \wr_pick_dly$1283 1'0
+ update \wr_pick_dly$1152 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1283 \wr_pick_dly$1283$next
+ update \wr_pick_dly$1152 \wr_pick_dly$1152$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1284
+ wire width 1 $1153
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1285
+ cell $not $1154
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1283
- connect \Y $1284
+ connect \A \wr_pick_dly$1152
+ connect \Y $1153
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1286
+ wire width 1 $1155
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1287
+ cell $and $1156
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1280
- connect \B $1284
- connect \Y $1286
+ connect \A \wr_pick$1149
+ connect \B $1153
+ connect \Y $1155
end
- process $group_424
- assign \wr_pick_rise$876 1'0
- assign \wr_pick_rise$876 $1286
+ process $group_480
+ assign \wr_pick_rise$732 1'0
+ assign \wr_pick_rise$732 $1155
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 2 \write_en$1288
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 2 $1289
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1290
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1291
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1157
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1158
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1159
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1280
+ connect \A \wr_pick$1149
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $1290
+ connect \Y $1158
+ end
+ process $group_481
+ assign \wp$1157 1'0
+ assign \wp$1157 $1158
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1292
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 2 \addr_en$1160
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 2 $1161
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1162
parameter \WIDTH 2
connect \A 2'00
connect \B 2'10
- connect \S $1290
- connect \Y $1289
+ connect \S \wp$1157
+ connect \Y $1161
end
- process $group_425
- assign \write_en$1288 2'00
- assign \write_en$1288 $1289
+ process $group_482
+ assign \addr_en$1160 2'00
+ assign \addr_en$1160 $1161
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_logical0_xer_ca_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1293
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1294
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1163
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1164
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_xer_ca_ok$120
connect \B \fus_cu_busy_o$13
- connect \Y $1293
+ connect \Y $1163
end
- process $group_426
+ process $group_483
assign \wrflag_logical0_xer_ca_2 1'0
- assign \wrflag_logical0_xer_ca_2 $1293
+ assign \wrflag_logical0_xer_ca_2 $1163
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1295
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1296
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1297
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1165
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1166
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1167
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ca_o [1]
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $1296
+ connect \Y $1166
end
- process $group_427
- assign \wr_pick$1295 1'0
- assign \wr_pick$1295 $1296
+ process $group_484
+ assign \wr_pick$1165 1'0
+ assign \wr_pick$1165 $1166
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1298
+ wire width 1 \wr_pick_dly$1168
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1298$next
- process $group_428
- assign \wr_pick_dly$1298$next \wr_pick_dly$1298
- assign \wr_pick_dly$1298$next \wr_pick$1295
+ wire width 1 \wr_pick_dly$1168$next
+ process $group_485
+ assign \wr_pick_dly$1168$next \wr_pick_dly$1168
+ assign \wr_pick_dly$1168$next \wr_pick$1165
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1298$next 1'0
+ assign \wr_pick_dly$1168$next 1'0
end
sync init
- update \wr_pick_dly$1298 1'0
+ update \wr_pick_dly$1168 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1298 \wr_pick_dly$1298$next
+ update \wr_pick_dly$1168 \wr_pick_dly$1168$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1299
+ wire width 1 $1169
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1300
+ cell $not $1170
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1298
- connect \Y $1299
+ connect \A \wr_pick_dly$1168
+ connect \Y $1169
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1301
+ wire width 1 $1171
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1302
+ cell $and $1172
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1295
- connect \B $1299
- connect \Y $1301
+ connect \A \wr_pick$1165
+ connect \B $1169
+ connect \Y $1171
end
- process $group_429
- assign \wr_pick_rise$940 1'0
- assign \wr_pick_rise$940 $1301
+ process $group_486
+ assign \wr_pick_rise$791 1'0
+ assign \wr_pick_rise$791 $1171
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 2 \write_en$1303
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 2 $1304
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1305
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1306
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1173
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1174
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1175
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1295
+ connect \A \wr_pick$1165
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $1305
+ connect \Y $1174
+ end
+ process $group_487
+ assign \wp$1173 1'0
+ assign \wp$1173 $1174
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1307
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 2 \addr_en$1176
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 2 $1177
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1178
parameter \WIDTH 2
connect \A 2'00
connect \B 2'10
- connect \S $1305
- connect \Y $1304
+ connect \S \wp$1173
+ connect \Y $1177
end
- process $group_430
- assign \write_en$1303 2'00
- assign \write_en$1303 $1304
+ process $group_488
+ assign \addr_en$1176 2'00
+ assign \addr_en$1176 $1177
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_spr0_xer_ca_5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1308
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1309
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1179
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1180
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_xer_ca_ok$121
connect \B \fus_cu_busy_o$16
- connect \Y $1308
+ connect \Y $1179
end
- process $group_431
+ process $group_489
assign \wrflag_spr0_xer_ca_5 1'0
- assign \wrflag_spr0_xer_ca_5 $1308
+ assign \wrflag_spr0_xer_ca_5 $1179
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1310
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1311
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1312
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1181
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1182
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1183
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ca_o [2]
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $1311
+ connect \Y $1182
end
- process $group_432
- assign \wr_pick$1310 1'0
- assign \wr_pick$1310 $1311
+ process $group_490
+ assign \wr_pick$1181 1'0
+ assign \wr_pick$1181 $1182
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1313
+ wire width 1 \wr_pick_dly$1184
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1313$next
- process $group_433
- assign \wr_pick_dly$1313$next \wr_pick_dly$1313
- assign \wr_pick_dly$1313$next \wr_pick$1310
+ wire width 1 \wr_pick_dly$1184$next
+ process $group_491
+ assign \wr_pick_dly$1184$next \wr_pick_dly$1184
+ assign \wr_pick_dly$1184$next \wr_pick$1181
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1313$next 1'0
+ assign \wr_pick_dly$1184$next 1'0
end
sync init
- update \wr_pick_dly$1313 1'0
+ update \wr_pick_dly$1184 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1313 \wr_pick_dly$1313$next
+ update \wr_pick_dly$1184 \wr_pick_dly$1184$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1314
+ wire width 1 $1185
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1315
+ cell $not $1186
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1313
- connect \Y $1314
+ connect \A \wr_pick_dly$1184
+ connect \Y $1185
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1316
+ wire width 1 $1187
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1317
+ cell $and $1188
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1310
- connect \B $1314
- connect \Y $1316
+ connect \A \wr_pick$1181
+ connect \B $1185
+ connect \Y $1187
end
- process $group_434
- assign \wr_pick_rise$959 1'0
- assign \wr_pick_rise$959 $1316
+ process $group_492
+ assign \wr_pick_rise$809 1'0
+ assign \wr_pick_rise$809 $1187
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 2 \write_en$1318
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 2 $1319
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1320
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1321
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1189
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1190
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1191
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1310
+ connect \A \wr_pick$1181
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $1320
+ connect \Y $1190
+ end
+ process $group_493
+ assign \wp$1189 1'0
+ assign \wp$1189 $1190
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1322
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 2 \addr_en$1192
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 2 $1193
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1194
parameter \WIDTH 2
connect \A 2'00
connect \B 2'10
- connect \S $1320
- connect \Y $1319
+ connect \S \wp$1189
+ connect \Y $1193
end
- process $group_435
- assign \write_en$1318 2'00
- assign \write_en$1318 $1319
+ process $group_494
+ assign \addr_en$1192 2'00
+ assign \addr_en$1192 $1193
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_shiftrot0_xer_ca_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1323
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1324
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1195
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1196
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_xer_ca_ok$122
connect \B \fus_cu_busy_o$25
- connect \Y $1323
+ connect \Y $1195
end
- process $group_436
+ process $group_495
assign \wrflag_shiftrot0_xer_ca_2 1'0
- assign \wrflag_shiftrot0_xer_ca_2 $1323
+ assign \wrflag_shiftrot0_xer_ca_2 $1195
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1325
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1326
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1327
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1197
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1198
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1199
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ca_o [3]
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $1326
+ connect \Y $1198
end
- process $group_437
- assign \wr_pick$1325 1'0
- assign \wr_pick$1325 $1326
+ process $group_496
+ assign \wr_pick$1197 1'0
+ assign \wr_pick$1197 $1198
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1328
+ wire width 1 \wr_pick_dly$1200
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1328$next
- process $group_438
- assign \wr_pick_dly$1328$next \wr_pick_dly$1328
- assign \wr_pick_dly$1328$next \wr_pick$1325
+ wire width 1 \wr_pick_dly$1200$next
+ process $group_497
+ assign \wr_pick_dly$1200$next \wr_pick_dly$1200
+ assign \wr_pick_dly$1200$next \wr_pick$1197
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1328$next 1'0
+ assign \wr_pick_dly$1200$next 1'0
end
sync init
- update \wr_pick_dly$1328 1'0
+ update \wr_pick_dly$1200 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1328 \wr_pick_dly$1328$next
+ update \wr_pick_dly$1200 \wr_pick_dly$1200$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1329
+ wire width 1 $1201
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1330
+ cell $not $1202
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1328
- connect \Y $1329
+ connect \A \wr_pick_dly$1200
+ connect \Y $1201
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1331
+ wire width 1 $1203
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1332
+ cell $and $1204
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1325
- connect \B $1329
- connect \Y $1331
+ connect \A \wr_pick$1197
+ connect \B $1201
+ connect \Y $1203
end
- process $group_439
- assign \wr_pick_rise$1025 1'0
- assign \wr_pick_rise$1025 $1331
+ process $group_498
+ assign \wr_pick_rise$872 1'0
+ assign \wr_pick_rise$872 $1203
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 2 \write_en$1333
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 2 $1334
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1335
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1336
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1205
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1206
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1207
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1325
+ connect \A \wr_pick$1197
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $1335
+ connect \Y $1206
+ end
+ process $group_499
+ assign \wp$1205 1'0
+ assign \wp$1205 $1206
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1337
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 2 \addr_en$1208
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 2 $1209
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1210
parameter \WIDTH 2
connect \A 2'00
connect \B 2'10
- connect \S $1335
- connect \Y $1334
+ connect \S \wp$1205
+ connect \Y $1209
end
- process $group_440
- assign \write_en$1333 2'00
- assign \write_en$1333 $1334
+ process $group_500
+ assign \addr_en$1208 2'00
+ assign \addr_en$1208 $1209
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 2 $1338
+ wire width 2 $1211
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1339
+ cell $or $1212
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \fus_dest3_o$123
connect \B \fus_dest3_o$124
- connect \Y $1338
+ connect \Y $1211
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 2 $1340
+ wire width 2 $1213
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1341
+ cell $or $1214
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \fus_dest6_o
connect \B \fus_dest3_o$125
- connect \Y $1340
+ connect \Y $1213
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 2 $1342
+ wire width 2 $1215
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1343
+ cell $or $1216
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
- connect \A $1338
- connect \B $1340
- connect \Y $1342
+ connect \A $1211
+ connect \B $1213
+ connect \Y $1215
end
- process $group_441
+ process $group_501
assign \xer_data_i 2'00
- assign \xer_data_i $1342
+ assign \xer_data_i $1215
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 3 $1344
+ wire width 3 $1217
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 2 $1345
+ wire width 2 $1218
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1346
+ cell $or $1219
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
- connect \A \write_en$1288
- connect \B \write_en$1303
- connect \Y $1345
+ connect \A \addr_en$1160
+ connect \B \addr_en$1176
+ connect \Y $1218
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 2 $1347
+ wire width 2 $1220
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1348
+ cell $or $1221
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
- connect \A \write_en$1318
- connect \B \write_en$1333
- connect \Y $1347
+ connect \A \addr_en$1192
+ connect \B \addr_en$1208
+ connect \Y $1220
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 2 $1349
+ wire width 2 $1222
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1350
+ cell $or $1223
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
- connect \A $1345
- connect \B $1347
- connect \Y $1349
+ connect \A $1218
+ connect \B $1220
+ connect \Y $1222
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $pos $1351
+ cell $pos $1224
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 3
- connect \A $1349
- connect \Y $1344
+ connect \A $1222
+ connect \Y $1217
end
- process $group_442
+ process $group_502
assign \xer_wen 3'000
- assign \xer_wen $1344
+ assign \xer_wen $1217
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_alu0_xer_ov_3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1352
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1353
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1225
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1226
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_xer_ov_ok
connect \B \fus_cu_busy_o
- connect \Y $1352
+ connect \Y $1225
end
- process $group_443
+ process $group_503
assign \wrflag_alu0_xer_ov_3 1'0
- assign \wrflag_alu0_xer_ov_3 $1352
+ assign \wrflag_alu0_xer_ov_3 $1225
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1354
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1355
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1227
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1228
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o [3]
connect \B \fu_enable [0]
- connect \Y $1354
+ connect \Y $1227
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1356
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1357
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1229
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1230
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$90 [4]
connect \B \fu_enable [5]
- connect \Y $1356
+ connect \Y $1229
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1358
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1359
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1231
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1232
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$93 [2]
connect \B \fu_enable [6]
- connect \Y $1358
+ connect \Y $1231
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1360
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1361
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1233
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1234
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$96 [2]
connect \B \fu_enable [7]
- connect \Y $1360
+ connect \Y $1233
end
- process $group_444
+ process $group_504
assign \wrpick_XER_xer_ov_i 4'0000
- assign \wrpick_XER_xer_ov_i [0] $1354
- assign \wrpick_XER_xer_ov_i [1] $1356
- assign \wrpick_XER_xer_ov_i [2] $1358
- assign \wrpick_XER_xer_ov_i [3] $1360
+ assign \wrpick_XER_xer_ov_i [0] $1227
+ assign \wrpick_XER_xer_ov_i [1] $1229
+ assign \wrpick_XER_xer_ov_i [2] $1231
+ assign \wrpick_XER_xer_ov_i [3] $1233
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1362
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1363
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1364
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1235
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1236
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1237
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ov_o [0]
connect \B \wrpick_XER_xer_ov_en_o
- connect \Y $1363
+ connect \Y $1236
end
- process $group_445
- assign \wr_pick$1362 1'0
- assign \wr_pick$1362 $1363
+ process $group_505
+ assign \wr_pick$1235 1'0
+ assign \wr_pick$1235 $1236
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1365
+ wire width 1 \wr_pick_dly$1238
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1365$next
- process $group_446
- assign \wr_pick_dly$1365$next \wr_pick_dly$1365
- assign \wr_pick_dly$1365$next \wr_pick$1362
+ wire width 1 \wr_pick_dly$1238$next
+ process $group_506
+ assign \wr_pick_dly$1238$next \wr_pick_dly$1238
+ assign \wr_pick_dly$1238$next \wr_pick$1235
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1365$next 1'0
+ assign \wr_pick_dly$1238$next 1'0
end
sync init
- update \wr_pick_dly$1365 1'0
+ update \wr_pick_dly$1238 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1365 \wr_pick_dly$1365$next
+ update \wr_pick_dly$1238 \wr_pick_dly$1238$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1366
+ wire width 1 $1239
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1367
+ cell $not $1240
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1365
- connect \Y $1366
+ connect \A \wr_pick_dly$1238
+ connect \Y $1239
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1368
+ wire width 1 $1241
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1369
+ cell $and $1242
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1362
- connect \B $1366
- connect \Y $1368
+ connect \A \wr_pick$1235
+ connect \B $1239
+ connect \Y $1241
end
- process $group_447
- assign \wr_pick_rise$877 1'0
- assign \wr_pick_rise$877 $1368
+ process $group_507
+ assign \wr_pick_rise$733 1'0
+ assign \wr_pick_rise$733 $1241
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 3 \write_en$1370
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 3 $1371
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1372
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1373
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1243
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1244
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1245
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1362
+ connect \A \wr_pick$1235
connect \B \wrpick_XER_xer_ov_en_o
- connect \Y $1372
+ connect \Y $1244
+ end
+ process $group_508
+ assign \wp$1243 1'0
+ assign \wp$1243 $1244
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1374
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 3 \addr_en$1246
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 3 $1247
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1248
parameter \WIDTH 3
connect \A 3'000
connect \B 3'100
- connect \S $1372
- connect \Y $1371
+ connect \S \wp$1243
+ connect \Y $1247
end
- process $group_448
- assign \write_en$1370 3'000
- assign \write_en$1370 $1371
+ process $group_509
+ assign \addr_en$1246 3'000
+ assign \addr_en$1246 $1247
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_spr0_xer_ov_4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1375
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1376
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1249
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1250
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_xer_ov_ok$126
connect \B \fus_cu_busy_o$16
- connect \Y $1375
+ connect \Y $1249
end
- process $group_449
+ process $group_510
assign \wrflag_spr0_xer_ov_4 1'0
- assign \wrflag_spr0_xer_ov_4 $1375
+ assign \wrflag_spr0_xer_ov_4 $1249
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1377
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1378
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1379
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1251
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1252
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1253
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ov_o [1]
connect \B \wrpick_XER_xer_ov_en_o
- connect \Y $1378
+ connect \Y $1252
end
- process $group_450
- assign \wr_pick$1377 1'0
- assign \wr_pick$1377 $1378
+ process $group_511
+ assign \wr_pick$1251 1'0
+ assign \wr_pick$1251 $1252
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1380
+ wire width 1 \wr_pick_dly$1254
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1380$next
- process $group_451
- assign \wr_pick_dly$1380$next \wr_pick_dly$1380
- assign \wr_pick_dly$1380$next \wr_pick$1377
+ wire width 1 \wr_pick_dly$1254$next
+ process $group_512
+ assign \wr_pick_dly$1254$next \wr_pick_dly$1254
+ assign \wr_pick_dly$1254$next \wr_pick$1251
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1380$next 1'0
+ assign \wr_pick_dly$1254$next 1'0
end
sync init
- update \wr_pick_dly$1380 1'0
+ update \wr_pick_dly$1254 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1380 \wr_pick_dly$1380$next
+ update \wr_pick_dly$1254 \wr_pick_dly$1254$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1381
+ wire width 1 $1255
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1382
+ cell $not $1256
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1380
- connect \Y $1381
+ connect \A \wr_pick_dly$1254
+ connect \Y $1255
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1383
+ wire width 1 $1257
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1384
+ cell $and $1258
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1377
- connect \B $1381
- connect \Y $1383
+ connect \A \wr_pick$1251
+ connect \B $1255
+ connect \Y $1257
end
- process $group_452
- assign \wr_pick_rise$960 1'0
- assign \wr_pick_rise$960 $1383
+ process $group_513
+ assign \wr_pick_rise$810 1'0
+ assign \wr_pick_rise$810 $1257
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 3 \write_en$1385
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 3 $1386
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1387
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1388
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1259
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1260
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1261
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1377
+ connect \A \wr_pick$1251
connect \B \wrpick_XER_xer_ov_en_o
- connect \Y $1387
+ connect \Y $1260
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1389
+ process $group_514
+ assign \wp$1259 1'0
+ assign \wp$1259 $1260
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 3 \addr_en$1262
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 3 $1263
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1264
parameter \WIDTH 3
connect \A 3'000
connect \B 3'100
- connect \S $1387
- connect \Y $1386
+ connect \S \wp$1259
+ connect \Y $1263
end
- process $group_453
- assign \write_en$1385 3'000
- assign \write_en$1385 $1386
+ process $group_515
+ assign \addr_en$1262 3'000
+ assign \addr_en$1262 $1263
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_div0_xer_ov_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1390
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1391
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1265
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1266
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_xer_ov_ok$127
connect \B \fus_cu_busy_o$19
- connect \Y $1390
+ connect \Y $1265
end
- process $group_454
+ process $group_516
assign \wrflag_div0_xer_ov_2 1'0
- assign \wrflag_div0_xer_ov_2 $1390
+ assign \wrflag_div0_xer_ov_2 $1265
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1392
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1393
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1394
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1267
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1268
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1269
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ov_o [2]
connect \B \wrpick_XER_xer_ov_en_o
- connect \Y $1393
+ connect \Y $1268
end
- process $group_455
- assign \wr_pick$1392 1'0
- assign \wr_pick$1392 $1393
+ process $group_517
+ assign \wr_pick$1267 1'0
+ assign \wr_pick$1267 $1268
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1395
+ wire width 1 \wr_pick_dly$1270
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1395$next
- process $group_456
- assign \wr_pick_dly$1395$next \wr_pick_dly$1395
- assign \wr_pick_dly$1395$next \wr_pick$1392
+ wire width 1 \wr_pick_dly$1270$next
+ process $group_518
+ assign \wr_pick_dly$1270$next \wr_pick_dly$1270
+ assign \wr_pick_dly$1270$next \wr_pick$1267
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1395$next 1'0
+ assign \wr_pick_dly$1270$next 1'0
end
sync init
- update \wr_pick_dly$1395 1'0
+ update \wr_pick_dly$1270 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1395 \wr_pick_dly$1395$next
+ update \wr_pick_dly$1270 \wr_pick_dly$1270$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1396
+ wire width 1 $1271
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1397
+ cell $not $1272
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1395
- connect \Y $1396
+ connect \A \wr_pick_dly$1270
+ connect \Y $1271
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1398
+ wire width 1 $1273
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1399
+ cell $and $1274
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1392
- connect \B $1396
- connect \Y $1398
+ connect \A \wr_pick$1267
+ connect \B $1271
+ connect \Y $1273
end
- process $group_457
- assign \wr_pick_rise$983 1'0
- assign \wr_pick_rise$983 $1398
+ process $group_519
+ assign \wr_pick_rise$832 1'0
+ assign \wr_pick_rise$832 $1273
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 3 \write_en$1400
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 3 $1401
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1402
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1403
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1275
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1276
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1277
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1392
+ connect \A \wr_pick$1267
connect \B \wrpick_XER_xer_ov_en_o
- connect \Y $1402
+ connect \Y $1276
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1404
+ process $group_520
+ assign \wp$1275 1'0
+ assign \wp$1275 $1276
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 3 \addr_en$1278
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 3 $1279
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1280
parameter \WIDTH 3
connect \A 3'000
connect \B 3'100
- connect \S $1402
- connect \Y $1401
+ connect \S \wp$1275
+ connect \Y $1279
end
- process $group_458
- assign \write_en$1400 3'000
- assign \write_en$1400 $1401
+ process $group_521
+ assign \addr_en$1278 3'000
+ assign \addr_en$1278 $1279
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_mul0_xer_ov_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1405
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1406
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1281
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1282
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_xer_ov_ok$128
connect \B \fus_cu_busy_o$22
- connect \Y $1405
+ connect \Y $1281
end
- process $group_459
+ process $group_522
assign \wrflag_mul0_xer_ov_2 1'0
- assign \wrflag_mul0_xer_ov_2 $1405
+ assign \wrflag_mul0_xer_ov_2 $1281
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1407
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1408
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1409
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1283
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1284
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1285
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ov_o [3]
connect \B \wrpick_XER_xer_ov_en_o
- connect \Y $1408
+ connect \Y $1284
end
- process $group_460
- assign \wr_pick$1407 1'0
- assign \wr_pick$1407 $1408
+ process $group_523
+ assign \wr_pick$1283 1'0
+ assign \wr_pick$1283 $1284
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1410
+ wire width 1 \wr_pick_dly$1286
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1410$next
- process $group_461
- assign \wr_pick_dly$1410$next \wr_pick_dly$1410
- assign \wr_pick_dly$1410$next \wr_pick$1407
+ wire width 1 \wr_pick_dly$1286$next
+ process $group_524
+ assign \wr_pick_dly$1286$next \wr_pick_dly$1286
+ assign \wr_pick_dly$1286$next \wr_pick$1283
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1410$next 1'0
+ assign \wr_pick_dly$1286$next 1'0
end
sync init
- update \wr_pick_dly$1410 1'0
+ update \wr_pick_dly$1286 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1410 \wr_pick_dly$1410$next
+ update \wr_pick_dly$1286 \wr_pick_dly$1286$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1411
+ wire width 1 $1287
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1412
+ cell $not $1288
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1410
- connect \Y $1411
+ connect \A \wr_pick_dly$1286
+ connect \Y $1287
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1413
+ wire width 1 $1289
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1414
+ cell $and $1290
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1407
- connect \B $1411
- connect \Y $1413
+ connect \A \wr_pick$1283
+ connect \B $1287
+ connect \Y $1289
end
- process $group_462
- assign \wr_pick_rise$1004 1'0
- assign \wr_pick_rise$1004 $1413
+ process $group_525
+ assign \wr_pick_rise$852 1'0
+ assign \wr_pick_rise$852 $1289
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 3 \write_en$1415
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 3 $1416
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1417
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1418
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1291
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1292
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1293
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1407
+ connect \A \wr_pick$1283
connect \B \wrpick_XER_xer_ov_en_o
- connect \Y $1417
+ connect \Y $1292
+ end
+ process $group_526
+ assign \wp$1291 1'0
+ assign \wp$1291 $1292
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1419
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 3 \addr_en$1294
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 3 $1295
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1296
parameter \WIDTH 3
connect \A 3'000
connect \B 3'100
- connect \S $1417
- connect \Y $1416
+ connect \S \wp$1291
+ connect \Y $1295
end
- process $group_463
- assign \write_en$1415 3'000
- assign \write_en$1415 $1416
+ process $group_527
+ assign \addr_en$1294 3'000
+ assign \addr_en$1294 $1295
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 2 $1420
+ wire width 2 $1297
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1421
+ cell $or $1298
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \fus_dest4_o
connect \B \fus_dest5_o
- connect \Y $1420
+ connect \Y $1297
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 2 $1422
+ wire width 2 $1299
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1423
+ cell $or $1300
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \fus_dest3_o$129
connect \B \fus_dest3_o$130
- connect \Y $1422
+ connect \Y $1299
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 2 $1424
+ wire width 2 $1301
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1425
+ cell $or $1302
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
- connect \A $1420
- connect \B $1422
- connect \Y $1424
+ connect \A $1297
+ connect \B $1299
+ connect \Y $1301
end
- process $group_464
+ process $group_528
assign \xer_data_i$153 2'00
- assign \xer_data_i$153 $1424
+ assign \xer_data_i$153 $1301
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 3 $1426
+ wire width 3 $1303
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1427
+ cell $or $1304
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
- connect \A \write_en$1370
- connect \B \write_en$1385
- connect \Y $1426
+ connect \A \addr_en$1246
+ connect \B \addr_en$1262
+ connect \Y $1303
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 3 $1428
+ wire width 3 $1305
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1429
+ cell $or $1306
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
- connect \A \write_en$1400
- connect \B \write_en$1415
- connect \Y $1428
+ connect \A \addr_en$1278
+ connect \B \addr_en$1294
+ connect \Y $1305
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 3 $1430
+ wire width 3 $1307
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1431
+ cell $or $1308
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
- connect \A $1426
- connect \B $1428
- connect \Y $1430
+ connect \A $1303
+ connect \B $1305
+ connect \Y $1307
end
- process $group_465
+ process $group_529
assign \xer_wen$154 3'000
- assign \xer_wen$154 $1430
+ assign \xer_wen$154 $1307
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_alu0_xer_so_4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1432
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1433
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1309
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1310
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_xer_so_ok
connect \B \fus_cu_busy_o
- connect \Y $1432
+ connect \Y $1309
end
- process $group_466
+ process $group_530
assign \wrflag_alu0_xer_so_4 1'0
- assign \wrflag_alu0_xer_so_4 $1432
+ assign \wrflag_alu0_xer_so_4 $1309
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1434
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1435
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1311
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1312
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o [4]
connect \B \fu_enable [0]
- connect \Y $1434
+ connect \Y $1311
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1436
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1437
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1313
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1314
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$90 [3]
connect \B \fu_enable [5]
- connect \Y $1436
+ connect \Y $1313
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1438
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1439
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1315
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1316
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$93 [3]
connect \B \fu_enable [6]
- connect \Y $1438
+ connect \Y $1315
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1440
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1441
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1317
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1318
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$96 [3]
connect \B \fu_enable [7]
- connect \Y $1440
+ connect \Y $1317
end
- process $group_467
+ process $group_531
assign \wrpick_XER_xer_so_i 4'0000
- assign \wrpick_XER_xer_so_i [0] $1434
- assign \wrpick_XER_xer_so_i [1] $1436
- assign \wrpick_XER_xer_so_i [2] $1438
- assign \wrpick_XER_xer_so_i [3] $1440
+ assign \wrpick_XER_xer_so_i [0] $1311
+ assign \wrpick_XER_xer_so_i [1] $1313
+ assign \wrpick_XER_xer_so_i [2] $1315
+ assign \wrpick_XER_xer_so_i [3] $1317
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1442
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1443
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1444
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1319
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1320
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1321
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_so_o [0]
connect \B \wrpick_XER_xer_so_en_o
- connect \Y $1443
+ connect \Y $1320
end
- process $group_468
- assign \wr_pick$1442 1'0
- assign \wr_pick$1442 $1443
+ process $group_532
+ assign \wr_pick$1319 1'0
+ assign \wr_pick$1319 $1320
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1445
+ wire width 1 \wr_pick_dly$1322
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1445$next
- process $group_469
- assign \wr_pick_dly$1445$next \wr_pick_dly$1445
- assign \wr_pick_dly$1445$next \wr_pick$1442
+ wire width 1 \wr_pick_dly$1322$next
+ process $group_533
+ assign \wr_pick_dly$1322$next \wr_pick_dly$1322
+ assign \wr_pick_dly$1322$next \wr_pick$1319
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1445$next 1'0
+ assign \wr_pick_dly$1322$next 1'0
end
sync init
- update \wr_pick_dly$1445 1'0
+ update \wr_pick_dly$1322 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1445 \wr_pick_dly$1445$next
+ update \wr_pick_dly$1322 \wr_pick_dly$1322$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1446
+ wire width 1 $1323
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1447
+ cell $not $1324
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1445
- connect \Y $1446
+ connect \A \wr_pick_dly$1322
+ connect \Y $1323
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1448
+ wire width 1 $1325
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1449
+ cell $and $1326
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1442
- connect \B $1446
- connect \Y $1448
+ connect \A \wr_pick$1319
+ connect \B $1323
+ connect \Y $1325
end
- process $group_470
- assign \wr_pick_rise$878 1'0
- assign \wr_pick_rise$878 $1448
+ process $group_534
+ assign \wr_pick_rise$734 1'0
+ assign \wr_pick_rise$734 $1325
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 1 \write_en$1450
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1451
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1452
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1453
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1327
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1328
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1329
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1442
+ connect \A \wr_pick$1319
connect \B \wrpick_XER_xer_so_en_o
- connect \Y $1452
+ connect \Y $1328
+ end
+ process $group_535
+ assign \wp$1327 1'0
+ assign \wp$1327 $1328
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1454
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 1 \addr_en$1330
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 1 $1331
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1332
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
- connect \S $1452
- connect \Y $1451
+ connect \S \wp$1327
+ connect \Y $1331
end
- process $group_471
- assign \write_en$1450 1'0
- assign \write_en$1450 $1451
+ process $group_536
+ assign \addr_en$1330 1'0
+ assign \addr_en$1330 $1331
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_spr0_xer_so_3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1455
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1456
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1333
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1334
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_xer_so_ok$131
connect \B \fus_cu_busy_o$16
- connect \Y $1455
+ connect \Y $1333
end
- process $group_472
+ process $group_537
assign \wrflag_spr0_xer_so_3 1'0
- assign \wrflag_spr0_xer_so_3 $1455
+ assign \wrflag_spr0_xer_so_3 $1333
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1457
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1458
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1459
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1335
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1336
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1337
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_so_o [1]
connect \B \wrpick_XER_xer_so_en_o
- connect \Y $1458
+ connect \Y $1336
end
- process $group_473
- assign \wr_pick$1457 1'0
- assign \wr_pick$1457 $1458
+ process $group_538
+ assign \wr_pick$1335 1'0
+ assign \wr_pick$1335 $1336
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1460
+ wire width 1 \wr_pick_dly$1338
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1460$next
- process $group_474
- assign \wr_pick_dly$1460$next \wr_pick_dly$1460
- assign \wr_pick_dly$1460$next \wr_pick$1457
+ wire width 1 \wr_pick_dly$1338$next
+ process $group_539
+ assign \wr_pick_dly$1338$next \wr_pick_dly$1338
+ assign \wr_pick_dly$1338$next \wr_pick$1335
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1460$next 1'0
+ assign \wr_pick_dly$1338$next 1'0
end
sync init
- update \wr_pick_dly$1460 1'0
+ update \wr_pick_dly$1338 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1460 \wr_pick_dly$1460$next
+ update \wr_pick_dly$1338 \wr_pick_dly$1338$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1461
+ wire width 1 $1339
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1462
+ cell $not $1340
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1460
- connect \Y $1461
+ connect \A \wr_pick_dly$1338
+ connect \Y $1339
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1463
+ wire width 1 $1341
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1464
+ cell $and $1342
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1457
- connect \B $1461
- connect \Y $1463
+ connect \A \wr_pick$1335
+ connect \B $1339
+ connect \Y $1341
end
- process $group_475
- assign \wr_pick_rise$961 1'0
- assign \wr_pick_rise$961 $1463
+ process $group_540
+ assign \wr_pick_rise$811 1'0
+ assign \wr_pick_rise$811 $1341
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 1 \write_en$1465
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1466
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1467
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1468
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1343
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1344
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1345
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1457
+ connect \A \wr_pick$1335
connect \B \wrpick_XER_xer_so_en_o
- connect \Y $1467
+ connect \Y $1344
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1469
+ process $group_541
+ assign \wp$1343 1'0
+ assign \wp$1343 $1344
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 1 \addr_en$1346
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 1 $1347
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1348
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
- connect \S $1467
- connect \Y $1466
+ connect \S \wp$1343
+ connect \Y $1347
end
- process $group_476
- assign \write_en$1465 1'0
- assign \write_en$1465 $1466
+ process $group_542
+ assign \addr_en$1346 1'0
+ assign \addr_en$1346 $1347
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_div0_xer_so_3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1470
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1471
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1349
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1350
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_xer_so_ok$132
connect \B \fus_cu_busy_o$19
- connect \Y $1470
+ connect \Y $1349
end
- process $group_477
+ process $group_543
assign \wrflag_div0_xer_so_3 1'0
- assign \wrflag_div0_xer_so_3 $1470
+ assign \wrflag_div0_xer_so_3 $1349
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1472
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1473
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1474
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1351
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1352
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1353
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_so_o [2]
connect \B \wrpick_XER_xer_so_en_o
- connect \Y $1473
+ connect \Y $1352
end
- process $group_478
- assign \wr_pick$1472 1'0
- assign \wr_pick$1472 $1473
+ process $group_544
+ assign \wr_pick$1351 1'0
+ assign \wr_pick$1351 $1352
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1475
+ wire width 1 \wr_pick_dly$1354
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1475$next
- process $group_479
- assign \wr_pick_dly$1475$next \wr_pick_dly$1475
- assign \wr_pick_dly$1475$next \wr_pick$1472
+ wire width 1 \wr_pick_dly$1354$next
+ process $group_545
+ assign \wr_pick_dly$1354$next \wr_pick_dly$1354
+ assign \wr_pick_dly$1354$next \wr_pick$1351
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1475$next 1'0
+ assign \wr_pick_dly$1354$next 1'0
end
sync init
- update \wr_pick_dly$1475 1'0
+ update \wr_pick_dly$1354 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1475 \wr_pick_dly$1475$next
+ update \wr_pick_dly$1354 \wr_pick_dly$1354$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1476
+ wire width 1 $1355
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1477
+ cell $not $1356
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1475
- connect \Y $1476
+ connect \A \wr_pick_dly$1354
+ connect \Y $1355
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1478
+ wire width 1 $1357
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1479
+ cell $and $1358
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1472
- connect \B $1476
- connect \Y $1478
+ connect \A \wr_pick$1351
+ connect \B $1355
+ connect \Y $1357
end
- process $group_480
- assign \wr_pick_rise$984 1'0
- assign \wr_pick_rise$984 $1478
+ process $group_546
+ assign \wr_pick_rise$833 1'0
+ assign \wr_pick_rise$833 $1357
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 1 \write_en$1480
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1481
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1482
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1483
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1359
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1360
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1361
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1472
+ connect \A \wr_pick$1351
connect \B \wrpick_XER_xer_so_en_o
- connect \Y $1482
+ connect \Y $1360
+ end
+ process $group_547
+ assign \wp$1359 1'0
+ assign \wp$1359 $1360
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1484
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 1 \addr_en$1362
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 1 $1363
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1364
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
- connect \S $1482
- connect \Y $1481
+ connect \S \wp$1359
+ connect \Y $1363
end
- process $group_481
- assign \write_en$1480 1'0
- assign \write_en$1480 $1481
+ process $group_548
+ assign \addr_en$1362 1'0
+ assign \addr_en$1362 $1363
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_mul0_xer_so_3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1485
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1486
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1365
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1366
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_xer_so_ok$133
connect \B \fus_cu_busy_o$22
- connect \Y $1485
+ connect \Y $1365
end
- process $group_482
+ process $group_549
assign \wrflag_mul0_xer_so_3 1'0
- assign \wrflag_mul0_xer_so_3 $1485
+ assign \wrflag_mul0_xer_so_3 $1365
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1487
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1488
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1489
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1367
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1368
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1369
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_so_o [3]
connect \B \wrpick_XER_xer_so_en_o
- connect \Y $1488
+ connect \Y $1368
end
- process $group_483
- assign \wr_pick$1487 1'0
- assign \wr_pick$1487 $1488
+ process $group_550
+ assign \wr_pick$1367 1'0
+ assign \wr_pick$1367 $1368
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1490
+ wire width 1 \wr_pick_dly$1370
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1490$next
- process $group_484
- assign \wr_pick_dly$1490$next \wr_pick_dly$1490
- assign \wr_pick_dly$1490$next \wr_pick$1487
+ wire width 1 \wr_pick_dly$1370$next
+ process $group_551
+ assign \wr_pick_dly$1370$next \wr_pick_dly$1370
+ assign \wr_pick_dly$1370$next \wr_pick$1367
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1490$next 1'0
+ assign \wr_pick_dly$1370$next 1'0
end
sync init
- update \wr_pick_dly$1490 1'0
+ update \wr_pick_dly$1370 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1490 \wr_pick_dly$1490$next
+ update \wr_pick_dly$1370 \wr_pick_dly$1370$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1491
+ wire width 1 $1371
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1492
+ cell $not $1372
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1490
- connect \Y $1491
+ connect \A \wr_pick_dly$1370
+ connect \Y $1371
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1493
+ wire width 1 $1373
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1494
+ cell $and $1374
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1487
- connect \B $1491
- connect \Y $1493
+ connect \A \wr_pick$1367
+ connect \B $1371
+ connect \Y $1373
end
- process $group_485
- assign \wr_pick_rise$1005 1'0
- assign \wr_pick_rise$1005 $1493
+ process $group_552
+ assign \wr_pick_rise$853 1'0
+ assign \wr_pick_rise$853 $1373
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 1 \write_en$1495
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1496
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1497
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1498
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1375
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1376
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1377
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1487
+ connect \A \wr_pick$1367
connect \B \wrpick_XER_xer_so_en_o
- connect \Y $1497
+ connect \Y $1376
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1499
+ process $group_553
+ assign \wp$1375 1'0
+ assign \wp$1375 $1376
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 1 \addr_en$1378
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 1 $1379
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1380
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
- connect \S $1497
- connect \Y $1496
+ connect \S \wp$1375
+ connect \Y $1379
end
- process $group_486
- assign \write_en$1495 1'0
- assign \write_en$1495 $1496
+ process $group_554
+ assign \addr_en$1378 1'0
+ assign \addr_en$1378 $1379
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 2 $1500
+ wire width 2 $1381
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 1 $1501
+ wire width 1 $1382
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1502
+ cell $or $1383
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_dest5_o$134
connect \B \fus_dest4_o$135
- connect \Y $1501
+ connect \Y $1382
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 1 $1503
+ wire width 1 $1384
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1504
+ cell $or $1385
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_dest4_o$136
connect \B \fus_dest4_o$137
- connect \Y $1503
+ connect \Y $1384
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 1 $1505
+ wire width 1 $1386
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1506
+ cell $or $1387
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $1501
- connect \B $1503
- connect \Y $1505
+ connect \A $1382
+ connect \B $1384
+ connect \Y $1386
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $pos $1507
+ cell $pos $1388
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 2
- connect \A $1505
- connect \Y $1500
+ connect \A $1386
+ connect \Y $1381
end
- process $group_487
+ process $group_555
assign \xer_data_i$155 2'00
- assign \xer_data_i$155 $1500
+ assign \xer_data_i$155 $1381
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 3 $1508
+ wire width 3 $1389
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 1 $1509
+ wire width 1 $1390
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1510
+ cell $or $1391
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \write_en$1450
- connect \B \write_en$1465
- connect \Y $1509
+ connect \A \addr_en$1330
+ connect \B \addr_en$1346
+ connect \Y $1390
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 1 $1511
+ wire width 1 $1392
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1512
+ cell $or $1393
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \write_en$1480
- connect \B \write_en$1495
- connect \Y $1511
+ connect \A \addr_en$1362
+ connect \B \addr_en$1378
+ connect \Y $1392
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 1 $1513
+ wire width 1 $1394
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1514
+ cell $or $1395
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $1509
- connect \B $1511
- connect \Y $1513
+ connect \A $1390
+ connect \B $1392
+ connect \Y $1394
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $pos $1515
+ cell $pos $1396
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 3
- connect \A $1513
- connect \Y $1508
+ connect \A $1394
+ connect \Y $1389
end
- process $group_488
+ process $group_556
assign \xer_wen$156 3'000
- assign \xer_wen$156 $1508
+ assign \xer_wen$156 $1389
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_branch0_fast1_0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1516
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1517
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1397
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1398
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_fast1_ok
connect \B \fus_cu_busy_o$7
- connect \Y $1516
+ connect \Y $1397
end
- process $group_489
+ process $group_557
assign \wrflag_branch0_fast1_0 1'0
- assign \wrflag_branch0_fast1_0 $1516
+ assign \wrflag_branch0_fast1_0 $1397
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1518
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1519
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1399
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1400
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$138 [0]
connect \B \fu_enable [2]
- connect \Y $1518
+ connect \Y $1399
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1520
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1521
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1401
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1402
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$84 [1]
connect \B \fu_enable [3]
- connect \Y $1520
+ connect \Y $1401
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1522
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1523
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1403
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1404
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$90 [2]
connect \B \fu_enable [5]
- connect \Y $1522
+ connect \Y $1403
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1524
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1525
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1405
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1406
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$138 [1]
connect \B \fu_enable [2]
- connect \Y $1524
+ connect \Y $1405
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1526
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1527
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1407
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1408
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$84 [2]
connect \B \fu_enable [3]
- connect \Y $1526
+ connect \Y $1407
end
- process $group_490
+ process $group_558
assign \wrpick_FAST_fast1_i 5'00000
- assign \wrpick_FAST_fast1_i [0] $1518
- assign \wrpick_FAST_fast1_i [1] $1520
- assign \wrpick_FAST_fast1_i [2] $1522
- assign \wrpick_FAST_fast1_i [3] $1524
- assign \wrpick_FAST_fast1_i [4] $1526
+ assign \wrpick_FAST_fast1_i [0] $1399
+ assign \wrpick_FAST_fast1_i [1] $1401
+ assign \wrpick_FAST_fast1_i [2] $1403
+ assign \wrpick_FAST_fast1_i [3] $1405
+ assign \wrpick_FAST_fast1_i [4] $1407
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1528
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1529
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1530
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1409
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1410
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1411
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_FAST_fast1_o [0]
connect \B \wrpick_FAST_fast1_en_o
- connect \Y $1529
+ connect \Y $1410
end
- process $group_491
- assign \wr_pick$1528 1'0
- assign \wr_pick$1528 $1529
+ process $group_559
+ assign \wr_pick$1409 1'0
+ assign \wr_pick$1409 $1410
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1531
+ wire width 1 \wr_pick_dly$1412
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1531$next
- process $group_492
- assign \wr_pick_dly$1531$next \wr_pick_dly$1531
- assign \wr_pick_dly$1531$next \wr_pick$1528
+ wire width 1 \wr_pick_dly$1412$next
+ process $group_560
+ assign \wr_pick_dly$1412$next \wr_pick_dly$1412
+ assign \wr_pick_dly$1412$next \wr_pick$1409
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1531$next 1'0
+ assign \wr_pick_dly$1412$next 1'0
end
sync init
- update \wr_pick_dly$1531 1'0
+ update \wr_pick_dly$1412 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1531 \wr_pick_dly$1531$next
+ update \wr_pick_dly$1412 \wr_pick_dly$1412$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$1532
+ wire width 1 \wr_pick_rise$1413
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1533
+ wire width 1 $1414
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1534
+ cell $not $1415
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1531
- connect \Y $1533
+ connect \A \wr_pick_dly$1412
+ connect \Y $1414
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1535
+ wire width 1 $1416
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1536
+ cell $and $1417
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1528
- connect \B $1533
- connect \Y $1535
+ connect \A \wr_pick$1409
+ connect \B $1414
+ connect \Y $1416
end
- process $group_493
- assign \wr_pick_rise$1532 1'0
- assign \wr_pick_rise$1532 $1535
+ process $group_561
+ assign \wr_pick_rise$1413 1'0
+ assign \wr_pick_rise$1413 $1416
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$1537
+ wire width 1 \wr_pick_rise$1418
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
- wire width 1 \wr_pick_rise$1538
- process $group_494
+ wire width 1 \wr_pick_rise$1419
+ process $group_562
assign \fus_cu_wr__go_i$139 3'000
- assign \fus_cu_wr__go_i$139 [0] \wr_pick_rise$1532
- assign \fus_cu_wr__go_i$139 [1] \wr_pick_rise$1537
- assign \fus_cu_wr__go_i$139 [2] \wr_pick_rise$1538
+ assign \fus_cu_wr__go_i$139 [0] \wr_pick_rise$1413
+ assign \fus_cu_wr__go_i$139 [1] \wr_pick_rise$1418
+ assign \fus_cu_wr__go_i$139 [2] \wr_pick_rise$1419
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1420
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1421
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1422
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_pick$1409
+ connect \B \wrpick_FAST_fast1_en_o
+ connect \Y $1421
+ end
+ process $group_563
+ assign \wp$1420 1'0
+ assign \wp$1420 $1421
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 8 \write_en$1539
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 8 \addr_en$1423
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178"
- wire width 8 $1540
+ wire width 8 $1424
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178"
- cell $sshl $1541
+ cell $sshl $1425
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 1'1
connect \B \pdecode2_fasto1
- connect \Y $1540
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 8 $1542
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1543
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1544
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_pick$1528
- connect \B \wrpick_FAST_fast1_en_o
- connect \Y $1543
+ connect \Y $1424
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1545
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 8 $1426
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1427
parameter \WIDTH 8
connect \A 8'00000000
- connect \B $1540
- connect \S $1543
- connect \Y $1542
+ connect \B $1424
+ connect \S \wp$1420
+ connect \Y $1426
end
- process $group_495
- assign \write_en$1539 8'00000000
- assign \write_en$1539 $1542
+ process $group_564
+ assign \addr_en$1423 8'00000000
+ assign \addr_en$1423 $1426
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_trap0_fast1_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1546
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1547
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1428
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1429
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_fast1_ok$140
connect \B \fus_cu_busy_o$10
- connect \Y $1546
+ connect \Y $1428
end
- process $group_496
+ process $group_565
assign \wrflag_trap0_fast1_1 1'0
- assign \wrflag_trap0_fast1_1 $1546
+ assign \wrflag_trap0_fast1_1 $1428
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1548
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1549
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1550
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1430
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1431
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1432
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_FAST_fast1_o [1]
connect \B \wrpick_FAST_fast1_en_o
- connect \Y $1549
+ connect \Y $1431
end
- process $group_497
- assign \wr_pick$1548 1'0
- assign \wr_pick$1548 $1549
+ process $group_566
+ assign \wr_pick$1430 1'0
+ assign \wr_pick$1430 $1431
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1551
+ wire width 1 \wr_pick_dly$1433
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1551$next
- process $group_498
- assign \wr_pick_dly$1551$next \wr_pick_dly$1551
- assign \wr_pick_dly$1551$next \wr_pick$1548
+ wire width 1 \wr_pick_dly$1433$next
+ process $group_567
+ assign \wr_pick_dly$1433$next \wr_pick_dly$1433
+ assign \wr_pick_dly$1433$next \wr_pick$1430
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1551$next 1'0
+ assign \wr_pick_dly$1433$next 1'0
end
sync init
- update \wr_pick_dly$1551 1'0
+ update \wr_pick_dly$1433 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1551 \wr_pick_dly$1551$next
+ update \wr_pick_dly$1433 \wr_pick_dly$1433$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1552
+ wire width 1 $1434
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1553
+ cell $not $1435
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1551
- connect \Y $1552
+ connect \A \wr_pick_dly$1433
+ connect \Y $1434
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1554
+ wire width 1 $1436
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1555
+ cell $and $1437
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1548
- connect \B $1552
- connect \Y $1554
+ connect \A \wr_pick$1430
+ connect \B $1434
+ connect \Y $1436
end
- process $group_499
- assign \wr_pick_rise$917 1'0
- assign \wr_pick_rise$917 $1554
+ process $group_568
+ assign \wr_pick_rise$769 1'0
+ assign \wr_pick_rise$769 $1436
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1438
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1439
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1440
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_pick$1430
+ connect \B \wrpick_FAST_fast1_en_o
+ connect \Y $1439
+ end
+ process $group_569
+ assign \wp$1438 1'0
+ assign \wp$1438 $1439
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 8 \write_en$1556
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 8 \addr_en$1441
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178"
- wire width 8 $1557
+ wire width 8 $1442
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178"
- cell $sshl $1558
+ cell $sshl $1443
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 1'1
connect \B \pdecode2_fasto1
- connect \Y $1557
+ connect \Y $1442
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 8 $1559
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1560
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1561
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_pick$1548
- connect \B \wrpick_FAST_fast1_en_o
- connect \Y $1560
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1562
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 8 $1444
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1445
parameter \WIDTH 8
connect \A 8'00000000
- connect \B $1557
- connect \S $1560
- connect \Y $1559
+ connect \B $1442
+ connect \S \wp$1438
+ connect \Y $1444
end
- process $group_500
- assign \write_en$1556 8'00000000
- assign \write_en$1556 $1559
+ process $group_570
+ assign \addr_en$1441 8'00000000
+ assign \addr_en$1441 $1444
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_spr0_fast1_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1563
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1564
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1446
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1447
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_fast1_ok$141
connect \B \fus_cu_busy_o$16
- connect \Y $1563
+ connect \Y $1446
end
- process $group_501
+ process $group_571
assign \wrflag_spr0_fast1_2 1'0
- assign \wrflag_spr0_fast1_2 $1563
+ assign \wrflag_spr0_fast1_2 $1446
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1565
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1566
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1567
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1448
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1449
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1450
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_FAST_fast1_o [2]
connect \B \wrpick_FAST_fast1_en_o
- connect \Y $1566
+ connect \Y $1449
end
- process $group_502
- assign \wr_pick$1565 1'0
- assign \wr_pick$1565 $1566
+ process $group_572
+ assign \wr_pick$1448 1'0
+ assign \wr_pick$1448 $1449
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1568
+ wire width 1 \wr_pick_dly$1451
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1568$next
- process $group_503
- assign \wr_pick_dly$1568$next \wr_pick_dly$1568
- assign \wr_pick_dly$1568$next \wr_pick$1565
+ wire width 1 \wr_pick_dly$1451$next
+ process $group_573
+ assign \wr_pick_dly$1451$next \wr_pick_dly$1451
+ assign \wr_pick_dly$1451$next \wr_pick$1448
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1568$next 1'0
+ assign \wr_pick_dly$1451$next 1'0
end
sync init
- update \wr_pick_dly$1568 1'0
+ update \wr_pick_dly$1451 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1568 \wr_pick_dly$1568$next
+ update \wr_pick_dly$1451 \wr_pick_dly$1451$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1569
+ wire width 1 $1452
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1570
+ cell $not $1453
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1568
- connect \Y $1569
+ connect \A \wr_pick_dly$1451
+ connect \Y $1452
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1571
+ wire width 1 $1454
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1572
+ cell $and $1455
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1565
- connect \B $1569
- connect \Y $1571
+ connect \A \wr_pick$1448
+ connect \B $1452
+ connect \Y $1454
end
- process $group_504
- assign \wr_pick_rise$962 1'0
- assign \wr_pick_rise$962 $1571
+ process $group_574
+ assign \wr_pick_rise$812 1'0
+ assign \wr_pick_rise$812 $1454
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 8 \write_en$1573
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1456
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1457
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1458
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_pick$1448
+ connect \B \wrpick_FAST_fast1_en_o
+ connect \Y $1457
+ end
+ process $group_575
+ assign \wp$1456 1'0
+ assign \wp$1456 $1457
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 8 \addr_en$1459
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178"
- wire width 8 $1574
+ wire width 8 $1460
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178"
- cell $sshl $1575
+ cell $sshl $1461
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 1'1
connect \B \pdecode2_fasto1
- connect \Y $1574
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 8 $1576
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1577
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1578
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_pick$1565
- connect \B \wrpick_FAST_fast1_en_o
- connect \Y $1577
+ connect \Y $1460
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1579
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 8 $1462
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1463
parameter \WIDTH 8
connect \A 8'00000000
- connect \B $1574
- connect \S $1577
- connect \Y $1576
+ connect \B $1460
+ connect \S \wp$1456
+ connect \Y $1462
end
- process $group_505
- assign \write_en$1573 8'00000000
- assign \write_en$1573 $1576
+ process $group_576
+ assign \addr_en$1459 8'00000000
+ assign \addr_en$1459 $1462
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_branch0_fast1_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1580
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1581
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1464
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1465
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_fast2_ok
connect \B \fus_cu_busy_o$7
- connect \Y $1580
+ connect \Y $1464
end
- process $group_506
+ process $group_577
assign \wrflag_branch0_fast1_1 1'0
- assign \wrflag_branch0_fast1_1 $1580
+ assign \wrflag_branch0_fast1_1 $1464
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1582
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1583
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1584
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1466
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1467
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1468
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_FAST_fast1_o [3]
connect \B \wrpick_FAST_fast1_en_o
- connect \Y $1583
+ connect \Y $1467
end
- process $group_507
- assign \wr_pick$1582 1'0
- assign \wr_pick$1582 $1583
+ process $group_578
+ assign \wr_pick$1466 1'0
+ assign \wr_pick$1466 $1467
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1585
+ wire width 1 \wr_pick_dly$1469
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1585$next
- process $group_508
- assign \wr_pick_dly$1585$next \wr_pick_dly$1585
- assign \wr_pick_dly$1585$next \wr_pick$1582
+ wire width 1 \wr_pick_dly$1469$next
+ process $group_579
+ assign \wr_pick_dly$1469$next \wr_pick_dly$1469
+ assign \wr_pick_dly$1469$next \wr_pick$1466
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1585$next 1'0
+ assign \wr_pick_dly$1469$next 1'0
end
sync init
- update \wr_pick_dly$1585 1'0
+ update \wr_pick_dly$1469 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1585 \wr_pick_dly$1585$next
+ update \wr_pick_dly$1469 \wr_pick_dly$1469$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1586
+ wire width 1 $1470
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1587
+ cell $not $1471
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1585
- connect \Y $1586
+ connect \A \wr_pick_dly$1469
+ connect \Y $1470
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1588
+ wire width 1 $1472
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1589
+ cell $and $1473
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1582
- connect \B $1586
- connect \Y $1588
+ connect \A \wr_pick$1466
+ connect \B $1470
+ connect \Y $1472
end
- process $group_509
- assign \wr_pick_rise$1537 1'0
- assign \wr_pick_rise$1537 $1588
+ process $group_580
+ assign \wr_pick_rise$1418 1'0
+ assign \wr_pick_rise$1418 $1472
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1474
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1475
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1476
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_pick$1466
+ connect \B \wrpick_FAST_fast1_en_o
+ connect \Y $1475
+ end
+ process $group_581
+ assign \wp$1474 1'0
+ assign \wp$1474 $1475
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 8 \write_en$1590
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 8 \addr_en$1477
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180"
- wire width 8 $1591
+ wire width 8 $1478
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180"
- cell $sshl $1592
+ cell $sshl $1479
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 1'1
connect \B \pdecode2_fasto2
- connect \Y $1591
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 8 $1593
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1594
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1595
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_pick$1582
- connect \B \wrpick_FAST_fast1_en_o
- connect \Y $1594
+ connect \Y $1478
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1596
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 8 $1480
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1481
parameter \WIDTH 8
connect \A 8'00000000
- connect \B $1591
- connect \S $1594
- connect \Y $1593
+ connect \B $1478
+ connect \S \wp$1474
+ connect \Y $1480
end
- process $group_510
- assign \write_en$1590 8'00000000
- assign \write_en$1590 $1593
+ process $group_582
+ assign \addr_en$1477 8'00000000
+ assign \addr_en$1477 $1480
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_trap0_fast1_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1597
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1598
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1482
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1483
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_fast2_ok$142
connect \B \fus_cu_busy_o$10
- connect \Y $1597
+ connect \Y $1482
end
- process $group_511
+ process $group_583
assign \wrflag_trap0_fast1_2 1'0
- assign \wrflag_trap0_fast1_2 $1597
+ assign \wrflag_trap0_fast1_2 $1482
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1599
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1600
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1601
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1484
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1485
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1486
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_FAST_fast1_o [4]
connect \B \wrpick_FAST_fast1_en_o
- connect \Y $1600
+ connect \Y $1485
end
- process $group_512
- assign \wr_pick$1599 1'0
- assign \wr_pick$1599 $1600
+ process $group_584
+ assign \wr_pick$1484 1'0
+ assign \wr_pick$1484 $1485
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1602
+ wire width 1 \wr_pick_dly$1487
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1602$next
- process $group_513
- assign \wr_pick_dly$1602$next \wr_pick_dly$1602
- assign \wr_pick_dly$1602$next \wr_pick$1599
+ wire width 1 \wr_pick_dly$1487$next
+ process $group_585
+ assign \wr_pick_dly$1487$next \wr_pick_dly$1487
+ assign \wr_pick_dly$1487$next \wr_pick$1484
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1602$next 1'0
+ assign \wr_pick_dly$1487$next 1'0
end
sync init
- update \wr_pick_dly$1602 1'0
+ update \wr_pick_dly$1487 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1602 \wr_pick_dly$1602$next
+ update \wr_pick_dly$1487 \wr_pick_dly$1487$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1603
+ wire width 1 $1488
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1604
+ cell $not $1489
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1602
- connect \Y $1603
+ connect \A \wr_pick_dly$1487
+ connect \Y $1488
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1605
+ wire width 1 $1490
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1606
+ cell $and $1491
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1599
- connect \B $1603
- connect \Y $1605
+ connect \A \wr_pick$1484
+ connect \B $1488
+ connect \Y $1490
end
- process $group_514
- assign \wr_pick_rise$918 1'0
- assign \wr_pick_rise$918 $1605
+ process $group_586
+ assign \wr_pick_rise$770 1'0
+ assign \wr_pick_rise$770 $1490
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 8 \write_en$1607
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1492
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1493
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1494
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_pick$1484
+ connect \B \wrpick_FAST_fast1_en_o
+ connect \Y $1493
+ end
+ process $group_587
+ assign \wp$1492 1'0
+ assign \wp$1492 $1493
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 8 \addr_en$1495
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180"
- wire width 8 $1608
+ wire width 8 $1496
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180"
- cell $sshl $1609
+ cell $sshl $1497
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 1'1
connect \B \pdecode2_fasto2
- connect \Y $1608
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 8 $1610
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1611
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1612
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_pick$1599
- connect \B \wrpick_FAST_fast1_en_o
- connect \Y $1611
+ connect \Y $1496
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1613
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 8 $1498
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1499
parameter \WIDTH 8
connect \A 8'00000000
- connect \B $1608
- connect \S $1611
- connect \Y $1610
+ connect \B $1496
+ connect \S \wp$1492
+ connect \Y $1498
end
- process $group_515
- assign \write_en$1607 8'00000000
- assign \write_en$1607 $1610
+ process $group_588
+ assign \addr_en$1495 8'00000000
+ assign \addr_en$1495 $1498
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $1614
+ wire width 64 $1500
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1615
+ cell $or $1501
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \fus_dest1_o$143
connect \B \fus_dest2_o$144
- connect \Y $1614
+ connect \Y $1500
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $1616
+ wire width 64 $1502
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1617
+ cell $or $1503
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \fus_dest2_o$146
connect \B \fus_dest3_o$147
- connect \Y $1616
+ connect \Y $1502
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $1618
+ wire width 64 $1504
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1619
+ cell $or $1505
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
connect \A \fus_dest3_o$145
- connect \B $1616
- connect \Y $1618
+ connect \B $1502
+ connect \Y $1504
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 64 $1620
+ wire width 64 $1506
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1621
+ cell $or $1507
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $1614
- connect \B $1618
- connect \Y $1620
+ connect \A $1500
+ connect \B $1504
+ connect \Y $1506
end
- process $group_516
+ process $group_589
assign \fast_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fast_data_i $1620
+ assign \fast_data_i $1506
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 8 $1622
+ wire width 8 $1508
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 8 $1623
+ wire width 8 $1509
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1624
+ cell $or $1510
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A \write_en$1539
- connect \B \write_en$1556
- connect \Y $1623
+ connect \A \addr_en$1423
+ connect \B \addr_en$1441
+ connect \Y $1509
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 8 $1625
+ wire width 8 $1511
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1626
+ cell $or $1512
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A \write_en$1590
- connect \B \write_en$1607
- connect \Y $1625
+ connect \A \addr_en$1477
+ connect \B \addr_en$1495
+ connect \Y $1511
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 8 $1627
+ wire width 8 $1513
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1628
+ cell $or $1514
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A \write_en$1573
- connect \B $1625
- connect \Y $1627
+ connect \A \addr_en$1459
+ connect \B $1511
+ connect \Y $1513
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- wire width 8 $1629
+ wire width 8 $1515
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
- cell $or $1630
+ cell $or $1516
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $1623
- connect \B $1627
- connect \Y $1629
+ connect \A $1509
+ connect \B $1513
+ connect \Y $1515
end
- connect $1622 $1629
- process $group_517
+ connect $1508 $1515
+ process $group_590
assign \fast_wen 5'00000
- assign \fast_wen $1622 [4:0]
+ assign \fast_wen $1508 [4:0]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_branch0_nia_2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1631
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1632
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1517
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1518
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_nia_ok
connect \B \fus_cu_busy_o$7
- connect \Y $1631
+ connect \Y $1517
end
- process $group_518
+ process $group_591
assign \wrflag_branch0_nia_2 1'0
- assign \wrflag_branch0_nia_2 $1631
+ assign \wrflag_branch0_nia_2 $1517
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1633
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1634
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1519
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1520
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$138 [2]
connect \B \fu_enable [2]
- connect \Y $1633
+ connect \Y $1519
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1635
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1636
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1521
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1522
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$84 [3]
connect \B \fu_enable [3]
- connect \Y $1635
+ connect \Y $1521
end
- process $group_519
+ process $group_592
assign \wrpick_STATE_nia_i 2'00
- assign \wrpick_STATE_nia_i [0] $1633
- assign \wrpick_STATE_nia_i [1] $1635
+ assign \wrpick_STATE_nia_i [0] $1519
+ assign \wrpick_STATE_nia_i [1] $1521
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1637
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1638
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1639
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1523
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1524
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1525
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_STATE_nia_o [0]
connect \B \wrpick_STATE_nia_en_o
- connect \Y $1638
+ connect \Y $1524
end
- process $group_520
- assign \wr_pick$1637 1'0
- assign \wr_pick$1637 $1638
+ process $group_593
+ assign \wr_pick$1523 1'0
+ assign \wr_pick$1523 $1524
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1640
+ wire width 1 \wr_pick_dly$1526
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1640$next
- process $group_521
- assign \wr_pick_dly$1640$next \wr_pick_dly$1640
- assign \wr_pick_dly$1640$next \wr_pick$1637
+ wire width 1 \wr_pick_dly$1526$next
+ process $group_594
+ assign \wr_pick_dly$1526$next \wr_pick_dly$1526
+ assign \wr_pick_dly$1526$next \wr_pick$1523
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1640$next 1'0
+ assign \wr_pick_dly$1526$next 1'0
end
sync init
- update \wr_pick_dly$1640 1'0
+ update \wr_pick_dly$1526 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1640 \wr_pick_dly$1640$next
+ update \wr_pick_dly$1526 \wr_pick_dly$1526$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1641
+ wire width 1 $1527
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1642
+ cell $not $1528
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1640
- connect \Y $1641
+ connect \A \wr_pick_dly$1526
+ connect \Y $1527
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1643
+ wire width 1 $1529
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1644
+ cell $and $1530
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1637
- connect \B $1641
- connect \Y $1643
+ connect \A \wr_pick$1523
+ connect \B $1527
+ connect \Y $1529
end
- process $group_522
- assign \wr_pick_rise$1538 1'0
- assign \wr_pick_rise$1538 $1643
+ process $group_595
+ assign \wr_pick_rise$1419 1'0
+ assign \wr_pick_rise$1419 $1529
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 1 \write_en$1645
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1646
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1647
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1648
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1531
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1532
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1533
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1637
+ connect \A \wr_pick$1523
connect \B \wrpick_STATE_nia_en_o
- connect \Y $1647
+ connect \Y $1532
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1649
+ process $group_596
+ assign \wp$1531 1'0
+ assign \wp$1531 $1532
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 1 \addr_en$1534
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 1 $1535
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1536
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
- connect \S $1647
- connect \Y $1646
+ connect \S \wp$1531
+ connect \Y $1535
end
- process $group_523
- assign \write_en$1645 1'0
- assign \write_en$1645 $1646
+ process $group_597
+ assign \addr_en$1534 1'0
+ assign \addr_en$1534 $1535
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_trap0_nia_3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1650
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1651
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1537
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1538
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_nia_ok$148
connect \B \fus_cu_busy_o$10
- connect \Y $1650
+ connect \Y $1537
end
- process $group_524
+ process $group_598
assign \wrflag_trap0_nia_3 1'0
- assign \wrflag_trap0_nia_3 $1650
+ assign \wrflag_trap0_nia_3 $1537
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1652
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1653
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1654
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1539
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1540
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1541
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_STATE_nia_o [1]
connect \B \wrpick_STATE_nia_en_o
- connect \Y $1653
+ connect \Y $1540
end
- process $group_525
- assign \wr_pick$1652 1'0
- assign \wr_pick$1652 $1653
+ process $group_599
+ assign \wr_pick$1539 1'0
+ assign \wr_pick$1539 $1540
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1655
+ wire width 1 \wr_pick_dly$1542
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1655$next
- process $group_526
- assign \wr_pick_dly$1655$next \wr_pick_dly$1655
- assign \wr_pick_dly$1655$next \wr_pick$1652
+ wire width 1 \wr_pick_dly$1542$next
+ process $group_600
+ assign \wr_pick_dly$1542$next \wr_pick_dly$1542
+ assign \wr_pick_dly$1542$next \wr_pick$1539
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1655$next 1'0
+ assign \wr_pick_dly$1542$next 1'0
end
sync init
- update \wr_pick_dly$1655 1'0
+ update \wr_pick_dly$1542 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1655 \wr_pick_dly$1655$next
+ update \wr_pick_dly$1542 \wr_pick_dly$1542$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1656
+ wire width 1 $1543
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1657
+ cell $not $1544
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1655
- connect \Y $1656
+ connect \A \wr_pick_dly$1542
+ connect \Y $1543
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1658
+ wire width 1 $1545
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1659
+ cell $and $1546
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1652
- connect \B $1656
- connect \Y $1658
+ connect \A \wr_pick$1539
+ connect \B $1543
+ connect \Y $1545
end
- process $group_527
- assign \wr_pick_rise$919 1'0
- assign \wr_pick_rise$919 $1658
+ process $group_601
+ assign \wr_pick_rise$771 1'0
+ assign \wr_pick_rise$771 $1545
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 1 \write_en$1660
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1661
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1662
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1663
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1547
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1548
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1549
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1652
+ connect \A \wr_pick$1539
connect \B \wrpick_STATE_nia_en_o
- connect \Y $1662
+ connect \Y $1548
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1664
+ process $group_602
+ assign \wp$1547 1'0
+ assign \wp$1547 $1548
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 1 \addr_en$1550
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 1 $1551
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1552
parameter \WIDTH 1
connect \A 1'0
connect \B 1'1
- connect \S $1662
- connect \Y $1661
+ connect \S \wp$1547
+ connect \Y $1551
end
- process $group_528
- assign \write_en$1660 1'0
- assign \write_en$1660 $1661
+ process $group_603
+ assign \addr_en$1550 1'0
+ assign \addr_en$1550 $1551
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 64 $1665
+ wire width 64 $1553
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1666
+ cell $or $1554
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \fus_dest3_o$149
connect \B \fus_dest4_o$150
- connect \Y $1665
+ connect \Y $1553
end
- process $group_529
+ process $group_604
assign \state_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \state_data_i $1665
+ assign \state_data_i $1553
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 2 $1667
+ wire width 2 $1555
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- wire width 1 $1668
+ wire width 1 $1556
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $or $1669
+ cell $or $1557
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \write_en$1645
- connect \B \write_en$1660
- connect \Y $1668
+ connect \A \addr_en$1534
+ connect \B \addr_en$1550
+ connect \Y $1556
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
- cell $pos $1670
+ cell $pos $1558
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 2
- connect \A $1668
- connect \Y $1667
+ connect \A $1556
+ connect \Y $1555
end
- process $group_530
+ process $group_605
assign \state_nia_wen 2'00
- assign \state_nia_wen $1667
+ assign \state_nia_wen $1555
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_trap0_msr_4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1671
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1672
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1559
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1560
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_msr_ok
connect \B \fus_cu_busy_o$10
- connect \Y $1671
+ connect \Y $1559
end
- process $group_531
+ process $group_606
assign \wrflag_trap0_msr_4 1'0
- assign \wrflag_trap0_msr_4 $1671
+ assign \wrflag_trap0_msr_4 $1559
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1673
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1674
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1561
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1562
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$84 [4]
connect \B \fu_enable [3]
- connect \Y $1673
+ connect \Y $1561
end
- process $group_532
+ process $group_607
assign \wrpick_STATE_msr_i 1'0
- assign \wrpick_STATE_msr_i $1673
+ assign \wrpick_STATE_msr_i $1561
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1675
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1676
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1677
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1563
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1564
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1565
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_STATE_msr_o
connect \B \wrpick_STATE_msr_en_o
- connect \Y $1676
+ connect \Y $1564
end
- process $group_533
- assign \wr_pick$1675 1'0
- assign \wr_pick$1675 $1676
+ process $group_608
+ assign \wr_pick$1563 1'0
+ assign \wr_pick$1563 $1564
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1678
+ wire width 1 \wr_pick_dly$1566
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1678$next
- process $group_534
- assign \wr_pick_dly$1678$next \wr_pick_dly$1678
- assign \wr_pick_dly$1678$next \wr_pick$1675
+ wire width 1 \wr_pick_dly$1566$next
+ process $group_609
+ assign \wr_pick_dly$1566$next \wr_pick_dly$1566
+ assign \wr_pick_dly$1566$next \wr_pick$1563
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1678$next 1'0
+ assign \wr_pick_dly$1566$next 1'0
end
sync init
- update \wr_pick_dly$1678 1'0
+ update \wr_pick_dly$1566 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1678 \wr_pick_dly$1678$next
+ update \wr_pick_dly$1566 \wr_pick_dly$1566$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1679
+ wire width 1 $1567
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1680
+ cell $not $1568
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1678
- connect \Y $1679
+ connect \A \wr_pick_dly$1566
+ connect \Y $1567
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1681
+ wire width 1 $1569
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1682
+ cell $and $1570
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1675
- connect \B $1679
- connect \Y $1681
+ connect \A \wr_pick$1563
+ connect \B $1567
+ connect \Y $1569
end
- process $group_535
- assign \wr_pick_rise$920 1'0
- assign \wr_pick_rise$920 $1681
+ process $group_610
+ assign \wr_pick_rise$772 1'0
+ assign \wr_pick_rise$772 $1569
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:341"
- wire width 2 \write_en$1683
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 2 $1684
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1685
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1686
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1571
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1572
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1573
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1675
+ connect \A \wr_pick$1563
connect \B \wrpick_STATE_msr_en_o
- connect \Y $1685
+ connect \Y $1572
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1687
+ process $group_611
+ assign \wp$1571 1'0
+ assign \wp$1571 $1572
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 2 \addr_en$1574
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 2 $1575
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1576
parameter \WIDTH 2
connect \A 2'00
connect \B 2'10
- connect \S $1685
- connect \Y $1684
+ connect \S \wp$1571
+ connect \Y $1575
end
- process $group_536
- assign \write_en$1683 2'00
- assign \write_en$1683 $1684
+ process $group_612
+ assign \addr_en$1574 2'00
+ assign \addr_en$1574 $1575
sync init
end
- process $group_537
+ process $group_613
assign \state_data_i$157 64'0000000000000000000000000000000000000000000000000000000000000000
assign \state_data_i$157 \fus_dest5_o$151
sync init
end
- process $group_538
+ process $group_614
assign \state_wen 2'00
- assign \state_wen \write_en$1683
+ assign \state_wen \addr_en$1574
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347"
wire width 1 \wrflag_spr0_spr1_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- wire width 1 $1688
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
- cell $and $1689
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ wire width 1 $1577
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348"
+ cell $and $1578
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_spr1_ok
connect \B \fus_cu_busy_o$16
- connect \Y $1688
+ connect \Y $1577
end
- process $group_539
+ process $group_615
assign \wrflag_spr0_spr1_1 1'0
- assign \wrflag_spr0_spr1_1 $1688
+ assign \wrflag_spr0_spr1_1 $1577
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- wire width 1 $1690
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:331"
- cell $and $1691
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ wire width 1 $1579
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352"
+ cell $and $1580
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fus_cu_wr__rel_o$90 [1]
connect \B \fu_enable [5]
- connect \Y $1690
+ connect \Y $1579
end
- process $group_540
+ process $group_616
assign \wrpick_SPR_spr1_i 1'0
- assign \wrpick_SPR_spr1_i $1690
+ assign \wrpick_SPR_spr1_i $1579
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
- wire width 1 \wr_pick$1692
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- wire width 1 $1693
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:335"
- cell $and $1694
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355"
+ wire width 1 \wr_pick$1581
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ wire width 1 $1582
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356"
+ cell $and $1583
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_SPR_spr1_o
connect \B \wrpick_SPR_spr1_en_o
- connect \Y $1693
+ connect \Y $1582
end
- process $group_541
- assign \wr_pick$1692 1'0
- assign \wr_pick$1692 $1693
+ process $group_617
+ assign \wr_pick$1581 1'0
+ assign \wr_pick$1581 $1582
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1695
+ wire width 1 \wr_pick_dly$1584
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
- wire width 1 \wr_pick_dly$1695$next
- process $group_542
- assign \wr_pick_dly$1695$next \wr_pick_dly$1695
- assign \wr_pick_dly$1695$next \wr_pick$1692
+ wire width 1 \wr_pick_dly$1584$next
+ process $group_618
+ assign \wr_pick_dly$1584$next \wr_pick_dly$1584
+ assign \wr_pick_dly$1584$next \wr_pick$1581
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \coresync_rst
case 1'1
- assign \wr_pick_dly$1695$next 1'0
+ assign \wr_pick_dly$1584$next 1'0
end
sync init
- update \wr_pick_dly$1695 1'0
+ update \wr_pick_dly$1584 1'0
sync posedge \coresync_clk
- update \wr_pick_dly$1695 \wr_pick_dly$1695$next
+ update \wr_pick_dly$1584 \wr_pick_dly$1584$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1696
+ wire width 1 $1585
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $1697
+ cell $not $1586
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick_dly$1695
- connect \Y $1696
+ connect \A \wr_pick_dly$1584
+ connect \Y $1585
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- wire width 1 $1698
+ wire width 1 $1587
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $1699
+ cell $and $1588
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1692
- connect \B $1696
- connect \Y $1698
+ connect \A \wr_pick$1581
+ connect \B $1585
+ connect \Y $1587
end
- process $group_543
- assign \wr_pick_rise$963 1'0
- assign \wr_pick_rise$963 $1698
+ process $group_619
+ assign \wr_pick_rise$813 1'0
+ assign \wr_pick_rise$813 $1587
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 10 $1700
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- wire width 1 $1701
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $and $1702
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363"
+ wire width 1 \wp$1589
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ wire width 1 $1590
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364"
+ cell $and $1591
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr_pick$1692
+ connect \A \wr_pick$1581
connect \B \wrpick_SPR_spr1_en_o
- connect \Y $1701
+ connect \Y $1590
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:342"
- cell $mux $1703
+ process $group_620
+ assign \wp$1589 1'0
+ assign \wp$1589 $1590
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362"
+ wire width 10 \addr_en$1592
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ wire width 10 $1593
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365"
+ cell $mux $1594
parameter \WIDTH 10
connect \A 10'0000000000
connect \B \pdecode2_spro
- connect \S $1701
- connect \Y $1700
+ connect \S \wp$1589
+ connect \Y $1593
end
- process $group_544
- assign \write_en 10'0000000000
- assign \write_en $1700
+ process $group_621
+ assign \addr_en$1592 10'0000000000
+ assign \addr_en$1592 $1593
sync init
end
- process $group_545
- assign $memory_w_data 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $memory_w_data \fus_dest2_o$152
+ process $group_622
+ assign \spr_spr1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \spr_spr1__data_i \fus_dest2_o$152
sync init
end
- process $group_546
+ process $group_623
+ assign \spr_spr1__addr$158 7'0000000
+ assign \spr_spr1__addr$158 \addr_en$1592 [6:0]
+ sync init
+ end
+ process $group_624
+ assign \spr_spr1__wen 1'0
+ assign \spr_spr1__wen \wp$1589
+ sync init
+ end
+ process $group_625
assign \coresync_rst 1'0
assign \coresync_rst \core_reset_i
sync init
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \core_data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 32 \core_dmi__ren
+ wire width 1 \core_dmi__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \core_dmi__data_o
cell \core \core
end
sync init
end
- attribute \src "simple/issuer.py:228"
+ attribute \src "simple/issuer.py:229"
wire width 128 $45
- attribute \src "simple/issuer.py:228"
+ attribute \src "simple/issuer.py:229"
wire width 128 $46
- attribute \src "simple/issuer.py:228"
+ attribute \src "simple/issuer.py:229"
cell $sshl $47
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
connect $45 $46
process $group_35
- assign \core_dmi__ren 32'00000000000000000000000000000000
+ assign \core_dmi__ren 1'0
attribute \src "simple/issuer.py:225"
switch { \dbg_dbg_gpr_req }
attribute \src "simple/issuer.py:225"
case 1'1
- assign \core_dmi__ren $45 [31:0]
+ assign \core_dmi__ren $45 [0]
end
sync init
end
projects / soclayout.git / commitdiff