convert boot rom to bootmem and get first hello_world firmware loaded

diff --git a/Makefile b/Makefile
index a1328582b38640b0bca850541962c3c03cf109bf..c60893b1398beebf80874d011636694e522a68a5 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -26,16 +26,16 @@ endif
 
 # Hello world
 MEMORY_SIZE=8192
-RAM_INIT_FILE=hello_world/hello_world.hex
+RAM_INIT_FILE=hello_world/hello_world.bin
 SIM_MAIN_BRAM=false
 
 # Micropython
 #MEMORY_SIZE=393216
-#RAM_INIT_FILE=micropython/firmware.hex
+#RAM_INIT_FILE=micropython/firmware.bin
 
 # Linux
 #MEMORY_SIZE=536870912
-#RAM_INIT_FILE=dtbImage.microwatt.hex
+#RAM_INIT_FILE=dtbImage.microwatt.bin
 #SIM_MAIN_BRAM=false
 SIM_BRAM_CHAINBOOT=6291456 # 0x600000
 
@@ -49,7 +49,7 @@ clkgen=fpga/clk_gen_bypass.vhd
 endif
 
 ls2.v: src/ls2.py
-       python3 src/ls2.py sim
+       python3 src/ls2.py sim $(RAM_INIT_FILE)
 
 # Need to investigate why yosys is hitting verilator warnings,
 # and eventually turn on -Wall

diff --git a/src/ls2.py b/src/ls2.py
index 84724019ef39849faf518e86006f2911de347d16..b93e290a5d0f3ef7b7ee56eb988a08ac8644af05 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -71,12 +71,14 @@ class DDR3SoC(SoC, Elaboratable):
 
         # SRAM (but actually a ROM, for firmware), at address 0x0
         if fw_addr is not None:
-            self.rom = SRAMPeripheral(size=4096, writable=False)
+            sram_width = 32
+            self.bootmem = SRAMPeripheral(size=8192, data_width=sram_width,
+                                      writable=True)
             with open(firmware, "rb") as f:
-                words = iter(lambda: f.read(self.cpu.data_width // 8), b'')
-                bios  = [int.from_bytes(w, self.cpu.byteorder) for w in words]
-            self.rom.init = bios
-            self._decoder.add(self.rom.bus, addr=fw_addr) # ROM at fw_addr
+                words = iter(lambda: f.read(sram_width // 8), b'')
+                bios  = [int.from_bytes(w, "little") for w in words]
+            self.bootmem.init = bios
+            self._decoder.add(self.bootmem.bus, addr=fw_addr) # ROM at fw_addr
 
         # SRAM (read-writeable BRAM)
         self.ram = SRAMPeripheral(size=4096)
@@ -122,8 +124,8 @@ class DDR3SoC(SoC, Elaboratable):
         if platform is not None:
             m.submodules.sysclk = self.crg
 
-        if hasattr(self, "rom"):
-            m.submodules.rom = self.rom
+        if hasattr(self, "bootmem"):
+            m.submodules.bootmem = self.bootmem
         m.submodules.ram = self.ram
         m.submodules.uart = self.uart
         if False: