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diff --git a/src/soc/fu/alu/main_stage.py b/src/soc/fu/alu/main_stage.py
index b39d01999f3a15ef380912facc6d7e90b379d815..28c6b4d3c1edf14e22309c1dac49bac6e3d1bd05 100644 (file)
--- a/src/soc/fu/alu/main_stage.py
+++ b/src/soc/fu/alu/main_stage.py
@@ -16,14 +16,16 @@ class ALUMainStage(PipeModBase):
         super().__init__(pspec, "main")
 
     def ispec(self):
-        return ALUInputData(self.pspec)
+        return ALUInputData(self.pspec) # defines pipeline stage input format
 
     def ospec(self):
-        return ALUOutputData(self.pspec) # TODO: ALUIntermediateData
+        return ALUOutputData(self.pspec) # defines pipeline stage output format
 
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
+
+        # convenience variables
         cry_o, o, cr0 = self.o.xer_ca, self.o.o, self.o.cr0
         ov_o = self.o.xer_ov
         a, b, cry_i, op = self.i.a, self.i.b, self.i.xer_ca, self.i.ctx.op