dcache.py fix asserts, use backslash and two strings, one per line,

fixes rest of https://bugs.libre-soc.org/show_bug.cgi?id=469#c2

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index e11ba0d63b0be71f1ad0ef7776ff67644e9626c8..9d833c406804de36b59f8e9dcf082d3b052dce17 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1017,35 +1017,35 @@ class Dcache(Elaboratable):
 #     assert SET_SIZE_BITS <= TLB_LG_PGSZ
 #      report "Set indexed by virtual address" severity FAILURE;
         assert (LINE_SIZE % ROW_SIZE) == 0 "LINE_SIZE not " \
-                          "multiple of ROW_SIZE -!- severity FAILURE"
+         "multiple of ROW_SIZE -!- severity FAILURE"
 
         assert (LINE_SIZE % 2) == 0 "LINE_SIZE not power of" \
-                        "2 -!- severity FAILURE"
+         "2 -!- severity FAILURE"
 
-        assert (NUM_LINES % 2) == 0 "NUM_LINES not power of
-         2 -!- severity FAILURE"
+        assert (NUM_LINES % 2) == 0 "NUM_LINES not power of" \
+         "2 -!- severity FAILURE"
 
-        assert (ROW_PER_LINE % 2) == 0 "ROW_PER_LINE not
-         power of 2 -!- severity FAILURE"
+        assert (ROW_PER_LINE % 2) == 0 "ROW_PER_LINE not" \
+         "power of 2 -!- severity FAILURE"
 
-        assert ROW_BITS == (INDEX_BITS + ROW_LINE_BITS)
+        assert ROW_BITS == (INDEX_BITS + ROW_LINE_BITS) \
          "geometry bits don't add up -!- severity FAILURE"
 
-        assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
+        assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS) \
          "geometry bits don't add up -!- severity FAILURE"
 
-        assert REAL_ADDR_BITS == (TAG_BITS + INDEX_BITS
-         + LINE_OFF_BITS) "geometry bits don't add up -!-
-         severity FAILURE"
+        assert REAL_ADDR_BITS == (TAG_BITS + INDEX_BITS \
+         + LINE_OFF_BITS) "geometry bits don't add up -!-" \
+         "severity FAILURE"
 
-        assert REAL_ADDR_BITS == (TAG_BITS + ROW_BITS + ROW_OFF_BITS)
+        assert REAL_ADDR_BITS == (TAG_BITS + ROW_BITS + ROW_OFF_BITS) \
          "geometry bits don't add up -!- severity FAILURE"
 
-        assert 64 == wishbone_data_bits "Can't yet handle a
-         wishbone width that isn't 64-bits -!- severity FAILURE"
+        assert 64 == wishbone_data_bits "Can't yet handle a" \
+         "wishbone width that isn't 64-bits -!- severity FAILURE"
 
-        assert SET_SIZE_BITS <= TLB_LG_PGSZ "Set indexed by
-         virtual address -!- severity FAILURE"
+        assert SET_SIZE_BITS <= TLB_LG_PGSZ "Set indexed by" \
+         "virtual address -!- severity FAILURE"
 
 #     -- Latch the request in r0.req as long as we're not stalling
 #     stage_0 : process(clk)