system-arm: AArch64 boot, init CNTFRQ_EL0

CNTFRQ_EL0 should be initialised to a uniform value in all cores present
in the system. Previously, this was only done if EL3 was present,
however architecture states CNTFRQ_EL0 may be written from the highest
EL implemented.
This patch moves this initilization outside of the EL3-only one.

Change-Id: Ibaa197de53d531ba898e5137ba4f46a8c9554699
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24683
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/system/arm/bootloader/arm64/boot.S b/system/arm/bootloader/arm64/boot.S
index 38090c8f28d8ea81e5d97d4ca5fb72703f9c6996..fa7acdb5829195744506cba3ceef5030c7b6db1f 100644 (file)
--- a/system/arm/bootloader/arm64/boot.S
+++ b/system/arm/bootloader/arm64/boot.S
@@ -40,6 +40,8 @@
 
         .globl _start
 _start:
+        ldr    x0, =CNTFRQ
+        msr    cntfrq_el0, x0
         /*
          * EL3 initialisation
          */
@@ -55,9 +57,6 @@ _start:
 
         msr    cptr_el3, xzr                   // Disable copro. traps to EL3
 
-        ldr    x0, =CNTFRQ
-        msr    cntfrq_el0, x0
-
         /*
          * Check for the primary CPU to avoid a race on the distributor
          * registers.
@@ -180,10 +179,6 @@ start_ns:
         str    wzr, [x4, #0xa0]                // V2M_SYS_CFGDATA
         str    w5, [x4, #0xa4]                 // V2M_SYS_CFGCTRL
 
-        // set up the arch timer frequency
-        //ldr  x0, =CNTFRQ
-        //msr  cntfrq_el0, x0
-
         /*
          * Primary CPU
          */