projects / gem5.git / search
| 2020-01-27 | Adrian Herrera | system-arm: AArch64 boot, init CNTFRQ_EL0 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-23 | Adrian Herrera | dev-arm: SP805 peripherals in VExpress_GEM5_Base Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-22 | Adrian Herrera | dev-arm: add Watchdog Module SP805 model Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-22 | Adrian Herrera | dev-arm: VExpress_GEM5_Base, add refclock 32KHz Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-22 | Giacomo Travaglini | tests: Fix python line break in m5_exit test Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-21 | Giacomo Travaglini | tests: Add a timeout to getremotetime Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-21 | Adrian Herrera | dev-arm: add FixedClock SimObject Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-21 | Giacomo Travaglini | tests: Adding --bin-path option to select tests bin... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-21 | Giacomo Travaglini | tests: fs/linux/arm passing M5_PATH via commandline Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-17 | Timothy Hayes | configs: MESI_Three_level python parameters |
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| 2020-01-17 | Timothy Hayes | misc: add Arm build_opts for MESI_Three_Level and MOESI_hammer |
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| 2020-01-15 | Adrian Herrera | arch-arm: ELIsInHost, check VHE and SecEL2 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-15 | Adrian Herrera | arch-arm: Virtualization Host Extensions checking Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-14 | Adrian Herrera | system-arm: bigLITTLE with VExpress_GEM5_V2 in dtb Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-10 | Adrian Herrera | dev-arm: VExpress_GEM5_Base, fix daughterboard reference Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-09 | Giacomo Travaglini | base, gpu-compute: Move gpu AMOs into the generic header Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-08 | Giacomo Travaglini | arch, base: Move arm AtomicOpFunctor into the generic... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-08 | Giacomo Travaglini | base: Move AtomicOpFunctors to a dedicated header Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-07 | Gabor Dozsa | cpu: Disable O3CPU value forwarding with write strobes |
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| 2020-01-07 | Gabor Dozsa | cpu: Use enums for O3CPU store value forwarding |
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| 2020-01-07 | Giacomo Travaglini | system-arm: GICv2/GICv3 have different Distributor... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-07 | Giacomo Travaglini | system-arm: Rename ARM bootloader source Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-07 | Giacomo Travaglini | system-arm: Rename ARM bootloader directories Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-07 | Adrian Herrera | misc: Reflect changes of arm bootloader name |
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| 2020-01-06 | Adrian Herrera | arch-arm: Semihosting, specify files root dir Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-06 | Michiel van Tol | dev-arm: Fix SMMUv3 walkMasks in page table ops Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-06 | Giacomo Travaglini | dev-arm: Fix SMMUv3 16KB next-level table address masking Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-06 | Adrian Herrera | dev-arm: GICv3, handle GICR_ICFGR0 WI behaviour Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-06 | Adrian Herrera | configs-arm: enable PMU instantiation in CpuCluster Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-03 | Giacomo Gabrielli | cpu: Fix issue with MinorCPU predicated-false mem.... |
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| 2020-01-03 | Gabor Dozsa | cpu: Disable MinorCPU value forwarding with write strobes |
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| 2019-12-23 | Giacomo Travaglini | tests: Always print stderr in gem5 Fixtures Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-20 | Giacomo Travaglini | configs: arm realview(64) regressions using VExpress_GEM5_V1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-18 | Adrian Herrera | arch-arm: Semihosting, fix SYS_FLEN Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-18 | Adrian Herrera | sim: kernelExtras optional load addresses Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-18 | Adrian Herrera | python: fix "fatal" usage in fdthelper Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-18 | Adrian Herrera | arch-arm: Secure EL2 checking Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-18 | Adrian Herrera | arch-arm: AArch64 trap check, arbitrary ECs/Imms Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-16 | Adrian Herrera | sim: kernelExtras if no kernel provided Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-11 | Giacomo Travaglini | arch-arm: Always initialize SVE memData Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-11 | Giacomo Travaglini | arch-arm: Avoid creating an empty byteEnable vector Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-11 | Giacomo Travaglini | cpu: Replace empty byteEnable check with Request::isMasked Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-11 | Giacomo Travaglini | cpu: Fix coding style (byteEnable->byte_enable) Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-11 | Giacomo Travaglini | cpu: Add byteEnable assertions to readMem and initateMemRead Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-10 | Adrian Herrera | dev-arm: GenericTimer, configurable base and low freqs Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-10 | Adrian Herrera | dev-arm: GenericTimer, freq as 32-bit value Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-10 | Giacomo Travaglini | arch-arm: Disambuiguate NumFloatV7ArchRegs usage Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-10 | Giacomo Travaglini | arch-arm: Unify VLdmStm behaviour when reg out of index Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-10 | Giacomo Travaglini | arch-arm: Fix NumVecV7ArchRegs value (64->16) Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-10 | Giacomo Travaglini | arch-arm: Reorder arch/arm/registers.hh constants Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-10 | Giacomo Travaglini | arch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegs Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-09 | Giacomo Travaglini | tests: AArch64 Linux as quick regressions (instead... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-09 | Giacomo Travaglini | mem: Add Request::isMasked to check for byte strobing Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-09 | Giacomo Travaglini | mem: Add byteEnable copy to Request copy constructor Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-03 | Giacomo Travaglini | sim-se: Avoid function overloading for syscall implementation Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-28 | Adrian Herrera | dev-arm: device name in AmbaFake accesses Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-27 | Giacomo Travaglini | base, python: Allow dirname selection for the interpreter Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-27 | Giacomo Travaglini | configs: Add --redirects for syscall emulation Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-27 | Giacomo Travaglini | base: Fix DPRINTF_UNCONDITIONAL on gem5.fast |
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| 2019-11-27 | Giacomo Travaglini | configs: Add root redirect path in SE mode only when set Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-27 | Giacomo Travaglini | sim-se: Check Path redirection when mmapping Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-27 | Giacomo Travaglini | configs: Fix baremetal platform Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-26 | Giacomo Travaglini | arch-arm: Make the Tarmac parsed registers case insensitive Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-25 | Adrian Herrera | arch-arm: default MIDR for Armv8 ISA processors Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-25 | Giacomo Travaglini | dev-arm: Adjust off_chip ranges in VExpress_GEM5 platform Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-21 | Giacomo Travaglini | base: Remove tests making use of Big/LittleEndianOrder... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-18 | Adrian Herrera | arch-arm: R/W interface to AArch32 HCR2 misc reg Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-18 | Giacomo Travaglini | arch-arm: Fix short descriptors cacheability during... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-18 | Giacomo Travaglini | arch-arm: Fix long descriptors cacheability during... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-14 | Giacomo Travaglini | tests: Specify a non-default root folder for regressions Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-13 | Adrian Herrera | arch-arm: fix routeToHyp for AArch64 in faults Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-12 | Giacomo Travaglini | tests: Using super in arm_generic whenever possible Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-12 | Giacomo Travaglini | tests: Using super for calling superclass __init__ Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-12 | Giacomo Travaglini | tests: Remove Noncoherent cache from regressions Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-11 | Giacomo Travaglini | arch-arm: Fix TarmacParser handling of 64bit LD/ST Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-11 | Giacomo Travaglini | arch-arm: Provide SVE support to the TarmacTracer Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-11 | Giacomo Gabrielli | arch-arm: Provide SVE support to the TarmacParser Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-05 | Giacomo Travaglini | arch-arm: Annotate original address in CMOs Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-05 | Adrian Herrera | dev-arm: optional instantiation of GICv3 ITS Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-01 | Adrian Herrera | arch-arm: generic method for getting an ArmSystem Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-11-01 | Giacomo Travaglini | dev-arm: Add SMMUv3 to VExpress_GEM5_V* Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-10-31 | Giacomo Travaglini | configs: Add baremetal.py example script Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-10-30 | Giacomo Travaglini | base: Name segments after their index Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-10-22 | Giacomo Travaglini | configs: Clean setupBootLoader signature Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-10-22 | Giacomo Travaglini | configs: Do not assume bootmem is a System child Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-10-22 | Giacomo Travaglini | dev-arm, configs: Using _on_chip_memory for on chip... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-10-16 | Giacomo Travaglini | base: Using scoped string in DPRINTFNR Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-10-16 | Giacomo Travaglini | base: Fix gem5.fast compilation Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-10-15 | Giacomo Travaglini | dev-arm: Carve out a portion of VExpress_GEM5 for the... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-10-15 | Giacomo Travaglini | configs: Add simpleSystem helper to generate devices... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-10-10 | Giacomo Travaglini | arch-arm: Move generateDtb to ArmSystem Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-10-10 | Giacomo Travaglini | dev-arm, configs: Remove RealViewPBX platform Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-10-03 | Giacomo Travaglini | arch-arm: Annotate CM flag in AA64 CM Instructions Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-10-03 | Giacomo Travaglini | arch-arm: Set CM bit in DataAbort Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-10-02 | Giacomo Travaglini | sim: Mark System::getThreadContext method as const Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-10-02 | Marc Mari Barcelo | dev-arm: Improve fault message on SMMUv3 translation... Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-10-02 | Marc Mari Barcelo | dev-arm: Fix address used to update the SMMUv3 Walk... Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-10-02 | Giacomo Travaglini | arch-arm: Create helper for sending events (SEV) Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-09-19 | Giacomo Travaglini | dev-arm: Conditionally enable HDLcd when doing DTB... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-09-19 | Giacomo Travaglini | dev-arm: Add HDLcd DTB autogeneration Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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