a_enabled and b_enabled into signals

diff --git a/src/ieee754/part_mul_add/multiply.py b/src/ieee754/part_mul_add/multiply.py
index aa4fafb62617d74e36019f2e5e2d1f02355769af..bdbb28cc8d9ec04ab9b226dccb3a4d61934e222e 100644 (file)
--- a/src/ieee754/part_mul_add/multiply.py
+++ b/src/ieee754/part_mul_add/multiply.py
@@ -570,10 +570,14 @@ class Mul8_16_32_64(Elaboratable):
             byte_width = 8 // len(parts)
             bit_width = 8 * byte_width
             for i in range(len(parts)):
-                b_enabled = parts[i] & self.a[(i + 1) * bit_width - 1] \
+                ae = parts[i] & self.a[(i + 1) * bit_width - 1] \
                     & self._a_signed[i * byte_width]
-                a_enabled = parts[i] & self.b[(i + 1) * bit_width - 1] \
+                be = parts[i] & self.b[(i + 1) * bit_width - 1] \
                     & self._b_signed[i * byte_width]
+                a_enabled = Signal(name="a_enabled_%d" % i, reset_less=True)
+                b_enabled = Signal(name="b_enabled_%d" % i, reset_less=True)
+                m.d.comb += a_enabled.eq(ae)
+                m.d.comb += b_enabled.eq(be)
 
                 # for 8-bit values: form a * 0xFF00 by using -a * 0x100, the
                 # negation operation is split into a bitwise not and a +1.