Add test for prtyw pseudocode

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 4050fab35a311292fba8f522d34a36ae5d1773cd..10db874c344b29fef311b3d731c49fd0207f1f25 100644 (file)
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -230,6 +230,16 @@ class DecoderTestCase(FHDLTestCase):
             sim = self.run_tst_program(program, initial_regs)
             self.assertEqual(sim.gpr(3), SelectableInt(0xdf95fd81bc0, 64))
 
+    def test_prty(self):
+        lst = ["prtyw 2, 1"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xdeadbeeecaffc0de
+        with Program(lst) as program:
+            sim = self.run_tst_program(program, initial_regs)
+            self.assertEqual(sim.gpr(2), SelectableInt(0x100000001, 64))
+
+        
+
     def test_mtcrf(self):
         for i in range(4):
             # 0x76540000 gives expected (3+4) (2+4) (1+4) (0+4) for

diff --git a/src/soc/decoder/selectable_int.py b/src/soc/decoder/selectable_int.py
index a275de0724d0c6fed689d6ceaef2904cf99c01a6..ce7c2ebbb9dc585e25036ba2a62e9fd46fe01fae 100644 (file)
--- a/src/soc/decoder/selectable_int.py
+++ b/src/soc/decoder/selectable_int.py
@@ -216,6 +216,11 @@ class SelectableInt:
         assert b.bits == self.bits
         return SelectableInt(self.value ^ b.value, self.bits)
 
+    def __rxor__(self, b):
+        b = check_extsign(self, b)
+        assert b.bits == self.bits
+        return SelectableInt(self.value ^ b.value, self.bits)
+
     def __invert__(self):
         return SelectableInt(~self.value, self.bits)