add truth table for PassThroughHandshake

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index 82ad70629920e21445c850d06c6e26b085963e5c..a6a4bfed16cb3f3619c767aecf618092c96be760 100644 (file)
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -764,7 +764,7 @@ class SimpleHandshake(ControlBase):
 
         Inputs   Temporary  Output
         -------  ---------- -----
-        P P N N  PiV& ~NiV&  N P
+        P P N N  PiV& ~NiR&  N P
         i o i o  PoR  NoV    o o
         V R R V              V R
 
@@ -1017,6 +1017,35 @@ class PassThroughStage(StageCls):
 
 class PassThroughHandshake(ControlBase):
     """ A control block that delays by one clock cycle.
+
+        Inputs   Temporary          Output Data
+        -------  ------------------  ----- ----
+        P P N N  PiV& PiV| NiR| pvr   N P  (pvr)
+        i o i o  PoR  ~PoR ~NoV       o o
+        V R R V                       V R
+
+        -------   -    -    -   -     - -
+        0 0 0 0   0    1    1   0     1 1   reg
+        0 0 0 1   0    1    0   0     1 0   reg
+        0 0 1 0   0    1    1   0     1 1   reg
+        0 0 1 1   0    1    1   0     1 1   reg
+        -------   -    -    -   -     - -
+        0 1 0 0   0    0    1   0     0 1   reg
+        0 1 0 1   0    0    0   0     0 0   reg
+        0 1 1 0   0    0    1   0     0 1   reg
+        0 1 1 1   0    0    1   0     0 1   reg
+        -------   -    -    -   -     - -
+        1 0 0 0   0    1    1   1     1 1   process(in)
+        1 0 0 1   0    1    0   0     1 0   reg
+        1 0 1 0   0    1    1   1     1 1   process(in)
+        1 0 1 1   0    1    1   1     1 1   process(in)
+        -------   -    -    -   -     - -
+        1 1 0 0   1    1    1   1     1 1   process(in)
+        1 1 0 1   1    1    0   0     1 0   reg
+        1 1 1 0   1    1    1   1     1 1   process(in)
+        1 1 1 1   1    1    1   1     1 1   process(in)
+        -------   -    -    -   -     - -
+
     """
 
     def elaborate(self, platform):