adding mtspr tests

diff --git a/libreriscv b/libreriscv
index 3cde5558a3df42b4a08be86881b03dbbdf5ea3e2..1bfe6d5bd723b78bd694a1f0955f1982f453196d 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 3cde5558a3df42b4a08be86881b03dbbdf5ea3e2
+Subproject commit 1bfe6d5bd723b78bd694a1f0955f1982f453196d

diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py
index e517192cc9804999ed9ef25c7e0ef3806242bb20..d58dc61ee6c9bc815a3e81272989f3c6e68456bf 100644 (file)
--- a/src/soc/fu/compunits/test/test_alu_compunit.py
+++ b/src/soc/fu/compunits/test/test_alu_compunit.py
@@ -20,7 +20,7 @@ class ALUTestRunner(TestRunner):
         res = yield from get_cu_inputs(dec2, sim)
         return res
 
-    def check_cu_outputs(self, res, dec2, sim, code):
+    def check_cu_outputs(self, res, dec2, sim, alu, code):
         """naming (res) must conform to ALUFunctionUnit output regspec
         """
 
@@ -39,9 +39,9 @@ class ALUTestRunner(TestRunner):
 
         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
-        yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_sim_xer_ov(sim_o, sim, alu, dec2)
         yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
-        yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_sim_xer_so(sim_o, sim, alu, dec2)
 
         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
         ALUHelpers.check_xer_ov(self, res, sim_o, code)

diff --git a/src/soc/fu/compunits/test/test_branch_compunit.py b/src/soc/fu/compunits/test/test_branch_compunit.py
index 6c9d1f6db534be89632652847740c08d7bb0dbee..31e664c5a5bb13b001ea1150287853ebd8957c70 100644 (file)
--- a/src/soc/fu/compunits/test/test_branch_compunit.py
+++ b/src/soc/fu/compunits/test/test_branch_compunit.py
@@ -25,7 +25,7 @@ class BranchTestRunner(TestRunner):
         res = yield from get_cu_inputs(dec2, sim)
         return res
 
-    def check_cu_outputs(self, res, dec2, sim, code):
+    def check_cu_outputs(self, res, dec2, sim, alu, code):
         """naming (res) must conform to BranchFunctionUnit output regspec
         """
 

diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index b1ee7c6f2e579e563a5cf36c9b98a18c872ae454..8b21029fe2e4bab80058dbaeb195ec2b17fbcf1f 100644 (file)
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -9,7 +9,7 @@ from soc.decoder.power_enums import Function
 from soc.decoder.isa.all import ISA
 
 from soc.experiment.compalu_multi import find_ok # hack
-
+from soc.config.test.test_loadstore import TestMemPspec
 
 def set_cu_input(cu, idx, data):
     rdop = cu.get_in_name(idx)
@@ -169,11 +169,13 @@ class TestRunner(FHDLTestCase):
 
         if self.funit == Function.LDST:
             from soc.experiment.l0_cache import TstL0CacheBuffer
-            m.submodules.l0 = l0 = TstL0CacheBuffer(n_units=1, regwid=64,
-                                                    addrwid=3,
-                                                    ifacetype='test_bare_wb')
+            pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
+                                 addr_wid=48,
+                                 mask_wid=8,
+                                 reg_wid=64)
+            m.submodules.l0 = l0 = TstL0CacheBuffer(pspec, n_units=1)
             pi = l0.l0.dports[0]
-            m.submodules.cu = cu = self.fukls(pi, awid=3)
+            m.submodules.cu = cu = self.fukls(pi, idx=0, awid=3)
             m.d.comb += cu.ad.go.eq(cu.ad.rel) # link addr-go direct to rel
             m.d.comb += cu.st.go.eq(cu.st.rel) # link store-go direct to rel
         else:
@@ -284,7 +286,7 @@ class TestRunner(FHDLTestCase):
                         yield from dump_sim_memory(self, l0, sim, code)
 
                     yield from self.iodef.check_cu_outputs(res, pdecode2,
-                                                            sim, code)
+                                                            sim, cu.alu, code)
 
                     # sigh.  hard-coded.  test memory
                     if self.funit == Function.LDST:

diff --git a/src/soc/fu/compunits/test/test_cr_compunit.py b/src/soc/fu/compunits/test/test_cr_compunit.py
index 6271ab096add0193c0702c371561a3cc59f4ee12..9d05d3f72b05ef60b34c6e470872cd7dda8447d2 100644 (file)
--- a/src/soc/fu/compunits/test/test_cr_compunit.py
+++ b/src/soc/fu/compunits/test/test_cr_compunit.py
@@ -20,7 +20,7 @@ class CRTestRunner(TestRunner):
         res = yield from get_cu_inputs(dec2, sim)
         return res
 
-    def check_cu_outputs(self, res, dec2, sim, code):
+    def check_cu_outputs(self, res, dec2, sim, alu, code):
         """naming (res) must conform to CRFunctionUnit output regspec
         """
 

diff --git a/src/soc/fu/compunits/test/test_logical_compunit.py b/src/soc/fu/compunits/test/test_logical_compunit.py
index d7465e79fe277d58ce47c4f7187317adbc9df4cf..439901a53c081d848dc1b82b97b6e39b5aae44c2 100644 (file)
--- a/src/soc/fu/compunits/test/test_logical_compunit.py
+++ b/src/soc/fu/compunits/test/test_logical_compunit.py
@@ -19,7 +19,7 @@ class LogicalTestRunner(TestRunner):
         res = yield from get_cu_inputs(dec2, sim)
         return res
 
-    def check_cu_outputs(self, res, dec2, sim, code):
+    def check_cu_outputs(self, res, dec2, sim, alu, code):
         """naming (res) must conform to LogicalFunctionUnit output regspec
         """
 

diff --git a/src/soc/fu/compunits/test/test_shiftrot_compunit.py b/src/soc/fu/compunits/test/test_shiftrot_compunit.py
index af14910bd952ef747a05f582bced06f66d299cce..1b8bf770f99bfcdc96eb52d6f1cebb57fc328755 100644 (file)
--- a/src/soc/fu/compunits/test/test_shiftrot_compunit.py
+++ b/src/soc/fu/compunits/test/test_shiftrot_compunit.py
@@ -20,7 +20,7 @@ class ShiftRotTestRunner(TestRunner):
         res = yield from get_cu_inputs(dec2, sim)
         return res
 
-    def check_cu_outputs(self, res, dec2, sim, code):
+    def check_cu_outputs(self, res, dec2, sim, alu, code):
         """naming (res) must conform to ShiftRotFunctionUnit output regspec
         """
 

diff --git a/src/soc/fu/compunits/test/test_spr_compunit.py b/src/soc/fu/compunits/test/test_spr_compunit.py
index 23366c534f32c99e285505141acda9d42eb5ea6d..087fc5083130ce3acc12a5eeea1627c40767aaf6 100644 (file)
--- a/src/soc/fu/compunits/test/test_spr_compunit.py
+++ b/src/soc/fu/compunits/test/test_spr_compunit.py
@@ -20,7 +20,7 @@ class SPRTestRunner(TestRunner):
         res = yield from get_cu_inputs(dec2, sim)
         return res
 
-    def check_cu_outputs(self, res, dec2, sim, code):
+    def check_cu_outputs(self, res, dec2, sim, alu, code):
         """naming (res) must conform to SPRFunctionUnit output regspec
         """
 
@@ -37,19 +37,30 @@ class SPRTestRunner(TestRunner):
 
         sim_o = {}
 
+        yield from ALUHelpers.get_int_o(res, alu, dec2)
+        yield from ALUHelpers.get_fast_spr1(res, alu, dec2)
+        yield from ALUHelpers.get_slow_spr1(res, alu, dec2)
+        yield from ALUHelpers.get_xer_ov(res, alu, dec2)
+        yield from ALUHelpers.get_xer_ca(res, alu, dec2)
+        yield from ALUHelpers.get_xer_so(res, alu, dec2)
+
+        print ("output", res)
+
         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
-        yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
-        yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_sim_xer_so(sim_o, sim, alu, dec2)
+        yield from ALUHelpers.get_wr_sim_xer_ov(sim_o, sim, alu, dec2)
         yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
         yield from ALUHelpers.get_wr_fast_spr1(sim_o, sim, dec2)
         yield from ALUHelpers.get_wr_slow_spr1(sim_o, sim, dec2)
 
+        print ("sim output", sim_o)
+
         ALUHelpers.check_xer_ov(self, res, sim_o, code)
         ALUHelpers.check_xer_ca(self, res, sim_o, code)
+        ALUHelpers.check_xer_so(self, res, sim_o, code)
         ALUHelpers.check_int_o(self, res, sim_o, code)
         ALUHelpers.check_fast_spr1(self, res, sim_o, code)
         ALUHelpers.check_slow_spr1(self, res, sim_o, code)
-        ALUHelpers.check_xer_so(self, res, sim_o, code)
 
 
 if __name__ == "__main__":

diff --git a/src/soc/fu/compunits/test/test_trap_compunit.py b/src/soc/fu/compunits/test/test_trap_compunit.py
index 4f4b44d3d7eae28ce89ec81524736cbce37c5de5..86ea94784591453603bfefe9b68f9efe820b5680 100644 (file)
--- a/src/soc/fu/compunits/test/test_trap_compunit.py
+++ b/src/soc/fu/compunits/test/test_trap_compunit.py
@@ -20,7 +20,7 @@ class TrapTestRunner(TestRunner):
         res = yield from get_cu_inputs(dec2, sim)
         return res
 
-    def check_cu_outputs(self, res, dec2, sim, code):
+    def check_cu_outputs(self, res, dec2, sim, alu, code):
         """naming (res) must conform to TrapFunctionUnit output regspec
         """
 

diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py
index ebe5d884fcabf9a4b748c764e82199ec980aad02..be147ca7a7a0db4eb262270d7fc8f5cf084b5eb2 100644 (file)
--- a/src/soc/fu/spr/test/test_pipe_caller.py
+++ b/src/soc/fu/spr/test/test_pipe_caller.py
@@ -85,9 +85,23 @@ class SPRTestCase(FHDLTestCase):
     def test_1_mfspr(self):
         lst = ["mfspr 1, 26", # SRR0
                "mfspr 2, 27",  # SRR1
-               "mfspr 2, 8",] # LR
+               "mfspr 3, 8",  # LR
+               "mfspr 4, 1",] # XER
         initial_regs = [0] * 32
-        initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234}
+        initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
+                        'XER': 0xe00c0000}
+        self.run_tst_program(Program(lst), initial_regs, initial_sprs)
+
+    def test_1_mtspr(self):
+        lst = ["mtspr 26, 1", # SRR0
+               "mtspr 27, 2", # and into reg 2
+               "mtspr 1, 3",] # XER
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x129518230011feed
+        initial_regs[2] = 0x129518230011feed
+        initial_regs[3] = 0xe00c0000
+        initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
+                        'XER': 0x0}
         self.run_tst_program(Program(lst), initial_regs, initial_sprs)
 
     def test_ilang(self):
@@ -206,18 +220,20 @@ class TestRunner(FHDLTestCase):
         print ("output", res)
 
         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
-        yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
-        yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_sim_xer_so(sim_o, sim, alu, dec2)
+        yield from ALUHelpers.get_wr_sim_xer_ov(sim_o, sim, alu, dec2)
         yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
         yield from ALUHelpers.get_wr_fast_spr1(sim_o, sim, dec2)
         yield from ALUHelpers.get_wr_slow_spr1(sim_o, sim, dec2)
 
+        print ("sim output", sim_o)
+
         ALUHelpers.check_xer_ov(self, res, sim_o, code)
         ALUHelpers.check_xer_ca(self, res, sim_o, code)
+        ALUHelpers.check_xer_so(self, res, sim_o, code)
         ALUHelpers.check_int_o(self, res, sim_o, code)
         ALUHelpers.check_fast_spr1(self, res, sim_o, code)
         ALUHelpers.check_slow_spr1(self, res, sim_o, code)
-        ALUHelpers.check_xer_so(self, res, sim_o, code)
 
 
 if __name__ == "__main__":

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index 0b8dd58f63453feb417a9ba378005f90ff550db2..b07b3885899e82fabc1c275df511fab8d2d6f036 100644 (file)
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -233,6 +233,8 @@ class ALUHelpers:
         oe = yield dec2.e.do.oe.oe
         oe_ok = yield dec2.e.do.oe.ok
         xer_out = yield dec2.e.xer_out
+        if not (yield alu.n.data_o.xer_so.ok):
+            return
         if xer_out or (oe and oe_ok):
             res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
 
@@ -240,12 +242,16 @@ class ALUHelpers:
         oe = yield dec2.e.do.oe.oe
         oe_ok = yield dec2.e.do.oe.ok
         xer_out = yield dec2.e.xer_out
+        if not (yield alu.n.data_o.xer_ov.ok):
+            return
         if xer_out or (oe and oe_ok):
             res['xer_ov'] = yield alu.n.data_o.xer_ov.data
 
     def get_xer_ca(res, alu, dec2):
         cry_out = yield dec2.e.do.output_carry
         xer_out = yield dec2.e.xer_out
+        if not (yield alu.n.data_o.xer_ca.ok):
+            return
         if xer_out or (cry_out):
             res['xer_ca'] = yield alu.n.data_o.xer_ca.data
 
@@ -291,12 +297,36 @@ class ALUHelpers:
             res['spr1'] = sim.spr[spr_name].value
 
     def get_wr_sim_xer_ca(res, sim, dec2):
+        #if not (yield alu.n.data_o.xer_ca.ok):
+        #    return
         cry_out = yield dec2.e.do.output_carry
-        if cry_out:
+        xer_out = yield dec2.e.xer_out
+        if cry_out or xer_out:
             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 
+    def get_wr_sim_xer_ov(res, sim, alu, dec2):
+        oe = yield dec2.e.do.oe.oe
+        oe_ok = yield dec2.e.do.oe.ok
+        xer_out = yield dec2.e.xer_out
+        print ("get_wr_sim_xer_ov", xer_out)
+        if not (yield alu.n.data_o.xer_ov.ok):
+            return
+        if xer_out or (oe and oe_ok):
+            expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
+            expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
+            res['xer_ov'] = expected_ov | (expected_ov32 << 1)
+
+    def get_wr_sim_xer_so(res, sim, alu, dec2):
+        oe = yield dec2.e.do.oe.oe
+        oe_ok = yield dec2.e.do.oe.ok
+        xer_out = yield dec2.e.xer_out
+        if not (yield alu.n.data_o.xer_so.ok):
+            return
+        if xer_out or (oe and oe_ok):
+            res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
+
     def get_sim_xer_ov(res, sim, dec2):
         oe = yield dec2.e.do.oe.oe
         oe_ok = yield dec2.e.do.oe.ok

diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py
index b53f935fea475e9d1167102d060b7f2feaae076b..25514730c75c5cba8fafa48aa76a38ddbccd9d0f 100644 (file)
--- a/src/soc/fu/trap/test/test_pipe_caller.py
+++ b/src/soc/fu/trap/test/test_pipe_caller.py
@@ -113,7 +113,7 @@ class TrapTestCase(FHDLTestCase):
         initial_regs[1] = 0xffffffffffffffff
         self.run_tst_program(Program(lst), initial_regs)
 
-    def test_2_mtmsr_1(self):
+    def test_3_mtmsr_1(self):
         lst = ["mtmsr 1,1"]
         initial_regs = [0] * 32
         initial_regs[1] = 0xffffffffffffffff