r0 zero tests on addis, fails

diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index 2c730221f27e4ec203a1f7febe518a75ee3f7916..c8d23a350269ba237c587ad44e61d02984613992 100644 (file)
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -99,6 +99,15 @@ class ALUTestCase(TestAccumulatorBase):
             initial_regs[2] = random.randint(0, (1 << 64)-1)
             self.add_case(Program(lst, bigendian), initial_regs)
 
+    def case_addis_nonzero_r0(self):
+        for i in range(10):
+            imm = random.randint(-(1 << 15), (1 << 15)-1)
+            lst = [f"addis 3, 0, {imm}"]
+            print(lst)
+            initial_regs = [0] * 32
+            initial_regs[0] = random.randint(0, (1 << 64)-1)
+            self.add_case(Program(lst, bigendian), initial_regs)
+
     def case_rand_imm(self):
         insns = ["addi", "addis", "subfic"]
         for i in range(10):

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index b44d059f064258c9d4aa557a5ea839acc1cfd208..ba7b8643827e5fd0cd15b533ed2a7846fa109a3a 100644 (file)
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -330,6 +330,18 @@ class GeneralTestCases(FHDLTestCase):
         with Program(lst, bigendian) as program:
             self.run_tst_program(program, [12])
 
+    #@unittest.skip("disable")
+    def test_31_addis(self):
+        """tests for zero not in register zero
+        """
+        lst = [  "rldicr  0, 0,32,31",
+                 "oris    0, 0,32767",
+                 "ori     0, 0,65535",
+                "addis 1, 0, 1",
+        ]
+        with Program(lst, bigendian) as program:
+            self.run_tst_program(program, [0, 1])
+
     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
                         initial_mem=None):
         initial_regs = [0] * 32