argh - bad hack, detecting when there are no registers to write, in MultiCompUnit

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index baebed0974d86b6af81df45cbdbec14a9db68bb9..4c1f019170159f6b5d57d40f0a06c67cf3e5375d 100644 (file)
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -204,6 +204,12 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         m.d.comb += wr_any.eq(self.wr.go.bool())
         m.d.comb += req_done.eq(wr_any & ~self.alu.n.ready_i & \
                 ((req_l.q & self.wrmask) == 0))
+        # argh, complicated hack: if there are no regs to write,
+        # instead of waiting for regs that are never going to happen,
+        # we indicate "done" when the ALU is "done"
+        with m.If((self.wrmask == 0) & \
+                    self.alu.n.ready_i & self.alu.n.valid_o & self.busy_o):
+            m.d.comb += req_done.eq(1)
 
         # shadow/go_die
         reset = Signal(reset_less=True)

diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 2c4b43e08b3f5006bc2c6778ef9e05a358cf7270..eb419abd7642089f880488999a2acad9c18bdc85 100644 (file)
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -169,6 +169,10 @@ class TestRunner(FHDLTestCase):
                     wr_rel_o = yield cu.wr.rel
                     print ("before inputs, rd_rel, wr_rel: ",
                             bin(rd_rel_o), bin(wr_rel_o))
+                    assert wr_rel_o == 0, "wr.rel %s must be zero. "\
+                                "previous instr not written all regs\n"\
+                                "respec %s" % \
+                                (bin(wr_rel_o), cu.rwid[1])
                     yield from set_cu_inputs(cu, inp)
                     yield
                     rd_rel_o = yield cu.rd.rel
@@ -182,6 +186,7 @@ class TestRunner(FHDLTestCase):
                     yield from sim.call(opname)
                     index = sim.pc.CIA.value//4
 
+                    yield Settle()
                     # get all outputs (one by one, just "because")
                     res = yield from get_cu_outputs(cu, code)