connect up boundary scan to inputs/outputs

diff --git a/experiments10_verilog/add.py b/experiments10_verilog/add.py
index 7cbabb9d01f1c35d994caa8c81792d2e36c850c8..09799d3c1d3622afa4b9a1d671f6c09aee748e5b 100644 (file)
--- a/experiments10_verilog/add.py
+++ b/experiments10_verilog/add.py
@@ -5,15 +5,16 @@ from nmigen import Elaboratable, Signal, Module, Const, DomainRenamer
 from nmigen.cli import verilog
 
 # to get c4m-jtag
-# clone with $ git clone gitolite3@git.libre-soc.org:c4m-jtag.git
-#            $ git clone gitolite3@git.libre-soc.org:nmigen-soc.git
-# for each:  $ python3 setup.py develop --user
+# clone with $ git clone gitolite3@git.libre-soc.org:nmigen-soc.git
+#            $ git clone gitolite3@git.libre-soc.org:c4m-jtag.git
+# for each:  $ python3 setup.py develop # optional: --user
 
 from c4m.nmigen.jtag.tap import TAP, IOType
 
 
 class ADD(Elaboratable):
     def __init__(self, width):
+        self.width = width
         self.a      = Signal(width)
         self.b      = Signal(width)
         self.f      = Signal(width)
@@ -28,8 +29,19 @@ class ADD(Elaboratable):
         # have to create at least one shift register
         self.sr = self.jtag.add_shiftreg(ircode=4, length=3)
 
-        # sigh and one iotype
-        self.ios = self.jtag.add_io(name="test", iotype=IOType.In)
+        # add iotypes
+        self.io_a_0 = self.jtag.add_io(name="a_0", iotype=IOType.In)
+        self.io_a_1 = self.jtag.add_io(name="a_1", iotype=IOType.In)
+        self.io_a_2 = self.jtag.add_io(name="a_2", iotype=IOType.In)
+        self.io_a_3 = self.jtag.add_io(name="a_3", iotype=IOType.In)
+        self.io_b_0 = self.jtag.add_io(name="b_0", iotype=IOType.In)
+        self.io_b_1 = self.jtag.add_io(name="b_1", iotype=IOType.In)
+        self.io_b_2 = self.jtag.add_io(name="b_2", iotype=IOType.In)
+        self.io_b_3 = self.jtag.add_io(name="b_3", iotype=IOType.In)
+        self.io_f_0 = self.jtag.add_io(name="f_0", iotype=IOType.Out)
+        self.io_f_1 = self.jtag.add_io(name="f_1", iotype=IOType.Out)
+        self.io_f_2 = self.jtag.add_io(name="f_2", iotype=IOType.Out)
+        self.io_f_3 = self.jtag.add_io(name="f_3", iotype=IOType.Out)
 
     def elaborate(self, platform):
         m = Module()
@@ -37,9 +49,42 @@ class ADD(Elaboratable):
         m.submodules.jtag = jtag = self.jtag
         m.d.comb += self.sr.i.eq(self.sr.o) # loopback test
 
+        # connect inputs/outputs to pads
+        m.d.comb += self.io_a_0.pad.i.eq(self.a[0])
+        m.d.comb += self.io_a_1.pad.i.eq(self.a[1])
+        m.d.comb += self.io_a_2.pad.i.eq(self.a[2])
+        m.d.comb += self.io_a_3.pad.i.eq(self.a[3])
+        m.d.comb += self.io_b_0.pad.i.eq(self.b[0])
+        m.d.comb += self.io_b_1.pad.i.eq(self.b[1])
+        m.d.comb += self.io_b_2.pad.i.eq(self.b[2])
+        m.d.comb += self.io_b_3.pad.i.eq(self.b[3])
+        m.d.comb += self.f[0].eq(self.io_f_0.pad.o)
+        m.d.comb += self.f[1].eq(self.io_f_1.pad.o)
+        m.d.comb += self.f[2].eq(self.io_f_2.pad.o)
+        m.d.comb += self.f[3].eq(self.io_f_3.pad.o)
+
+        # internal signals (not external pads basically)
+        a      = Signal(self.width)
+        b      = Signal(self.width)
+        f      = Signal(self.width)
+
+        # and now the internal signals to the core
+        m.d.comb += a[0].eq(self.io_a_0.core.i)
+        m.d.comb += a[1].eq(self.io_a_1.core.i)
+        m.d.comb += a[2].eq(self.io_a_2.core.i)
+        m.d.comb += a[3].eq(self.io_a_3.core.i)
+        m.d.comb += b[0].eq(self.io_b_0.core.i)
+        m.d.comb += b[1].eq(self.io_b_1.core.i)
+        m.d.comb += b[2].eq(self.io_b_2.core.i)
+        m.d.comb += b[3].eq(self.io_b_3.core.i)
+        m.d.comb += self.io_f_0.core.o.eq(f[0])
+        m.d.comb += self.io_f_1.core.o.eq(f[1])
+        m.d.comb += self.io_f_2.core.o.eq(f[2])
+        m.d.comb += self.io_f_3.core.o.eq(f[3])
+
+
         # do a simple "add"
-        m.d.sync += self.f.eq(self.a + self.b)
-        m.d.sync += self.f[0].eq(Const(0, 1))
+        m.d.sync += f.eq(a + b)
 
         return m