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tidyup
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 18 Dec 2021 01:22:06 +0000 (01:22 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 18 Dec 2021 01:22:06 +0000 (01:22 +0000)
src/soc/experiment/icache.py patch | blob | history

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 3a80e430ba4a17481959ba521d3989a885c01179..2e5b33f3ef18b9457a484006a2e376b0690bca05 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -266,11 +266,9 @@ def write_tag(way, tagset, tag):
 
 # Simple hash for direct-mapped TLB index
 def hash_ea(addr):
-    hsh = addr[TLB_LG_PGSZ:TLB_LG_PGSZ + TLB_BITS] ^ addr[
-           TLB_LG_PGSZ + TLB_BITS:TLB_LG_PGSZ + 2 * TLB_BITS
-          ] ^ addr[
-           TLB_LG_PGSZ + 2 * TLB_BITS:TLB_LG_PGSZ + 3 * TLB_BITS
-          ]
+    hsh = (addr[TLB_LG_PGSZ:TLB_LG_PGSZ + TLB_BITS] ^
+           addr[TLB_LG_PGSZ + TLB_BITS:TLB_LG_PGSZ + 2 * TLB_BITS ] ^
+           addr[TLB_LG_PGSZ + 2 * TLB_BITS:TLB_LG_PGSZ + 3 * TLB_BITS])
     return hsh