rename ibus/dbus (shorten)

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 2a9f3b5a52d7c1c4c58ffc7bdf79db8c2ba994cb..49e4bd3a022a0b90ad11980896e070700729332e 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -44,10 +44,10 @@ class LibreSoC(CPU):
         self.variant      = variant
         self.reset        = Signal()
 
-        self.ibus         = wishbone.Interface(data_width=64, adr_width=29)
-        self.dbus         = wishbone.Interface(data_width=64, adr_width=29)
+        self.ibus = ibus = wishbone.Interface(data_width=64, adr_width=29)
+        self.dbus = dbus = wishbone.Interface(data_width=64, adr_width=29)
 
-        self.periph_buses = [self.ibus, self.dbus]
+        self.periph_buses = [ibus, dbus]
         self.memory_buses = []
 
         self.dmi_addr = Signal(3)
@@ -65,30 +65,30 @@ class LibreSoC(CPU):
             i_rst              = ResetSignal() | self.reset,
 
             # IBus
-            o_ibus__stb        = self.ibus.stb,
-            o_ibus__cyc        = self.ibus.cyc,
-            o_ibus__cti        = self.ibus.cti,
-            o_ibus__bte        = self.ibus.bte,
-            o_ibus__we         = self.ibus.we,
-            o_ibus__adr        = Cat(self.ibus.adr), # bytes to words addressing
-            o_ibus__dat_w      = self.ibus.dat_w,
-            o_ibus__sel        = self.ibus.sel,
-            i_ibus__ack        = self.ibus.ack,
-            i_ibus__err        = self.ibus.err,
-            i_ibus__dat_r      = self.ibus.dat_r,
+            o_ibus__stb        = ibus.stb,
+            o_ibus__cyc        = ibus.cyc,
+            o_ibus__cti        = ibus.cti,
+            o_ibus__bte        = ibus.bte,
+            o_ibus__we         = ibus.we,
+            o_ibus__adr        = Cat(ibus.adr), # bytes to words addressing
+            o_ibus__dat_w      = ibus.dat_w,
+            o_ibus__sel        = ibus.sel,
+            i_ibus__ack        = ibus.ack,
+            i_ibus__err        = ibus.err,
+            i_ibus__dat_r      = ibus.dat_r,
 
             # DBus
-            o_dbus__stb        = self.dbus.stb,
-            o_dbus__cyc        = self.dbus.cyc,
-            o_dbus__cti        = self.dbus.cti,
-            o_dbus__bte        = self.dbus.bte,
-            o_dbus__we         = self.dbus.we,
-            o_dbus__adr        = Cat(self.dbus.adr), # bytes to words addressing
-            o_dbus__dat_w      = self.dbus.dat_w,
-            o_dbus__sel        = self.dbus.sel,
-            i_dbus__ack        = self.dbus.ack,
-            i_dbus__err        = self.dbus.err,
-            i_dbus__dat_r      = self.dbus.dat_r,
+            o_dbus__stb        = dbus.stb,
+            o_dbus__cyc        = dbus.cyc,
+            o_dbus__cti        = dbus.cti,
+            o_dbus__bte        = dbus.bte,
+            o_dbus__we         = dbus.we,
+            o_dbus__adr        = Cat(dbus.adr), # bytes to words addressing
+            o_dbus__dat_w      = dbus.dat_w,
+            o_dbus__sel        = dbus.sel,
+            i_dbus__ack        = dbus.ack,
+            i_dbus__err        = dbus.err,
+            i_dbus__dat_r      = dbus.dat_r,
 
             # Monitoring / Debugging
             i_pc_i             = 0,