# also contains Staf's manually re-connected PLL edits to the verilog
# see commits 24cbbcc and 227a0f69
#
+# Include tweaks dedicated to jpc's slightly different build environment.
+
echo "remember to check doDesign core size"
echo "also use yosys 049e3abf9"
+if [ "${USER}" = "jpc" ]; then echo "Using \"jpc\" configuration."; fi
# initialise/update the pinmux submodule
-git submodule update --init --remote
+if [ "${USER}" = "jpc" ]; then
+ # Must be done in the root of the repository when cloning anew.
+ (cd ../..; git submodule update --init --remote)
+else
+ git submodule update --init --remote
+fi
# makes symlinks to alliance
-./mksyms.sh
+if [ ! -e "./mk" ]; then
+ if [ "${USER}" = "jpc" ]; then
+ ln -s ../../../../alliance-check-toolkit/etc/mk .
+ else
+ ./mksyms.sh
+ fi
+fi
# generates the io pads needed for ioring.py
make pinmux
# clear out
make clean
-rm *.vst *.ap
+rm -f *.vst *.ap
# copies over a "full" core
#cp non_generated/full_core_4_4ksram_ls180.il ls180.il
touch mem_4.init
touch mem_5.init
-# make the vst from verilog
-make vst
-
-# starts the build.
-make layout
+if [ "${USER}" != "jpc" ]; then
+ # make the vst from verilog
+ make vst
+ # starts the build.
+ make layout
+fi