add debugging chain for #425

diff --git a/src/soc/fu/div/pipeline.py b/src/soc/fu/div/pipeline.py
index d72083e52c872aec63997765c0cf813c9973e018..801cd44a995a8183398ff7f5d19ae278c45b3a5e 100644 (file)
--- a/src/soc/fu/div/pipeline.py
+++ b/src/soc/fu/div/pipeline.py
@@ -34,6 +34,7 @@ class DivStagesEnd(PipeModBaseChain):
         core_final = DivCoreFinalStage(self.pspec)
         div_out = DivOutputStage(self.pspec)
         alu_out = DivMulOutputStage(self.pspec)
+        self.div_out = div_out # debugging - bug #425
         return [core_final, div_out, alu_out]
 
 

diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index 6b80fcc1fc300e5508f32e2222143f677f14fb98..403c0b57e642311446511dcf8501ecf56ef81c40 100644 (file)
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -217,6 +217,7 @@ class TestRunner(FHDLTestCase):
                     while not vld:
                         yield
                         vld = yield alu.n.valid_o
+                        print ("bug track", alu.pipe_end.div_out)
                     yield
 
                     yield from self.check_alu_outputs(alu, pdecode2, sim, code)