add mul pipeline based on add

diff --git a/src/ieee754/fpmul/mulstages.py b/src/ieee754/fpmul/mulstages.py
new file mode 100644 (file)
index 0000000..adf68d3
--- /dev/null
+++ b/src/ieee754/fpmul/mulstages.py
@@ -0,0 +1,50 @@
+# IEEE Floating Point Multiplier
+
+from nmigen import Module
+from nmigen.cli import main, verilog
+
+from nmutil.singlepipe import (StageChain, SimpleHandshake)
+
+from ieee754.fpcommon.fpbase import FPState
+from ieee754.fpcommon.denorm import FPSCData
+from ieee754.fpcommon.postcalc import FPAddStage1Data
+from .mul0 import FPMulStage0Mod
+from .mul1 import FPMulStage1Mod
+
+
+class FPMulStages(FPState, SimpleHandshake):
+
+    def __init__(self, width, id_wid):
+        FPState.__init__(self, "align")
+        self.width = width
+        self.id_wid = id_wid
+        SimpleHandshake.__init__(self, self) # pipeline is its own stage
+        self.m1o = self.ospec()
+
+    def ispec(self):
+        return FPSCData(self.width, self.id_wid)
+
+    def ospec(self):
+        return FPAddStage1Data(self.width, self.id_wid) # AddStage1 ospec
+
+    def setup(self, m, i):
+        """ links module to inputs and outputs
+        """
+
+        # chain MulStage0 and MulStage1
+        m0mod = FPMulStage0Mod(self.width, self.id_wid)
+        m1mod = FPMulStage1Mod(self.width, self.id_wid)
+
+        chain = StageChain([m0mod, m1mod])
+        chain.setup(m, i)
+
+        self.o = m1mod.o
+
+    def process(self, i):
+        return self.o
+
+    def action(self, m):
+        m.d.sync += self.m1o.eq(self.process(None))
+        m.next = "normalise_1"
+
+

diff --git a/src/ieee754/fpmul/pipeline.py b/src/ieee754/fpmul/pipeline.py
new file mode 100644 (file)
index 0000000..0f49a37
--- /dev/null
+++ b/src/ieee754/fpmul/pipeline.py
@@ -0,0 +1,59 @@
+# IEEE Floating Point Adder (Single Precision)
+# Copyright (C) Jonathan P Dawson 2013
+# 2013-12-12
+
+from nmigen import Module
+from nmigen.cli import main, verilog
+
+from nmutil.singlepipe import (ControlBase, SimpleHandshake, PassThroughStage)
+from nmutil.multipipe import CombMuxOutPipe
+from nmutil.multipipe import PriorityCombMuxInPipe
+from nmutil.concurrentunit import ReservationStations, num_bits
+
+from ieee754.fpcommon.getop import FPADDBaseData
+from ieee754.fpcommon.denorm import FPSCData
+from ieee754.fpcommon.pack import FPPackData
+from ieee754.fpcommon.normtopack import FPNormToPack
+from .specialcases import FPMulSpecialCasesDeNorm
+from .addstages import FPMulStages
+
+
+
+class FPMULBasePipe(ControlBase):
+    def __init__(self, width, id_wid):
+        ControlBase.__init__(self)
+        self.pipe1 = FPMulSpecialCasesDeNorm(width, id_wid)
+        self.pipe2 = FPMulStages(width, id_wid)
+        self.pipe3 = FPNormToPack(width, id_wid)
+
+        self._eqs = self.connect([self.pipe1, self.pipe2, self.pipe3])
+
+    def elaborate(self, platform):
+        m = ControlBase.elaborate(self, platform)
+        m.submodules.scnorm = self.pipe1
+        m.submodules.mulstages = self.pipe2
+        m.submodules.normpack = self.pipe3
+        m.d.comb += self._eqs
+        return m
+
+
+class FPMULMuxInOut(ReservationStations):
+    """ Reservation-Station version of FPMUL pipeline.
+
+        * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
+        * 3-stage adder pipeline
+        * fan-out on outputs (an array of FPPackData: z,mid)
+
+        Fan-in and Fan-out are combinatorial.
+    """
+    def __init__(self, width, num_rows):
+        self.width = width
+        self.id_wid = num_bits(width)
+        self.alu = FPMULBasePipe(width, self.id_wid)
+        ReservationStations.__init__(self, num_rows)
+
+    def i_specfn(self):
+        return FPADDBaseData(self.width, self.id_wid)
+
+    def o_specfn(self):
+        return FPPackData(self.width, self.id_wid)