add copyright / bugreport notice

diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index e8920833ce2d60327500d565a2b57d8032e201ff..7a39d72759bb24521788294533bb6006f0d0b67d 100644 (file)
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -3,7 +3,11 @@
 Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 Copyright (C) 2019 Jacob Lifshay
 
-Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
+Relevant bugreports:
+* http://bugs.libre-riscv.org/show_bug.cgi?id=99
+* http://bugs.libre-riscv.org/show_bug.cgi?id=43
+* http://bugs.libre-riscv.org/show_bug.cgi?id=44
+
 """
 
 from nmigen import Module, Signal, Cat, Elaboratable, Const, Mux

diff --git a/src/ieee754/fpdiv/div2.py b/src/ieee754/fpdiv/div2.py
index 9e90155f49c2172e7d48a0328830bc248d52a165..5a26ace733309544088db31d40ba56dbff3e01c7 100644 (file)
--- a/src/ieee754/fpdiv/div2.py
+++ b/src/ieee754/fpdiv/div2.py
@@ -3,7 +3,10 @@
 Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 Copyright (C) 2019 Jacob Lifshay
 
-Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
+Relevant bugreports:
+* http://bugs.libre-riscv.org/show_bug.cgi?id=99
+* http://bugs.libre-riscv.org/show_bug.cgi?id=43
+* http://bugs.libre-riscv.org/show_bug.cgi?id=44
 """
 
 from nmigen import Module, Signal, Elaboratable, Cat

diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index 499bd79c4373ce7ecfe2ada31f12fd39c58f4830..c73d38148eb62bbd04f62359607e6106dc270e0d 100644 (file)
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -1,6 +1,12 @@
-"""IEEE Floating Point Divider Pipeline
+"""IEEE754 Floating Point Divider Pipeline
 
-Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
+Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Copyright (C) 2019 Jacob Lifshay
+
+Relevant bugreports:
+* http://bugs.libre-riscv.org/show_bug.cgi?id=99
+* http://bugs.libre-riscv.org/show_bug.cgi?id=43
+* http://bugs.libre-riscv.org/show_bug.cgi?id=44
 
 Stack looks like this:
 

diff --git a/src/ieee754/fpdiv/specialcases.py b/src/ieee754/fpdiv/specialcases.py
index 75721de27ee9508e06e8b57ea30ef82d3c1673ba..e0c9b07843aafb2dc1bbd778341d3dce91ae4c11 100644 (file)
--- a/src/ieee754/fpdiv/specialcases.py
+++ b/src/ieee754/fpdiv/specialcases.py
@@ -1,4 +1,13 @@
-# IEEE Floating Point Multiplier
+""" IEEE Floating Point Divider
+
+Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Copyright (C) 2019 Jacob Lifshay
+
+Relevant bugreports:
+* http://bugs.libre-riscv.org/show_bug.cgi?id=99
+* http://bugs.libre-riscv.org/show_bug.cgi?id=43
+* http://bugs.libre-riscv.org/show_bug.cgi?id=44
+"""
 
 from nmigen import Module, Signal, Cat, Const, Elaboratable
 from nmigen.cli import main, verilog
@@ -65,6 +74,7 @@ class FPDIVSpecialCasesMod(Elaboratable):
         m.d.comb += abinf.eq(a1.is_inf & b1.is_inf)
 
         with m.If(self.i.ctx.op == 0):  # DIV
+
             # if a is NaN or b is NaN return NaN
             with m.If(abnan):
                 m.d.comb += self.o.out_do_z.eq(1)