add test, temporary comb variable to stage2

diff --git a/src/add/pipeline_example.py b/src/add/pipeline_example.py
index 544b745b0a5d7b710b7d9eea38397acab5f4799a..590e1db65465db985aeedd7f6337811b8e32c547 100644 (file)
--- a/src/add/pipeline_example.py
+++ b/src/add/pipeline_example.py
@@ -22,7 +22,9 @@ class SimplePipelineExample(SimplePipeline):
         self.n = self.n + 1
 
     def stage2(self):
-        self.n = self.n << 1
+        localv = Signal(4)
+        self._pipe.comb += localv.eq(2)
+        self.n = self.n << localv
 
     def stage3(self):
         self.n = ~self.n
@@ -45,6 +47,6 @@ if __name__ == "__main__":
                     example.p._loopback,
         ])
 
-    print(verilog.convert(example, ports=[ 
-               example.p._loopback,
-             ]))
+    #print(verilog.convert(example, ports=[
+    #           example.p._loopback,
+    #         ]))